RTEMS  5.1
omap3.h
1 /*
2  * Copyright (c) 2012 Claas Ziemke. All rights reserved.
3  *
4  * Claas Ziemke
5  * Kernerstrasse 11
6  * 70182 Stuttgart
7  * Germany
8  * <claas.ziemke@gmx.net>
9  *
10  * The license and distribution terms for this file may be
11  * found in the file LICENSE in this distribution or at
12  * http://www.rtems.org/license/LICENSE.
13  *
14  * Modified by Ben Gras <beng@shrike-systems.com> to add lots
15  * of beagleboard/beaglebone definitions, delete lpc32xx specific
16  * ones, and merge with some other header files.
17  */
18 
19 /* Interrupt controller memory map */
20 #define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */
21 
22 /* Interrupt controller memory map */
23 #define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */
24 
25 /* Interrupt controller registers */
26 #define OMAP3_INTCPS_REVISION 0x000 /* IP revision code */
27 #define OMAP3_INTCPS_SYSCONFIG 0x010 /* Controls params */
28 #define OMAP3_INTCPS_SYSSTATUS 0x014 /* Status */
29 #define OMAP3_INTCPS_SIR_IRQ 0x040 /* Active IRQ number */
30 #define OMAP3_INTCPS_SIR_FIQ 0x044 /* Active FIQ number */
31 #define OMAP3_INTCPS_CONTROL 0x048 /* New int agreement bits */
32 #define OMAP3_INTCPS_PROTECTION 0x04C /* Protection for other regs */
33 #define OMAP3_INTCPS_IDLE 0x050 /* Clock auto-idle/gating */
34 #define OMAP3_INTCPS_IRQ_PRIORITY 0x060 /* Active IRQ priority level */
35 #define OMAP3_INTCPS_FIQ_PRIORITY 0x064 /* Active FIQ priority level */
36 #define OMAP3_INTCPS_THRESHOLD 0x068 /* Priority threshold */
37 #define OMAP3_INTCPS_ITR0 0x080 /* Raw pre-masking interrupt status */
38 #define OMAP3_INTCPS_MIR0 0x084 /* Interrupt mask */
39 #define OMAP3_INTCPS_MIR1 0x0A4 /* Interrupt mask */
40 #define OMAP3_INTCPS_MIR2 0x0C4 /* Interrupt mask */
41 #define OMAP3_INTCPS_MIR3 0x0E4 /* Interrupt mask */
42 #define OMAP3_INTCPS_MIR_CLEAR0 0x088 /* Clear interrupt mask bits */
43 #define OMAP3_INTCPS_MIR_SET0 0x08C /* Set interrupt mask bits */
44 #define OMAP3_INTCPS_ISR_SET0 0x090 /* Set software int bits */
45 #define OMAP3_INTCPS_ISR_CLEAR0 0x094 /* Clear software int bits */
46 #define OMAP3_INTCPS_PENDING_IRQ0 0x098 /* IRQ status post-masking */
47 #define OMAP3_INTCPS_PENDING_IRQ1 0x0b8 /* IRQ status post-masking */
48 #define OMAP3_INTCPS_PENDING_IRQ2 0x0d8 /* IRQ status post-masking */
49 #define OMAP3_INTCPS_PENDING_IRQ3 0x0f8 /* IRQ status post-masking */
50 #define OMAP3_INTCPS_PENDING_FIQ0 0x09C /* FIQ status post-masking */
51 #define OMAP3_INTCPS_ILR0 0x100 /* Priority for interrupts */
52 
53 /* SYSCONFIG */
54 #define OMAP3_SYSCONFIG_AUTOIDLE 0x01 /* SYSCONFIG.AUTOIDLE bit */
55 
56 #define OMAP3_INTR_ITR(base,n) \
57  (base + OMAP3_INTCPS_ITR0 + 0x20 * (n))
58 #define OMAP3_INTR_MIR(base,n) \
59  (base + OMAP3_INTCPS_MIR0 + 0x20 * (n))
60 #define OMAP3_INTR_MIR_CLEAR(base,n) \
61  (base + OMAP3_INTCPS_MIR_CLEAR0 + 0x20 * (n))
62 #define OMAP3_INTR_MIR_SET(base,n) \
63  (base + OMAP3_INTCPS_MIR_SET0 + 0x20 * (n))
64 #define OMAP3_INTR_ISR_SET(base,n) \
65  (base + OMAP3_INTCPS_ISR_SET0 + 0x20 * (n))
66 #define OMAP3_INTR_ISR_CLEAR(base,n) \
67  (base + OMAP3_INTCPS_ISR_CLEAR0 + 0x20 * (n))
68 #define OMAP3_INTR_PENDING_IRQ(base,n) \
69  (base + OMAP3_INTCPS_PENDING_IRQ0 + 0x20 * (n))
70 #define OMAP3_INTR_PENDING_FIQ(base,n) \
71  (base + OMAP3_INTCPS_PENDING_FIQ0 + 0x20 * (n))
72 #define OMAP3_INTR_ILR(base,m) \
73  (base + OMAP3_INTCPS_ILR0 + 0x4 * (m))
74 
75 #define OMAP3_INTR_SPURIOUSIRQ_MASK (0x1FFFFFF << 7) /* Spurious IRQ mask for SIR_IRQ */
76 #define OMAP3_INTR_ACTIVEIRQ_MASK 0x7F /* Active IRQ mask for SIR_IRQ */
77 #define OMAP3_INTR_NEWIRQAGR 0x1 /* New IRQ Generation */
78 
79 #define OMAP3_DM337X_NR_IRQ_VECTORS 96
80 
81 /* Interrupt mappings */
82 #define OMAP3_MCBSP2_ST_IRQ 4 /* Sidestone McBSP2 overflow */
83 #define OMAP3_MCBSP3_ST_IRQ 5 /* Sidestone McBSP3 overflow */
84 #define OMAP3_SYS_NIRQ 7 /* External source (active low) */
85 #define OMAP3_SMX_DBG_IRQ 9 /* L3 interconnect error for debug */
86 #define OMAP3_SMX_APP_IRQ 10 /* L3 interconnect error for application */
87 #define OMAP3_PRCM_IRQ 11 /* PRCM module */
88 #define OMAP3_SDMA0_IRQ 12 /* System DMA request 0 */
89 #define OMAP3_SDMA1_IRQ 13 /* System DMA request 1 */
90 #define OMAP3_SDMA2_IRQ 14 /* System DMA request 2 */
91 #define OMAP3_SDMA3_IRQ 15 /* System DMA request 3 */
92 #define OMAP3_MCBSP1_IRQ 16 /* McBSP module 1 */
93 #define OMAP3_MCBSP2_IRQ 17 /* McBSP module 2 */
94 #define OMAP3_GPMC_IRQ 20 /* General-purpose memory controller */
95 #define OMAP3_SGX_IRQ 21 /* 2D/3D graphics module */
96 #define OMAP3_MCBSP3_IRQ 22 /* McBSP module 3 */
97 #define OMAP3_MCBSP4_IRQ 23 /* McBSP module 4 */
98 #define OMAP3_CAM0_IRQ 24 /* Camera interface request 0 */
99 #define OMAP3_DSS_IRQ 25 /* Display subsystem module */
100 #define OMAP3_MAIL_U0_IRQ 26 /* Mailbox user 0 request */
101 #define OMAP3_MCBSP5_IRQ 27 /* McBSP module 5 */
102 #define OMAP3_IVA2_MMU_IRQ 28 /* IVA2 MMU */
103 #define OMAP3_GPIO1_IRQ 29 /* GPIO module 1 */
104 #define OMAP3_GPIO2_IRQ 30 /* GPIO module 2 */
105 #define OMAP3_GPIO3_IRQ 31 /* GPIO module 3 */
106 #define OMAP3_GPIO4_IRQ 32 /* GPIO module 4 */
107 #define OMAP3_GPIO5_IRQ 33 /* GPIO module 5 */
108 #define OMAP3_GPIO6_IRQ 34 /* GPIO module 6 */
109 #define OMAP3_WDT3_IRQ 36 /* Watchdog timer module 3 overflow */
110 #define OMAP3_GPT1_IRQ 37 /* General-purpose timer module 1 */
111 #define OMAP3_GPT2_IRQ 38 /* General-purpose timer module 2 */
112 #define OMAP3_GPT3_IRQ 39 /* General-purpose timer module 3 */
113 #define OMAP3_GPT4_IRQ 40 /* General-purpose timer module 4 */
114 #define OMAP3_GPT5_IRQ 41 /* General-purpose timer module 5 */
115 #define OMAP3_GPT6_IRQ 42 /* General-purpose timer module 6 */
116 #define OMAP3_GPT7_IRQ 43 /* General-purpose timer module 7 */
117 #define OMAP3_GPT8_IRQ 44 /* General-purpose timer module 8 */
118 #define OMAP3_GPT9_IRQ 45 /* General-purpose timer module 9 */
119 #define OMAP3_GPT10_IRQ 46 /* General-purpose timer module 10 */
120 #define OMAP3_GPT11_IRQ 47 /* General-purpose timer module 11 */
121 #define OMAP3_SPI4_IRQ 48 /* McSPI module 4 */
122 #define OMAP3_MCBSP4_TX_IRQ 54 /* McBSP module 4 transmit */
123 #define OMAP3_MCBSP4_RX_IRQ 55 /* McBSP module 4 receive */
124 #define OMAP3_I2C1_IRQ 56 /* I2C module 1 */
125 #define OMAP3_I2C2_IRQ 57 /* I2C module 2 */
126 #define OMAP3_HDQ_IRQ 58 /* HDQ/1-Wire */
127 #define OMAP3_MCBSP1_TX_IRQ 59 /* McBSP module 1 transmit */
128 #define OMAP3_MCBSP1_RX_IRQ 60 /* McBSP module 1 receive */
129 #define OMAP3_I2C3_IRQ 61 /* I2C module 3 */
130 #define OMAP3_MCBSP2_TX_IRQ 62 /* McBSP module 2 transmit */
131 #define OMAP3_MCBSP2_RX_IRQ 63 /* McBSP module 2 receive */
132 #define OMAP3_SPI1_IRQ 65 /* McSPI module 1 */
133 #define OMAP3_SPI2_IRQ 66 /* McSPI module 2 */
134 #define OMAP3_UART1_IRQ 72 /* UART module 1 */
135 #define OMAP3_UART2_IRQ 73 /* UART module 2 */
136 #define OMAP3_UART3_IRQ 74 /* UART module 3 */
137 #define OMAP3_PBIAS_IRQ 75 /* Merged interrupt for PBIASlite 1/2 */
138 #define OMAP3_OHCI_IRQ 76 /* OHCI HSUSB MP Host Interrupt */
139 #define OMAP3_EHCI_IRQ 77 /* EHCI HSUSB MP Host Interrupt */
140 #define OMAP3_TLL_IRQ 78 /* HSUSB MP TLL Interrupt */
141 #define OMAP3_MCBSP5_TX_IRQ 81 /* McBSP module 5 transmit */
142 #define OMAP3_MCBSP5_RX_IRQ 82 /* McBSP module 5 receive */
143 #define OMAP3_MMC1_IRQ 83 /* MMC/SD module 1 */
144 #define OMAP3_MMC2_IRQ 86 /* MMC/SD module 2 */
145 #define OMAP3_ICR_IRQ 87 /* MPU ICR */
146 #define OMAP3_D2DFRINT_IRQ 88 /* 3G coproc (in stacked modem config) */
147 #define OMAP3_MCBSP3_TX_IRQ 89 /* McBSP module 3 transmit */
148 #define OMAP3_MCBSP3_RX_IRQ 90 /* McBSP module 3 receive */
149 #define OMAP3_SPI3_IRQ 91 /* McSPI module 3 */
150 #define OMAP3_HSUSB_MC_IRQ 92 /* High-speed USB OTG */
151 #define OMAP3_HSUSB_DMA_IRQ 93 /* High-speed USB OTG DMA */
152 #define OMAP3_MMC3_IRQ 94 /* MMC/SD module 3 */
153 
154 /* General-purpose timer register map */
155 #define OMAP3_GPTIMER1_BASE 0x48318000
156  /* GPTIMER1 physical address */
157 #define OMAP3_GPTIMER2_BASE 0x49032000
158  /* GPTIMER2 physical address */
159 #define OMAP3_GPTIMER3_BASE 0x49034000
160  /* GPTIMER3 physical address */
161 #define OMAP3_GPTIMER4_BASE 0x49036000
162  /* GPTIMER4 physical address */
163 #define OMAP3_GPTIMER5_BASE 0x49038000
164  /* GPTIMER5 physical address */
165 #define OMAP3_GPTIMER6_BASE 0x4903A000
166  /* GPTIMER6 physical address */
167 #define OMAP3_GPTIMER7_BASE 0x4903C000
168  /* GPTIMER7 physical address */
169 #define OMAP3_GPTIMER8_BASE 0x4903E000
170  /* GPTIMER8 physical address */
171 #define OMAP3_GPTIMER9_BASE 0x49040000
172  /* GPTIMER9 physical address */
173 #define OMAP3_GPTIMER10_BASE 0x48086000
174  /* GPTIMER10 physical address */
175 #define OMAP3_GPTIMER11_BASE 0x48088000
176  /* GPTIMER11 physical address */
177 
178 
179 /* General-purpose timer registers */
180 #define OMAP3_TIMER_TIDR 0x000
181  /* IP revision code */
182 #define OMAP3_TIMER_TIOCP_CFG 0x010
183  /* Controls params for GP timer L4 iface */
184 #define OMAP3_TIMER_TISTAT 0x014
185  /* Status (excl. interrupt status) */
186 #define OMAP3_TIMER_TISR 0x018
187  /* Pending interrupt status */
188 #define OMAP3_TIMER_TIER 0x01C
189  /* Interrupt enable */
190 #define OMAP3_TIMER_TWER 0x020
191  /* Wakeup enable */
192 #define OMAP3_TIMER_TCLR 0x024
193  /* Controls optional features */
194 #define OMAP3_TIMER_TCRR 0x028
195  /* Internal counter value */
196 #define OMAP3_TIMER_TLDR 0x02C
197  /* Timer load value */
198 #define OMAP3_TIMER_TTGR 0x030
199  /* Triggers counter reload */
200 #define OMAP3_TIMER_TWPS 0x034
201  /* Indicates if Write-Posted pending */
202 #define OMAP3_TIMER_TMAR 0x038
203  /* Value to be compared with counter */
204 #define OMAP3_TIMER_TCAR1 0x03C
205  /* First captured value of counter reg */
206 #define OMAP3_TIMER_TSICR 0x040
207  /* Control posted mode and functional SW rst */
208 #define OMAP3_TIMER_TCAR2 0x044
209  /* Second captured value of counter register */
210 #define OMAP3_TIMER_TPIR 0x048
211  /* Positive increment (1 ms tick) */
212 #define OMAP3_TIMER_TNIR 0x04C
213  /* Negative increment (1 ms tick) */
214 #define OMAP3_TIMER_TCVR 0x050
215  /* Defines TCRR is sub/over-period (1 ms tick) */
216 #define OMAP3_TIMER_TOCR 0x054
217  /* Masks tick interrupt */
218 #define OMAP3_TIMER_TOWR 0x058
219  /* Number of masked overflow interrupts */
220 
221 /* Interrupt status register fields */
222 #define OMAP3_TISR_MAT_IT_FLAG (1 << 0) /* Pending match interrupt status */
223 #define OMAP3_TISR_OVF_IT_FLAG (1 << 1) /* Pending overflow interrupt status */
224 #define OMAP3_TISR_TCAR_IT_FLAG (1 << 2) /* Pending capture interrupt status */
225 
226 /* Interrupt enable register fields */
227 #define OMAP3_TIER_MAT_IT_ENA (1 << 0) /* Enable match interrupt */
228 #define OMAP3_TIER_OVF_IT_ENA (1 << 1) /* Enable overflow interrupt */
229 #define OMAP3_TIER_TCAR_IT_ENA (1 << 2) /* Enable capture interrupt */
230 
231 /* Timer control fields */
232 #define OMAP3_TCLR_ST (1 << 0) /* Start/stop timer */
233 #define OMAP3_TCLR_AR (1 << 1) /* Autoreload or one-shot mode */
234 #define OMAP3_TCLR_PRE (1 << 5) /* Prescaler on */
235 #define OMAP3_TCLR_PTV (1 << 1) /* looks like "bleed" from Minix */
236 #define OMAP3_TCLR_OVF_TRG (1 << 10) /* Overflow trigger */
237 
238 
239 #define OMAP3_CM_CLKSEL_GFX 0x48004b40
240 #define OMAP3_CM_CLKEN_PLL 0x48004d00
241 #define OMAP3_CM_FCLKEN1_CORE 0x48004A00
242 #define OMAP3_CM_CLKSEL_CORE 0x48004A40 /* GPT10 src clock sel. */
243 #define OMAP3_CM_FCLKEN_PER 0x48005000
244 #define OMAP3_CM_CLKSEL_PER 0x48005040
245 #define OMAP3_CM_CLKSEL_WKUP 0x48004c40 /* GPT1 source clock selection */
246 
247 
248 #define CM_MODULEMODE_MASK (0x3 << 0)
249 #define CM_MODULEMODE_ENABLE (0x2 << 0)
250 #define CM_MODULEMODE_DISABLED (0x0 << 0)
251 
252 #define CM_CLKCTRL_IDLEST (0x3 << 16)
253 #define CM_CLKCTRL_IDLEST_FUNC (0x0 << 16)
254 #define CM_CLKCTRL_IDLEST_TRANS (0x1 << 16)
255 #define CM_CLKCTRL_IDLEST_IDLE (0x2 << 16)
256 #define CM_CLKCTRL_IDLEST_DISABLE (0x3 << 16)
257 
258 #define CM_WKUP_BASE 0x44E00400 /* Clock Module Wakeup Registers */
259 
260 #define CM_WKUP_TIMER1_CLKCTRL (CM_WKUP_BASE + 0xC4)
261  /* This register manages the TIMER1 clocks. [Memory Mapped] */
262 
263 #define CM_PER_BASE 0x44E00000 /* Clock Module Peripheral Registers */
264 #define CM_PER_TIMER7_CLKCTRL (CM_PER_BASE + 0x7C)
265  /* This register manages the TIMER7 clocks. [Memory Mapped] */
266 
267 /* CM_DPLL registers */
268 
269 #define CM_DPLL_BASE 0x44E00500 /* Clock Module PLL Registers */
270 
271 #define CLKSEL_TIMER1MS_CLK (CM_DPLL_BASE + 0x28)
272 
273 #define CLKSEL_TIMER1MS_CLK_SEL_MASK (0x7 << 0)
274 #define CLKSEL_TIMER1MS_CLK_SEL_SEL1 (0x0 << 0)
275  /* Select CLK_M_OSC clock */
276 #define CLKSEL_TIMER1MS_CLK_SEL_SEL2 (0x1 << 0)
277  /* Select CLK_32KHZ clock */
278 #define CLKSEL_TIMER1MS_CLK_SEL_SEL3 (0x2 << 0)
279  /* Select TCLKIN clock */
280 #define CLKSEL_TIMER1MS_CLK_SEL_SEL4 (0x3 << 0)
281  /* Select CLK_RC32K clock */
282 #define CLKSEL_TIMER1MS_CLK_SEL_SEL5 (0x4 << 0)
283  /* Selects the CLK_32768 from 32KHz Crystal Osc */
284 
285 #define CLKSEL_TIMER7_CLK (CM_DPLL_BASE + 0x04)
286 #define CLKSEL_TIMER7_CLK_SEL_MASK (0x3 << 0)
287 #define CLKSEL_TIMER7_CLK_SEL_SEL1 (0x0 << 0) /* Select TCLKIN clock */
288 #define CLKSEL_TIMER7_CLK_SEL_SEL2 (0x1 << 0) /* Select CLK_M_OSC clock */
289 #define CLKSEL_TIMER7_CLK_SEL_SEL3 (0x2 << 0) /* Select CLK_32KHZ clock */
290 #define CLKSEL_TIMER7_CLK_SEL_SEL4 (0x3 << 0) /* Reserved */
291 
292 /*RTC CLOCK BASE & Registers*/
293 #define CM_RTC_BASE 0x44E00800
294 #define CM_RTC_RTC_CLKCTRL 0x0
295 #define CM_RTC_CLKSTCTRL 0x4
296 
297 
298 #define OMAP3_CLKSEL_GPT1 (1 << 0)
299 #define OMAP3_CLKSEL_GPT10 (1 << 6)
300 #define OMAP3_CLKSEL_GPT11 (1 << 7)
301 
302 #define OMAP34XX_CORE_L4_IO_BASE 0x48000000
303 
304 #define ARM_TTBR_ADDR_MASK (0xffffc000)
305 #define ARM_TTBR_OUTER_NC (0x0 << 3) /* Non-cacheable*/
306 #define ARM_TTBR_OUTER_WBWA (0x1 << 3) /* Outer Write-Back */
307 #define ARM_TTBR_OUTER_WT (0x2 << 3) /* Outer Write-Through */
308 #define ARM_TTBR_OUTER_WBNWA (0x3 << 3) /* Outer Write-Back */
309 #define ARM_TTBR_FLAGS_CACHED ARM_TTBR_OUTER_WBWA
310 
311 /* cpu control flags */
312 /* CPU control register (CP15 register 1) */
313 #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */
314 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
315 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */
316 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
317 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
318 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
319 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
320 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
321 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
322 #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */
323 #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */
324 #define CPU_CONTROL_SWP_ENABLE 0x00000400 /* SW: SWP{B} perform normally. */
325 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
326 #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */
327 #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */
328 #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */
329 #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */
330 #define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */
331 #define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */
332 #define CPU_CONTROL_XP_ENABLE 0x00800000 /* XP: extended page table */
333 #define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */
334 #define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */
335 #define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */
336 #define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: */
337 #define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access flag enable */
338 #define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */
339 
340 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
341 
342 /* VM bits */
343 
344 /* Big page (1MB section) specific flags. */
345 #define ARM_VM_SECTION (1 << 1)
346  /* 1MB section */
347 #define ARM_VM_SECTION_PRESENT (1 << 1)
348  /* Section is present */
349 #define ARM_VM_SECTION_B (1 << 2)
350  /* B Bit */
351 #define ARM_VM_SECTION_C (1 << 3)
352  /* C Bit */
353 #define ARM_VM_SECTION_DOMAIN (0xF << 5)
354  /* Domain Number */
355 #define ARM_VM_SECTION_SUPER (0x1 << 10)
356  /* Super access only AP[1:0] */
357 #define ARM_VM_SECTION_USER (0x3 << 10)
358  /* Super/User access AP[1:0] */
359 #define ARM_VM_SECTION_TEX0 (1 << 12)
360  /* TEX[0] */
361 #define ARM_VM_SECTION_TEX1 (1 << 13)
362  /* TEX[1] */
363 #define ARM_VM_SECTION_TEX2 (1 << 14)
364  /* TEX[2] */
365 #define ARM_VM_SECTION_RO (1 << 15)
366  /* Read only access AP[2] */
367 #define ARM_VM_SECTION_SHAREABLE (1 << 16)
368  /* Shareable */
369 #define ARM_VM_SECTION_NOTGLOBAL (1 << 17)
370  /* Not Global */
371 
372 #define ARM_VM_SECTION_WB \
373  (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_B )
374 /* inner and outer write-back, write-allocate */
375 #define ARM_VM_SECTION_WT \
376  (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX1 | ARM_VM_SECTION_C )
377 /* inner and outer write-through, no write-allocate */
378 #define ARM_VM_SECTION_WTWB \
379  (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_C )
380 /* Inner , Write through, No Write Allocate Outer - Write Back, Write Allocate */
381 
382 /* shareable device */
383 #define ARM_VM_SECTION_CACHED ARM_VM_SECTION_WTWB
384 #define ARM_VM_SECTION_DEVICE (ARM_VM_SECTION_B)
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