RTEMS  5.1
ns16550_p.h
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1 
6 /*
7  * COPYRIGHT (c) 1998 by Radstone Technology
8  *
9  *
10  * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
11  * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
12  * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
13  * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
14  *
15  * You are hereby granted permission to use, copy, modify, and distribute
16  * this file, provided that this notice, plus the above copyright notice
17  * and disclaimer, appears in all copies. Radstone Technology will provide
18  * no support for this code.
19  *
20  * COPYRIGHT (c) 1989-2012.
21  * On-Line Applications Research Corporation (OAR).
22  *
23  * The license and distribution terms for this file may be
24  * found in the file LICENSE in this distribution or at
25  * http://www.rtems.org/license/LICENSE.
26  */
27 
28 #ifndef _NS16550_P_H_
29 #define _NS16550_P_H_
30 
31 #ifndef ASM
32 #include <libchip/serial.h>
33 #endif
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
39 /*
40  * Define NS16550_STATIC to nothing while debugging so the entry points
41  * will show up in the symbol table.
42  */
43 
44 #define NS16550_STATIC static
45 
46 #define NS16550_RECEIVE_BUFFER 0
47 #define NS16550_TRANSMIT_BUFFER 0
48 #define NS16550_DIVISOR_LATCH_L 0
49 #define NS16550_INTERRUPT_ENABLE 1
50 #define NS16550_DIVISOR_LATCH_M 1
51 #define NS16550_INTERRUPT_ID 2
52 #define NS16550_FIFO_CONTROL 2
53 #define NS16550_LINE_CONTROL 3
54 #define NS16550_MODEM_CONTROL 4
55 #define NS16550_LINE_STATUS 5
56 #define NS16550_MODEM_STATUS 6
57 #define NS16550_SCRATCH_PAD 7
58 #define NS16550_FRACTIONAL_DIVIDER 10
59 
60 /*
61  * Define serial port interrupt enable register structure.
62  */
63 
64 #define SP_INT_RX_ENABLE 0x01
65 #define SP_INT_TX_ENABLE 0x02
66 #define SP_INT_LS_ENABLE 0x04
67 #define SP_INT_MS_ENABLE 0x08
68 
69 #define NS16550_ENABLE_ALL_INTR (SP_INT_RX_ENABLE | SP_INT_TX_ENABLE)
70 #define NS16550_DISABLE_ALL_INTR 0x00
71 #define NS16550_ENABLE_ALL_INTR_EXCEPT_TX (SP_INT_RX_ENABLE)
72 
73 /*
74  * Define serial port interrupt ID register structure.
75  */
76 
77 #define SP_IID_0 0x01
78 #define SP_IID_1 0x02
79 #define SP_IID_2 0x04
80 #define SP_IID_3 0x08
81 
82 /*
83  * Define serial port fifo control register structure.
84  */
85 
86 #define SP_FIFO_ENABLE 0x01
87 #define SP_FIFO_RXRST 0x02
88 #define SP_FIFO_TXRST 0x04
89 #define SP_FIFO_DMA 0x08
90 #define SP_FIFO_RXLEVEL 0xc0
91 
92 #define SP_FIFO_SIZE 16
93 
94 /*
95  * Define serial port line control register structure.
96  */
97 
98 #define SP_LINE_SIZE 0x03
99 #define SP_LINE_STOP 0x04
100 #define SP_LINE_PAR 0x08
101 #define SP_LINE_ODD 0x10
102 #define SP_LINE_STICK 0x20
103 #define SP_LINE_BREAK 0x40
104 #define SP_LINE_DLAB 0x80
105 
106 /*
107  * Line status register character size definitions.
108  */
109 
110 #define FIVE_BITS 0x0 /* five bits per character */
111 #define SIX_BITS 0x1 /* six bits per character */
112 #define SEVEN_BITS 0x2 /* seven bits per character */
113 #define EIGHT_BITS 0x3 /* eight bits per character */
114 
115 /*
116  * Define serial port modem control register structure.
117  */
118 
119 #define SP_MODEM_DTR 0x01
120 #define SP_MODEM_RTS 0x02
121 #define SP_MODEM_IRQ 0x08
122 #define SP_MODEM_LOOP 0x10
123 #define SP_MODEM_DIV4 0x80
124 
125 /*
126  * Define serial port line status register structure.
127  */
128 
129 #define SP_LSR_RDY 0x01
130 #define SP_LSR_EOVRUN 0x02
131 #define SP_LSR_EPAR 0x04
132 #define SP_LSR_EFRAME 0x08
133 #define SP_LSR_BREAK 0x10
134 #define SP_LSR_THOLD 0x20
135 #define SP_LSR_TX 0x40
136 #define SP_LSR_EFIFO 0x80
137 
138 #ifdef __cplusplus
139 }
140 #endif
141 
142 #endif /* _NS16550_P_H_ */
serial.h
The generic libchip serial driver interface.
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