RTEMS  5.1
mcf532x.h
1 /*
2  * File: mcf532x.h
3  * Purpose: Register and bit definitions
4  */
5 
6 #ifndef __MCF532X_H__
7 #define __MCF532X_H__
8 
9 /*********************************************************************
10 *
11 * Cache
12 *
13 *********************************************************************/
14 
15 #define MCF_CACR_CENB (1 << 31)
16 #define MCF_CACR_ESB (1 << 29)
17 #define MCF_CACR_DPI (1 << 28)
18 #define MCF_CACR_HLCK (1 << 27)
19 #define MCF_CACR_CINVA (1 << 24)
20 #define MCF_CACR_DNFB (1 << 10)
21 #define MCF_CACR_DCM(A) (((A) & 0x3) << 8)
22 #define MCF_CACR_DW (1 << 5)
23 #define MCF_CACR_EUSP (1 << 4)
24 
25 #define MCF_ACR_ADDR_BASE(A) (((A) & 0xFF) << 24)
26 #define MCF_ACR_ADDR_MASK(A) (((A) & 0xFF) << 16)
27 #define MCF_ACR_E (1 << 15)
28 #define MCF_ACR_S(A) (((A) & 0x3) << 13)
29 #define MCF_ACR_CM(A) (((A) & 0x3) << 5)
30 #define MCF_ACR_W (1 << 2)
31 
32 /*********************************************************************
33 *
34 * System Control Module (SCM)
35 *
36 *********************************************************************/
37 
38 /* Register read/write macros */
39 #define MCF_SCM_MPR0 (*(vuint32*)(0xEC000000))
40 #define MCF_SCM_MPR1 (*(vuint32*)(0xFC000000))
41 #define MCF_SCM_BMT0 (*(vuint32*)(0xEC000054))
42 #define MCF_SCM_BMT1 (*(vuint32*)(0xFC000054))
43 #define MCF_SCM_PACRA (*(vuint32*)(0xFC000020))
44 #define MCF_SCM_PACRB (*(vuint32*)(0xFC000024))
45 #define MCF_SCM_PACRC (*(vuint32*)(0xFC000028))
46 #define MCF_SCM_PACRD (*(vuint32*)(0xFC00002C))
47 #define MCF_SCM_PACRE (*(vuint32*)(0xFC000040))
48 #define MCF_SCM_PACRF (*(vuint32*)(0xFC000044))
49 #define MCF_SCM_PACRG (*(vuint32*)(0xEC000048))
50 #define MCF_SCM_PACRH (*(vuint32*)(0xEC000040))
51 #define MCF_SCM_CWCR (*(vuint16*)(0xFC040016))
52 #define MCF_SCM_CWSR (*(vuint8 *)(0xFC04001B))
53 #define MCF_SCM_CWIR (*(vuint8 *)(0xFC04001F))
54 #define MCF_SCM_BCR (*(vuint32*)(0xFC040024))
55 #define MCF_SCM_CFADR (*(vuint32*)(0xFC040070))
56 #define MCF_SCM_CFIER (*(vuint8 *)(0xFC040075))
57 #define MCF_SCM_CFLOC (*(vuint8 *)(0xFC040076))
58 #define MCF_SCM_CFATR (*(vuint8 *)(0xFC040077))
59 #define MCF_SCM_CFDTR (*(vuint32*)(0xFC04007C))
60 
61 /* Bit definitions and macros for MCF_SCM_MPR */
62 #define MCF_SCM_MPR_MPROT6(x) (((x)&0x0000000F)<<4)
63 #define MCF_SCM_MPR_MPROT5(x) (((x)&0x0000000F)<<8)
64 #define MCF_SCM_MPR_MPROT4(x) (((x)&0x0000000F)<<12)
65 #define MCF_SCM_MPR_MPROT2(x) (((x)&0x0000000F)<<20)
66 #define MCF_SCM_MPR_MPROT1(x) (((x)&0x0000000F)<<24)
67 #define MCF_SCM_MPR_MPROT0(x) (((x)&0x0000000F)<<28)
68 #define MCF_SCM_MPR_MPROT_MTR (0x4)
69 #define MCF_SCM_MPR_MPROT_MTW (0x2)
70 #define MCF_SCM_MPR_MPROT_MPL (0x1)
71 
72 /* Bit definitions and macros for MCF_SCM_BMT */
73 #define MCF_SCM_BMT_BMT(x) (((x)&0x00000007)<<0)
74 #define MCF_SCM_BMT_BME (0x00000008)
75 #define MCF_SCM_BMT_BMT_1024 (0x00000000)
76 #define MCF_SCM_BMT_BMT_512 (0x00000001)
77 #define MCF_SCM_BMT_BMT_256 (0x00000002)
78 #define MCF_SCM_BMT_BMT_128 (0x00000003)
79 #define MCF_SCM_BMT_BMT_64 (0x00000004)
80 #define MCF_SCM_BMT_BMT_32 (0x00000005)
81 #define MCF_SCM_BMT_BMT_16 (0x00000006)
82 #define MCF_SCM_BMT_BMT_8 (0x00000007)
83 
84 /* Bit definitions and macros for MCF_SCM_PACRA */
85 #define MCF_SCM_PACRA_PACR2(x) (((x)&0x0000000F)<<20)
86 #define MCF_SCM_PACRA_PACR1(x) (((x)&0x0000000F)<<24)
87 #define MCF_SCM_PACRA_PACR0(x) (((x)&0x0000000F)<<28)
88 #define MCF_SCM_PACRA_PACR_SP (0x4)
89 #define MCF_SCM_PACRA_PACR_WP (0x2)
90 #define MCF_SCM_PACRA_PACR_TP (0x1)
91 
92 /* Bit definitions and macros for MCF_SCM_PACRB */
93 #define MCF_SCM_PACRB_PACR12(x) (((x)&0x0000000F)<<12)
94 #define MCF_SCM_PACRB_PACR8(x) (((x)&0x0000000F)<<28)
95 
96 /* Bit definitions and macros for MCF_SCM_PACRC */
97 #define MCF_SCM_PACRC_PACR23(x) (((x)&0x0000000F)<<0)
98 #define MCF_SCM_PACRC_PACR22(x) (((x)&0x0000000F)<<4)
99 #define MCF_SCM_PACRC_PACR21(x) (((x)&0x0000000F)<<8)
100 #define MCF_SCM_PACRC_PACR19(x) (((x)&0x0000000F)<<16)
101 #define MCF_SCM_PACRC_PACR18(x) (((x)&0x0000000F)<<20)
102 #define MCF_SCM_PACRC_PACR17(x) (((x)&0x0000000F)<<24)
103 #define MCF_SCM_PACRC_PACR16(x) (((x)&0x0000000F)<<28)
104 
105 /* Bit definitions and macros for MCF_SCM_PACRD */
106 #define MCF_SCM_PACRD_PACR31(x) (((x)&0x0000000F)<<0)
107 #define MCF_SCM_PACRD_PACR30(x) (((x)&0x0000000F)<<4)
108 #define MCF_SCM_PACRD_PACR29(x) (((x)&0x0000000F)<<8)
109 #define MCF_SCM_PACRD_PACR28(x) (((x)&0x0000000F)<<12)
110 #define MCF_SCM_PACRD_PACR26(x) (((x)&0x0000000F)<<20)
111 #define MCF_SCM_PACRD_PACR25(x) (((x)&0x0000000F)<<24)
112 #define MCF_SCM_PACRD_PACR24(x) (((x)&0x0000000F)<<28)
113 
114 /* Bit definitions and macros for MCF_SCM_PACRE */
115 #define MCF_SCM_PACRE_PACR38(x) (((x)&0x0000000F)<<4)
116 #define MCF_SCM_PACRE_PACR37(x) (((x)&0x0000000F)<<8)
117 #define MCF_SCM_PACRE_PACR36(x) (((x)&0x0000000F)<<12)
118 #define MCF_SCM_PACRE_PACR35(x) (((x)&0x0000000F)<<16)
119 #define MCF_SCM_PACRE_PACR34(x) (((x)&0x0000000F)<<20)
120 #define MCF_SCM_PACRE_PACR33(x) (((x)&0x0000000F)<<24)
121 #define MCF_SCM_PACRE_PACR32(x) (((x)&0x0000000F)<<28)
122 
123 /* Bit definitions and macros for MCF_SCM_PACRF */
124 #define MCF_SCM_PACRF_PACR47(x) (((x)&0x0000000F)<<0)
125 #define MCF_SCM_PACRF_PACR46(x) (((x)&0x0000000F)<<4)
126 #define MCF_SCM_PACRF_PACR45(x) (((x)&0x0000000F)<<8)
127 #define MCF_SCM_PACRF_PACR44(x) (((x)&0x0000000F)<<12)
128 #define MCF_SCM_PACRF_PACR43(x) (((x)&0x0000000F)<<16)
129 #define MCF_SCM_PACRF_PACR42(x) (((x)&0x0000000F)<<20)
130 #define MCF_SCM_PACRF_PACR41(x) (((x)&0x0000000F)<<24)
131 #define MCF_SCM_PACRF_PACR40(x) (((x)&0x0000000F)<<28)
132 
133 /* Bit definitions and macros for MCF_SCM_PACRG */
134 #define MCF_SCM_PACRG_PACR48(x) (((x)&0x0000000F)<<28)
135 
136 /* Bit definitions and macros for MCF_SCM_PACRH */
137 #define MCF_SCM_PACRH_PACR58(x) (((x)&0x0000000F)<<20)
138 #define MCF_SCM_PACRH_PACR57(x) (((x)&0x0000000F)<<24)
139 #define MCF_SCM_PACRH_PACR56(x) (((x)&0x0000000F)<<28)
140 
141 /* Bit definitions and macros for MCF_SCM_CWCR */
142 #define MCF_SCM_CWCR_CWT(x) (((x)&0x001F)<<0)
143 #define MCF_SCM_CWCR_CWRI(x) (((x)&0x0003)<<5)
144 #define MCF_SCM_CWCR_CWE (0x0080)
145 #define MCF_SCM_CWCR_CWR_WH (0x0100)
146 #define MCF_SCM_CWCR_RO (0x8000)
147 #define MCF_SCM_CWCR_CWRI_INT (0x0000)
148 #define MCF_SCM_CWCR_CWRI_INT_THEN_RESET (0x0020)
149 #define MCF_SCM_CWCR_CWRI_RESET (0x0040)
150 #define MCF_SCM_CWCR_CWRI_WINDOW (0x0060)
151 
152 /* Bit definitions and macros for MCF_SCM_CWSR */
153 #define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0)
154 
155 /* Bit definitions and macros for MCF_SCM_CWIR */
156 #define MCF_SCM_CWIR_CWIC (0x01)
157 #define MCF_SCM_CWIR_CFEI (0x02)
158 
159 /* Bit definitions and macros for MCF_SCM_BCR */
160 #define MCF_SCM_BCR_S1 (0x00000002)
161 #define MCF_SCM_BCR_S4 (0x00000010)
162 #define MCF_SCM_BCR_S6 (0x00000040)
163 #define MCF_SCM_BCR_S7 (0x00000080)
164 #define MCF_SCM_BCR_GBW (0x00000100)
165 #define MCF_SCM_BCR_GBR (0x00000200)
166 
167 /* Bit definitions and macros for MCF_SCM_CFADR */
168 #define MCF_SCM_CFADR_ADDR(x) (((x)&0xFFFFFFFF)<<0)
169 
170 /* Bit definitions and macros for MCF_SCM_CFIER */
171 #define MCF_SCM_CFIER_ECFEI (0x01)
172 
173 /* Bit definitions and macros for MCF_SCM_CFLOC */
174 #define MCF_SCM_CFLOC_LOC (0x80)
175 
176 /* Bit definitions and macros for MCF_SCM_CFATR */
177 #define MCF_SCM_CFATR_TYPE (0x01)
178 #define MCF_SCM_CFATR_MODE (0x02)
179 #define MCF_SCM_CFATR_CACHE (0x08)
180 #define MCF_SCM_CFATR_SIZE(x) (((x)&0x07)<<4)
181 #define MCF_SCM_CFATR_WRITE (0x80)
182 
183 /* Bit definitions and macros for MCF_SCM_CFDTR */
184 #define MCF_SCM_CFDTR_CFDTR(x) (((x)&0xFFFFFFFF)<<0)
185 
186 /*********************************************************************
187 *
188 * Message Digest Hardware Accelerator (MDHA)
189 *
190 *********************************************************************/
191 
192 /* Register read/write macros */
193 #define MCF_MDHA_MDMR (*(vuint32*)(0xEC080000))
194 #define MCF_MDHA_MDCR (*(vuint32*)(0xEC080004))
195 #define MCF_MDHA_MDCMR (*(vuint32*)(0xEC080008))
196 #define MCF_MDHA_MDSR (*(vuint32*)(0xEC08000C))
197 #define MCF_MDHA_MDISR (*(vuint32*)(0xEC080010))
198 #define MCF_MDHA_MDIMR (*(vuint32*)(0xEC080014))
199 #define MCF_MDHA_MDDSR (*(vuint32*)(0xEC08001C))
200 #define MCF_MDHA_MDIN (*(vuint32*)(0xEC080020))
201 #define MCF_MDHA_MDA0 (*(vuint32*)(0xEC080030))
202 #define MCF_MDHA_MDB0 (*(vuint32*)(0xEC080034))
203 #define MCF_MDHA_MDC0 (*(vuint32*)(0xEC080038))
204 #define MCF_MDHA_MDD0 (*(vuint32*)(0xEC08003C))
205 #define MCF_MDHA_MDE0 (*(vuint32*)(0xEC080040))
206 #define MCF_MDHA_MDMDS (*(vuint32*)(0xEC080044))
207 #define MCF_MDHA_MDA1 (*(vuint32*)(0xEC080070))
208 #define MCF_MDHA_MDB1 (*(vuint32*)(0xEC080074))
209 #define MCF_MDHA_MDC1 (*(vuint32*)(0xEC080078))
210 #define MCF_MDHA_MDD1 (*(vuint32*)(0xEC08007C))
211 #define MCF_MDHA_MDE1 (*(vuint32*)(0xEC080080))
212 
213 /* Bit definitions and macros for MCF_MDHA_MDMR */
214 #define MCF_MDHA_MDMR_ALG (0x00000001)
215 #define MCF_MDHA_MDMR_PDATA (0x00000004)
216 #define MCF_MDHA_MDMR_MAC(x) (((x)&0x00000003)<<3)
217 #define MCF_MDHA_MDMR_INIT (0x00000020)
218 #define MCF_MDHA_MDMR_IPAD (0x00000040)
219 #define MCF_MDHA_MDMR_OPAD (0x00000080)
220 #define MCF_MDHA_MDMR_SWAP (0x00000100)
221 #define MCF_MDHA_MDMR_MACFULL (0x00000200)
222 #define MCF_MDHA_MDMR_SSL (0x00000400)
223 
224 /* Bit definitions and macros for MCF_MDHA_MDCR */
225 #define MCF_MDHA_MDCR_IE (0x00000001)
226 #define MCF_MDHA_MDCR_DMA (0x00000002)
227 #define MCF_MDHA_MDCR_ENDIAN (0x00000004)
228 #define MCF_MDHA_MDCR_DMAL(x) (((x)&0x0000001F)<<16)
229 
230 /* Bit definitions and macros for MCF_MDHA_MDCMR */
231 #define MCF_MDHA_MDCMR_SWR (0x00000001)
232 #define MCF_MDHA_MDCMR_RI (0x00000002)
233 #define MCF_MDHA_MDCMR_CI (0x00000004)
234 #define MCF_MDHA_MDCMR_GO (0x00000008)
235 
236 /* Bit definitions and macros for MCF_MDHA_MDSR */
237 #define MCF_MDHA_MDSR_INT (0x00000001)
238 #define MCF_MDHA_MDSR_DONE (0x00000002)
239 #define MCF_MDHA_MDSR_ERR (0x00000004)
240 #define MCF_MDHA_MDSR_RD (0x00000008)
241 #define MCF_MDHA_MDSR_BUSY (0x00000010)
242 #define MCF_MDHA_MDSR_END (0x00000020)
243 #define MCF_MDHA_MDSR_HSH (0x00000040)
244 #define MCF_MDHA_MDSR_GNW (0x00000080)
245 #define MCF_MDHA_MDSR_FS(x) (((x)&0x00000007)<<8)
246 #define MCF_MDHA_MDSR_APD(x) (((x)&0x00000007)<<13)
247 #define MCF_MDHA_MDSR_IFL(x) (((x)&0x000000FF)<<16)
248 
249 /* Bit definitions and macros for MCF_MDHA_MDISR */
250 #define MCF_MDHA_MDISR_IFO (0x00000001)
251 #define MCF_MDHA_MDISR_NON (0x00000004)
252 #define MCF_MDHA_MDISR_IME (0x00000010)
253 #define MCF_MDHA_MDISR_IDS (0x00000020)
254 #define MCF_MDHA_MDISR_RMDP (0x00000080)
255 #define MCF_MDHA_MDISR_ERE (0x00000100)
256 #define MCF_MDHA_MDISR_GTDS (0x00000200)
257 
258 /* Bit definitions and macros for MCF_MDHA_MDIMR */
259 #define MCF_MDHA_MDIMR_IFO (0x00000001)
260 #define MCF_MDHA_MDIMR_NON (0x00000004)
261 #define MCF_MDHA_MDIMR_IME (0x00000010)
262 #define MCF_MDHA_MDIMR_IDS (0x00000020)
263 #define MCF_MDHA_MDIMR_RMDP (0x00000080)
264 #define MCF_MDHA_MDIMR_ERE (0x00000100)
265 #define MCF_MDHA_MDIMR_GTDS (0x00000200)
266 
267 /* Bit definitions and macros for MCF_MDHA_MDDSR */
268 #define MCF_MDHA_MDDSR_DATASIZE(x) (((x)&0x1FFFFFFF)<<0)
269 
270 /* Bit definitions and macros for MCF_MDHA_MDIN */
271 #define MCF_MDHA_MDIN_DATAIN(x) (((x)&0xFFFFFFFF)<<0)
272 
273 /* Bit definitions and macros for MCF_MDHA_MDA0 */
274 #define MCF_MDHA_MDA0_DATA(x) (((x)&0xFFFFFFFF)<<0)
275 
276 /* Bit definitions and macros for MCF_MDHA_MDB0 */
277 #define MCF_MDHA_MDB0_DATA(x) (((x)&0xFFFFFFFF)<<0)
278 
279 /* Bit definitions and macros for MCF_MDHA_MDC0 */
280 #define MCF_MDHA_MDC0_DATA(x) (((x)&0xFFFFFFFF)<<0)
281 
282 /* Bit definitions and macros for MCF_MDHA_MDD0 */
283 #define MCF_MDHA_MDD0_DATA(x) (((x)&0xFFFFFFFF)<<0)
284 
285 /* Bit definitions and macros for MCF_MDHA_MDE0 */
286 #define MCF_MDHA_MDE0_DATA(x) (((x)&0xFFFFFFFF)<<0)
287 
288 /* Bit definitions and macros for MCF_MDHA_MDMDS */
289 #define MCF_MDHA_MDMDS_DATASIZE(x) (((x)&0xFFFFFFFF)<<0)
290 
291 /* Bit definitions and macros for MCF_MDHA_MDA1 */
292 #define MCF_MDHA_MDA1_DATA(x) (((x)&0xFFFFFFFF)<<0)
293 
294 /* Bit definitions and macros for MCF_MDHA_MDB1 */
295 #define MCF_MDHA_MDB1_DATA(x) (((x)&0xFFFFFFFF)<<0)
296 
297 /* Bit definitions and macros for MCF_MDHA_MDC1 */
298 #define MCF_MDHA_MDC1_DATA(x) (((x)&0xFFFFFFFF)<<0)
299 
300 /* Bit definitions and macros for MCF_MDHA_MDD1 */
301 #define MCF_MDHA_MDD1_DATA(x) (((x)&0xFFFFFFFF)<<0)
302 
303 /* Bit definitions and macros for MCF_MDHA_MDE1 */
304 #define MCF_MDHA_MDE1_DATA(x) (((x)&0xFFFFFFFF)<<0)
305 
306 /*********************************************************************
307 *
308 * Symmetric Key Hardware Accelerator (SKHA)
309 *
310 *********************************************************************/
311 
312 /* Register read/write macros */
313 #define MCF_SKHA_SKMR (*(vuint32*)(0xEC084000))
314 #define MCF_SKHA_SKCR (*(vuint32*)(0xEC084004))
315 #define MCF_SKHA_SKCMR (*(vuint32*)(0xEC084008))
316 #define MCF_SKHA_SKSR (*(vuint32*)(0xEC08400C))
317 #define MCF_SKHA_SKISR (*(vuint32*)(0xEC084010))
318 #define MCF_SKHA_SKIMR (*(vuint32*)(0xEC084014))
319 #define MCF_SKHA_SKKSR (*(vuint32*)(0xEC084018))
320 #define MCF_SKHA_SKDSR (*(vuint32*)(0xEC08401C))
321 #define MCF_SKHA_SKIN (*(vuint32*)(0xEC084020))
322 #define MCF_SKHA_SKOUT (*(vuint32*)(0xEC084024))
323 #define MCF_SKHA_SKK0 (*(vuint32*)(0xEC084030))
324 #define MCF_SKHA_SKK1 (*(vuint32*)(0xEC084034))
325 #define MCF_SKHA_SKK2 (*(vuint32*)(0xEC084038))
326 #define MCF_SKHA_SKK3 (*(vuint32*)(0xEC08403C))
327 #define MCF_SKHA_SKK4 (*(vuint32*)(0xEC084040))
328 #define MCF_SKHA_SKK5 (*(vuint32*)(0xEC084044))
329 #define MCF_SKHA_SKK(x) (*(vuint32*)(0xEC084030+((x)*0x004)))
330 #define MCF_SKHA_SKC0 (*(vuint32*)(0xEC084070))
331 #define MCF_SKHA_SKC1 (*(vuint32*)(0xEC084074))
332 #define MCF_SKHA_SKC2 (*(vuint32*)(0xEC084078))
333 #define MCF_SKHA_SKC3 (*(vuint32*)(0xEC08407C))
334 #define MCF_SKHA_SKC4 (*(vuint32*)(0xEC084080))
335 #define MCF_SKHA_SKC5 (*(vuint32*)(0xEC084084))
336 #define MCF_SKHA_SKC6 (*(vuint32*)(0xEC084088))
337 #define MCF_SKHA_SKC7 (*(vuint32*)(0xEC08408C))
338 #define MCF_SKHA_SKC8 (*(vuint32*)(0xEC084090))
339 #define MCF_SKHA_SKC9 (*(vuint32*)(0xEC084094))
340 #define MCF_SKHA_SKC10 (*(vuint32*)(0xEC084098))
341 #define MCF_SKHA_SKC11 (*(vuint32*)(0xEC08409C))
342 #define MCF_SKHA_SKC(x) (*(vuint32*)(0xEC084070+((x)*0x004)))
343 
344 /* Bit definitions and macros for MCF_SKHA_SKMR */
345 #define MCF_SKHA_SKMR_ALG(x) (((x)&0x00000003)<<0)
346 #define MCF_SKHA_SKMR_DIR (0x00000004)
347 #define MCF_SKHA_SKMR_CM(x) (((x)&0x00000003)<<3)
348 #define MCF_SKHA_SKMR_DKP (0x00000100)
349 #define MCF_SKHA_SKMR_CTRM(x) (((x)&0x0000000F)<<9)
350 #define MCF_SKHA_SKMR_CM_ECB (0x00000000)
351 #define MCF_SKHA_SKMR_CM_CBC (0x00000008)
352 #define MCF_SKHA_SKMR_CM_CTR (0x00000018)
353 #define MCF_SKHA_SKMR_DIR_DEC (0x00000000)
354 #define MCF_SKHA_SKMR_DIR_ENC (0x00000004)
355 #define MCF_SKHA_SKMR_ALG_AES (0x00000000)
356 #define MCF_SKHA_SKMR_ALG_DES (0x00000001)
357 #define MCF_SKHA_SKMR_ALG_TDES (0x00000002)
358 
359 /* Bit definitions and macros for MCF_SKHA_SKCR */
360 #define MCF_SKHA_SKCR_IE (0x00000001)
361 #define MCF_SKHA_SKCR_IDMA (0x00000002)
362 #define MCF_SKHA_SKCR_ODMA (0x00000004)
363 #define MCF_SKHA_SKCR_ENDIAN (0x00000008)
364 #define MCF_SKHA_SKCR_IDMAL(x) (((x)&0x0000003F)<<16)
365 #define MCF_SKHA_SKCR_ODMAL(x) (((x)&0x0000003F)<<24)
366 
367 /* Bit definitions and macros for MCF_SKHA_SKCMR */
368 #define MCF_SKHA_SKCMR_SWR (0x00000001)
369 #define MCF_SKHA_SKCMR_RI (0x00000002)
370 #define MCF_SKHA_SKCMR_CI (0x00000004)
371 #define MCF_SKHA_SKCMR_GO (0x00000008)
372 
373 /* Bit definitions and macros for MCF_SKHA_SKSR */
374 #define MCF_SKHA_SKSR_INT (0x00000001)
375 #define MCF_SKHA_SKSR_DONE (0x00000002)
376 #define MCF_SKHA_SKSR_ERR (0x00000004)
377 #define MCF_SKHA_SKSR_RD (0x00000008)
378 #define MCF_SKHA_SKSR_BUSY (0x00000010)
379 #define MCF_SKHA_SKSR_IFL(x) (((x)&0x000000FF)<<16)
380 #define MCF_SKHA_SKSR_OFL(x) (((x)&0x000000FF)<<24)
381 
382 /* Bit definitions and macros for MCF_SKHA_SKISR */
383 #define MCF_SKHA_SKISR_IFO (0x00000001)
384 #define MCF_SKHA_SKISR_OFU (0x00000002)
385 #define MCF_SKHA_SKISR_NEIF (0x00000004)
386 #define MCF_SKHA_SKISR_NEOF (0x00000008)
387 #define MCF_SKHA_SKISR_IME (0x00000010)
388 #define MCF_SKHA_SKISR_DSE (0x00000020)
389 #define MCF_SKHA_SKISR_KSE (0x00000040)
390 #define MCF_SKHA_SKISR_RMDP (0x00000080)
391 #define MCF_SKHA_SKISR_ERE (0x00000100)
392 #define MCF_SKHA_SKISR_KPE (0x00000200)
393 #define MCF_SKHA_SKISR_KRE (0x00000400)
394 #define MCF_SKHA_SKISR_DRL (0x00000800)
395 
396 /* Bit definitions and macros for MCF_SKHA_SKIMR */
397 #define MCF_SKHA_SKIMR_IFO (0x00000001)
398 #define MCF_SKHA_SKIMR_OFU (0x00000002)
399 #define MCF_SKHA_SKIMR_NEIF (0x00000004)
400 #define MCF_SKHA_SKIMR_NEOF (0x00000008)
401 #define MCF_SKHA_SKIMR_IME (0x00000010)
402 #define MCF_SKHA_SKIMR_DSE (0x00000020)
403 #define MCF_SKHA_SKIMR_KSE (0x00000040)
404 #define MCF_SKHA_SKIMR_RMDP (0x00000080)
405 #define MCF_SKHA_SKIMR_ERE (0x00000100)
406 #define MCF_SKHA_SKIMR_KPE (0x00000200)
407 #define MCF_SKHA_SKIMR_KRE (0x00000400)
408 #define MCF_SKHA_SKIMR_DRL (0x00000800)
409 
410 /* Bit definitions and macros for MCF_SKHA_SKKSR */
411 #define MCF_SKHA_SKKSR_KEYSIZE(x) (((x)&0x0000003F)<<0)
412 
413 /* Bit definitions and macros for MCF_SKHA_SKDSR */
414 #define MCF_SKHA_SKDSR_DATASIZE(x) (((x)&0xFFFFFFFF)<<0)
415 
416 /* Bit definitions and macros for MCF_SKHA_SKIN */
417 #define MCF_SKHA_SKIN_DATAIN(x) (((x)&0xFFFFFFFF)<<0)
418 
419 /* Bit definitions and macros for MCF_SKHA_SKOUT */
420 #define MCF_SKHA_SKOUT_DATAOUT(x) (((x)&0xFFFFFFFF)<<0)
421 
422 /* Bit definitions and macros for MCF_SKHA_SKK */
423 #define MCF_SKHA_SKK_KEY(x) (((x)&0xFFFFFFFF)<<0)
424 
425 /* Bit definitions and macros for MCF_SKHA_SKC */
426 #define MCF_SKHA_SKC_CONTEXT(x) (((x)&0xFFFFFFFF)<<0)
427 
428 /*********************************************************************
429 *
430 * Random Number Generator (RNG)
431 *
432 *********************************************************************/
433 
434 /* Register read/write macros */
435 #define MCF_RNG_RNGCR (*(vuint32*)(0xEC088000))
436 #define MCF_RNG_RNGSR (*(vuint32*)(0xEC088004))
437 #define MCF_RNG_RNGER (*(vuint32*)(0xEC088008))
438 #define MCF_RNG_RNGOUT (*(vuint32*)(0xEC08800C))
439 
440 /* Bit definitions and macros for MCF_RNG_RNGCR */
441 #define MCF_RNG_RNGCR_GO (0x00000001)
442 #define MCF_RNG_RNGCR_HA (0x00000002)
443 #define MCF_RNG_RNGCR_IM (0x00000004)
444 #define MCF_RNG_RNGCR_CI (0x00000008)
445 
446 /* Bit definitions and macros for MCF_RNG_RNGSR */
447 #define MCF_RNG_RNGSR_SV (0x00000001)
448 #define MCF_RNG_RNGSR_LRS (0x00000002)
449 #define MCF_RNG_RNGSR_FUF (0x00000004)
450 #define MCF_RNG_RNGSR_EI (0x00000008)
451 #define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8)
452 #define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16)
453 
454 /* Bit definitions and macros for MCF_RNG_RNGER */
455 #define MCF_RNG_RNGER_ENTROPY(x) (((x)&0xFFFFFFFF)<<0)
456 
457 /* Bit definitions and macros for MCF_RNG_RNGOUT */
458 #define MCF_RNG_RNGOUT_OUTPUT(x) (((x)&0xFFFFFFFF)<<0)
459 
460 /*********************************************************************
461 *
462 * Power Management Module (PMM)
463 *
464 *********************************************************************/
465 
466 /* Register read/write macros */
467 #define MCF_PMM_WCR (*(vuint8 *)(0xFC040013))
468 #define MCF_PMM_PPMSR0 (*(vuint8 *)(0xFC04002C))
469 #define MCF_PMM_PPMSR1 (*(vuint8 *)(0xFC04002E))
470 #define MCF_PMM_PPMCR0 (*(vuint8 *)(0xFC04002D))
471 #define MCF_PMM_PPMCR1 (*(vuint8 *)(0xFC04002F))
472 #define MCF_PMM_PPMHR0 (*(vuint32*)(0xFC040030))
473 #define MCF_PMM_PPMLR0 (*(vuint32*)(0xFC040034))
474 #define MCF_PMM_PPMHR1 (*(vuint32*)(0xFC040038))
475 #define MCF_PMM_LPCR (*(vuint8 *)(0xFC0A0007))
476 
477 /* Bit definitions and macros for MCF_PMM_WCR */
478 #define MCF_PMM_WCR_PRILVL(x) (((x)&0x07)<<0)
479 #define MCF_PMM_WCR_ENBWCR (0x80)
480 
481 /* Bit definitions and macros for MCF_PMM_PPMSR */
482 #define MCF_PMM_PPMSR_SMCD(x) (((x)&0x3F)<<0)
483 #define MCF_PMM_PPMSR_SAMCD (0x40)
484 
485 /* Bit definitions and macros for MCF_PMM_PPMCR */
486 #define MCF_PMM_PPMCR_CMCD(x) (((x)&0x3F)<<0)
487 #define MCF_PMM_PPMCR_CAMCD (0x40)
488 
489 /* Bit definitions and macros for MCF_PMM_PPMHR0 */
490 #define MCF_PMM_PPMHR0_CD32 (0x00000001)
491 #define MCF_PMM_PPMHR0_CD33 (0x00000002)
492 #define MCF_PMM_PPMHR0_CD34 (0x00000004)
493 #define MCF_PMM_PPMHR0_CD35 (0x00000008)
494 #define MCF_PMM_PPMHR0_CD36 (0x00000010)
495 #define MCF_PMM_PPMHR0_CD37 (0x00000020)
496 #define MCF_PMM_PPMHR0_CD38 (0x00000040)
497 #define MCF_PMM_PPMHR0_CD40 (0x00000100)
498 #define MCF_PMM_PPMHR0_CD41 (0x00000200)
499 #define MCF_PMM_PPMHR0_CD42 (0x00000400)
500 #define MCF_PMM_PPMHR0_CD43 (0x00000800)
501 #define MCF_PMM_PPMHR0_CD44 (0x00001000)
502 #define MCF_PMM_PPMHR0_CD45 (0x00002000)
503 #define MCF_PMM_PPMHR0_CD46 (0x00004000)
504 #define MCF_PMM_PPMHR0_CD47 (0x00008000)
505 #define MCF_PMM_PPMHR0_CD48 (0x00010000)
506 
507 /* Bit definitions and macros for MCF_PMM_PPMLR0 */
508 #define MCF_PMM_PPMLR0_CD2 (0x00000004)
509 #define MCF_PMM_PPMLR0_CD8 (0x00000100)
510 #define MCF_PMM_PPMLR0_CD12 (0x00001000)
511 #define MCF_PMM_PPMLR0_CD17 (0x00020000)
512 #define MCF_PMM_PPMLR0_CD18 (0x00040000)
513 #define MCF_PMM_PPMLR0_CD19 (0x00080000)
514 #define MCF_PMM_PPMLR0_CD21 (0x00200000)
515 #define MCF_PMM_PPMLR0_CD22 (0x00400000)
516 #define MCF_PMM_PPMLR0_CD23 (0x00800000)
517 #define MCF_PMM_PPMLR0_CD24 (0x01000000)
518 #define MCF_PMM_PPMLR0_CD25 (0x02000000)
519 #define MCF_PMM_PPMLR0_CD26 (0x04000000)
520 #define MCF_PMM_PPMLR0_CD28 (0x10000000)
521 #define MCF_PMM_PPMLR0_CD29 (0x20000000)
522 #define MCF_PMM_PPMLR0_CD30 (0x40000000)
523 #define MCF_PMM_PPMLR0_CD31 (0x80000000)
524 
525 /* Bit definitions and macros for MCF_PMM_PPMHR1 */
526 #define MCF_PMM_PPMHR1_CD32 (0x00000001)
527 #define MCF_PMM_PPMHR1_CD33 (0x00000002)
528 #define MCF_PMM_PPMHR1_CD34 (0x00000004)
529 
530 /* Bit definitions and macros for MCF_PMM_LPCR */
531 #define MCF_PMM_LPCR_STPMD(x) (((x)&0x03)<<3)
532 #define MCF_PMM_LPCR_FWKUP (0x20)
533 #define MCF_PMM_LPCR_LPMD(x) (((x)&0x03)<<6)
534 #define MCF_PMM_LPCR_LPMD_RUN (0x00)
535 #define MCF_PMM_LPCR_LPMD_DOZE (0x40)
536 #define MCF_PMM_LPCR_LPMD_WAIT (0x80)
537 #define MCF_PMM_LPCR_LPMD_STOP (0xC0)
538 #define MCF_PMM_LPCR_STPMD_SYS_DISABLED (0x00)
539 #define MCF_PMM_LPCR_STPMD_SYS_BUSCLK_DISABLED (0x04)
540 #define MCF_PMM_LPCR_STPMD_ONLY_OSC_ENABLED (0x08)
541 #define MCF_PMM_LPCR_STPMD_ALL_DISABLED (0x0C)
542 
543 /*********************************************************************
544 *
545 * Cross-bar switch (XBS)
546 *
547 *********************************************************************/
548 
549 /* Register read/write macros */
550 #define MCF_XBS_PRS1 (*(vuint32*)(0xFC004100))
551 #define MCF_XBS_PRS2 (*(vuint32*)(0xFC004200))
552 #define MCF_XBS_PRS3 (*(vuint32*)(0xFC004300))
553 #define MCF_XBS_PRS4 (*(vuint32*)(0xFC004400))
554 #define MCF_XBS_PRS5 (*(vuint32*)(0xFC004500))
555 #define MCF_XBS_PRS6 (*(vuint32*)(0xFC004600))
556 #define MCF_XBS_PRS7 (*(vuint32*)(0xFC004700))
557 #define MCF_XBS_PRS(x) (*(vuint32*)(0xFC004100+((x-1)*0x100)))
558 #define MCF_XBS_CRS1 (*(vuint32*)(0xFC004110))
559 #define MCF_XBS_CRS2 (*(vuint32*)(0xFC004210))
560 #define MCF_XBS_CRS3 (*(vuint32*)(0xFC004310))
561 #define MCF_XBS_CRS4 (*(vuint32*)(0xFC004410))
562 #define MCF_XBS_CRS5 (*(vuint32*)(0xFC004510))
563 #define MCF_XBS_CRS6 (*(vuint32*)(0xFC004610))
564 #define MCF_XBS_CRS7 (*(vuint32*)(0xFC004710))
565 #define MCF_XBS_CRS(x) (*(vuint32*)(0xFC004110+((x-1)*0x100)))
566 
567 /* Bit definitions and macros for MCF_XBS_PRS */
568 #define MCF_XBS_PRS_M0(x) (((x)&0x00000007)<<0)
569 #define MCF_XBS_PRS_M1(x) (((x)&0x00000007)<<4)
570 #define MCF_XBS_PRS_M2(x) (((x)&0x00000007)<<8)
571 #define MCF_XBS_PRS_M4(x) (((x)&0x00000007)<<16)
572 #define MCF_XBS_PRS_M5(x) (((x)&0x00000007)<<20)
573 #define MCF_XBS_PRS_M6(x) (((x)&0x00000007)<<24)
574 
575 /* Bit definitions and macros for MCF_XBS_CRS */
576 #define MCF_XBS_CRS_PARK(x) (((x)&0x00000007)<<0)
577 #define MCF_XBS_CRS_PCTL(x) (((x)&0x00000003)<<4)
578 #define MCF_XBS_CRS_ARB (0x00000100)
579 #define MCF_XBS_CRS_RO (0x80000000)
580 #define MCF_XBS_CRS_PCTL_PARK_FIELD (0x00000000)
581 #define MCF_XBS_CRS_PCTL_PARK_ON_LAST (0x00000010)
582 #define MCF_XBS_CRS_PCTL_PARK_NO_MASTER (0x00000020)
583 #define MCF_XBS_CRS_PCTL_PARK_CORE (0x00000000)
584 #define MCF_XBS_CRS_PCTL_PARK_EDMA (0x00000001)
585 #define MCF_XBS_CRS_PCTL_PARK_FEC (0x00000002)
586 
587 /*********************************************************************
588 *
589 * FlexBus Chip Selects (FBCS)
590 *
591 *********************************************************************/
592 
593 /* Register read/write macros */
594 #define MCF_FBCS0_CSAR (*(vuint32*)(0xFC008000))
595 #define MCF_FBCS0_CSMR (*(vuint32*)(0xFC008004))
596 #define MCF_FBCS0_CSCR (*(vuint32*)(0xFC008008))
597 #define MCF_FBCS1_CSAR (*(vuint32*)(0xFC00800C))
598 #define MCF_FBCS1_CSMR (*(vuint32*)(0xFC008010))
599 #define MCF_FBCS1_CSCR (*(vuint32*)(0xFC008014))
600 #define MCF_FBCS2_CSAR (*(vuint32*)(0xFC008018))
601 #define MCF_FBCS2_CSMR (*(vuint32*)(0xFC00801C))
602 #define MCF_FBCS2_CSCR (*(vuint32*)(0xFC008020))
603 #define MCF_FBCS3_CSAR (*(vuint32*)(0xFC008024))
604 #define MCF_FBCS3_CSMR (*(vuint32*)(0xFC008028))
605 #define MCF_FBCS3_CSCR (*(vuint32*)(0xFC00802C))
606 #define MCF_FBCS4_CSAR (*(vuint32*)(0xFC008030))
607 #define MCF_FBCS4_CSMR (*(vuint32*)(0xFC008034))
608 #define MCF_FBCS4_CSCR (*(vuint32*)(0xFC008038))
609 #define MCF_FBCS5_CSAR (*(vuint32*)(0xFC00803C))
610 #define MCF_FBCS5_CSMR (*(vuint32*)(0xFC008040))
611 #define MCF_FBCS5_CSCR (*(vuint32*)(0xFC008044))
612 #define MCF_FBCS_CSAR(x) (*(vuint32*)(0xFC008000+((x)*0x00C)))
613 #define MCF_FBCS_CSMR(x) (*(vuint32*)(0xFC008004+((x)*0x00C)))
614 #define MCF_FBCS_CSCR(x) (*(vuint32*)(0xFC008008+((x)*0x00C)))
615 
616 /* Bit definitions and macros for MCF_FBCS_CSAR */
617 #define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
618 
619 /* Bit definitions and macros for MCF_FBCS_CSMR */
620 #define MCF_FBCS_CSMR_V (0x00000001)
621 #define MCF_FBCS_CSMR_WP (0x00000100)
622 #define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16)
623 #define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
624 #define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
625 #define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
626 #define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
627 #define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
628 #define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000)
629 #define MCF_FBCS_CSMR_BAM_128M (0x07FF0000)
630 #define MCF_FBCS_CSMR_BAM_64M (0x03FF0000)
631 #define MCF_FBCS_CSMR_BAM_32M (0x01FF0000)
632 #define MCF_FBCS_CSMR_BAM_16M (0x00FF0000)
633 #define MCF_FBCS_CSMR_BAM_8M (0x007F0000)
634 #define MCF_FBCS_CSMR_BAM_4M (0x003F0000)
635 #define MCF_FBCS_CSMR_BAM_2M (0x001F0000)
636 #define MCF_FBCS_CSMR_BAM_1M (0x000F0000)
637 #define MCF_FBCS_CSMR_BAM_1024K (0x000F0000)
638 #define MCF_FBCS_CSMR_BAM_512K (0x00070000)
639 #define MCF_FBCS_CSMR_BAM_256K (0x00030000)
640 #define MCF_FBCS_CSMR_BAM_128K (0x00010000)
641 #define MCF_FBCS_CSMR_BAM_64K (0x00000000)
642 
643 /* Bit definitions and macros for MCF_FBCS_CSCR */
644 #define MCF_FBCS_CSCR_BSTW (0x00000008)
645 #define MCF_FBCS_CSCR_BSTR (0x00000010)
646 #define MCF_FBCS_CSCR_BEM (0x00000020)
647 #define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6)
648 #define MCF_FBCS_CSCR_AA (0x00000100)
649 #define MCF_FBCS_CSCR_SBM (0x00000200)
650 #define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10)
651 #define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16)
652 #define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18)
653 #define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20)
654 #define MCF_FBCS_CSCR_SWSEN (0x00800000)
655 #define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26)
656 #define MCF_FBCS_CSCR_PS_8 (0x00000040)
657 #define MCF_FBCS_CSCR_PS_16 (0x00000080)
658 #define MCF_FBCS_CSCR_PS_32 (0x00000000)
659 
660 /*********************************************************************
661 *
662 * FlexCAN Module (CAN)
663 *
664 *********************************************************************/
665 
666 /* Register read/write macros */
667 #define MCF_CAN_CANMCR (*(vuint32*)(0xFC020000))
668 #define MCF_CAN_CANCTRL (*(vuint32*)(0xFC020004))
669 #define MCF_CAN_TIMER (*(vuint32*)(0xFC020008))
670 #define MCF_CAN_RXGMASK (*(vuint32*)(0xFC020010))
671 #define MCF_CAN_RX14MASK (*(vuint32*)(0xFC020014))
672 #define MCF_CAN_RX15MASK (*(vuint32*)(0xFC020018))
673 #define MCF_CAN_ERRCNT (*(vuint32*)(0xFC02001C))
674 #define MCF_CAN_ERRSTAT (*(vuint32*)(0xFC020020))
675 #define MCF_CAN_IMASK (*(vuint32*)(0xFC020028))
676 #define MCF_CAN_IFLAG (*(vuint32*)(0xFC020030))
677 
678 /* Bit definitions and macros for MCF_CAN_CANMCR */
679 #define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0)
680 #define MCF_CAN_CANMCR_LPMACK (0x00100000)
681 #define MCF_CAN_CANMCR_SUPV (0x00800000)
682 #define MCF_CAN_CANMCR_FRZACK (0x01000000)
683 #define MCF_CAN_CANMCR_SOFTRST (0x02000000)
684 #define MCF_CAN_CANMCR_NOTRDY (0x08000000)
685 #define MCF_CAN_CANMCR_HALT (0x10000000)
686 #define MCF_CAN_CANMCR_FRZ (0x40000000)
687 #define MCF_CAN_CANMCR_MDIS (0x80000000)
688 
689 /* Bit definitions and macros for MCF_CAN_CANCTRL */
690 #define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0)
691 #define MCF_CAN_CANCTRL_LOM (0x00000008)
692 #define MCF_CAN_CANCTRL_LBUF (0x00000010)
693 #define MCF_CAN_CANCTRL_TSYNC (0x00000020)
694 #define MCF_CAN_CANCTRL_BOFFREC (0x00000040)
695 #define MCF_CAN_CANCTRL_SAMP (0x00000080)
696 #define MCF_CAN_CANCTRL_LPB (0x00001000)
697 #define MCF_CAN_CANCTRL_CLKSRC (0x00002000)
698 #define MCF_CAN_CANCTRL_ERRMSK (0x00004000)
699 #define MCF_CAN_CANCTRL_BOFFMSK (0x00008000)
700 #define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16)
701 #define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19)
702 #define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22)
703 #define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24)
704 
705 /* Bit definitions and macros for MCF_CAN_TIMER */
706 #define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0)
707 
708 /* Bit definitions and macros for MCF_CAN_RXGMASK */
709 #define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0)
710 
711 /* Bit definitions and macros for MCF_CAN_RX14MASK */
712 #define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
713 
714 /* Bit definitions and macros for MCF_CAN_RX15MASK */
715 #define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
716 
717 /* Bit definitions and macros for MCF_CAN_ERRCNT */
718 #define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0)
719 #define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8)
720 
721 /* Bit definitions and macros for MCF_CAN_ERRSTAT */
722 #define MCF_CAN_ERRSTAT_WAKINT (0x00000001)
723 #define MCF_CAN_ERRSTAT_ERRINT (0x00000002)
724 #define MCF_CAN_ERRSTAT_BOFFINT (0x00000004)
725 #define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4)
726 #define MCF_CAN_ERRSTAT_TXRX (0x00000040)
727 #define MCF_CAN_ERRSTAT_IDLE (0x00000080)
728 #define MCF_CAN_ERRSTAT_RXWRN (0x00000100)
729 #define MCF_CAN_ERRSTAT_TXWRN (0x00000200)
730 #define MCF_CAN_ERRSTAT_STFERR (0x00000400)
731 #define MCF_CAN_ERRSTAT_FRMERR (0x00000800)
732 #define MCF_CAN_ERRSTAT_CRCERR (0x00001000)
733 #define MCF_CAN_ERRSTAT_ACKERR (0x00002000)
734 #define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14)
735 #define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000)
736 #define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010)
737 #define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020)
738 
739 /* Bit definitions and macros for MCF_CAN_IMASK */
740 #define MCF_CAN_IMASK_BUF0M (0x00000001)
741 #define MCF_CAN_IMASK_BUF1M (0x00000002)
742 #define MCF_CAN_IMASK_BUF2M (0x00000004)
743 #define MCF_CAN_IMASK_BUF3M (0x00000008)
744 #define MCF_CAN_IMASK_BUF4M (0x00000010)
745 #define MCF_CAN_IMASK_BUF5M (0x00000020)
746 #define MCF_CAN_IMASK_BUF6M (0x00000040)
747 #define MCF_CAN_IMASK_BUF7M (0x00000080)
748 #define MCF_CAN_IMASK_BUF8M (0x00000100)
749 #define MCF_CAN_IMASK_BUF9M (0x00000200)
750 #define MCF_CAN_IMASK_BUF10M (0x00000400)
751 #define MCF_CAN_IMASK_BUF11M (0x00000800)
752 #define MCF_CAN_IMASK_BUF12M (0x00001000)
753 #define MCF_CAN_IMASK_BUF13M (0x00002000)
754 #define MCF_CAN_IMASK_BUF14M (0x00004000)
755 #define MCF_CAN_IMASK_BUF15M (0x00008000)
756 #define MCF_CAN_IMASK_BUF(x) (1<<x)
757 
758 /* Bit definitions and macros for MCF_CAN_IFLAG */
759 #define MCF_CAN_IFLAG_BUF0I (0x00000001)
760 #define MCF_CAN_IFLAG_BUF1I (0x00000002)
761 #define MCF_CAN_IFLAG_BUF2I (0x00000004)
762 #define MCF_CAN_IFLAG_BUF3I (0x00000008)
763 #define MCF_CAN_IFLAG_BUF4I (0x00000010)
764 #define MCF_CAN_IFLAG_BUF5I (0x00000020)
765 #define MCF_CAN_IFLAG_BUF6I (0x00000040)
766 #define MCF_CAN_IFLAG_BUF7I (0x00000080)
767 #define MCF_CAN_IFLAG_BUF8I (0x00000100)
768 #define MCF_CAN_IFLAG_BUF9I (0x00000200)
769 #define MCF_CAN_IFLAG_BUF10I (0x00000400)
770 #define MCF_CAN_IFLAG_BUF11I (0x00000800)
771 #define MCF_CAN_IFLAG_BUF12I (0x00001000)
772 #define MCF_CAN_IFLAG_BUF13I (0x00002000)
773 #define MCF_CAN_IFLAG_BUF14I (0x00004000)
774 #define MCF_CAN_IFLAG_BUF15I (0x00008000)
775 #define MCF_CAN_IFLAG_BUF(x) (1<<x)
776 
777 /*********************************************************************
778 *
779 * Fast Ethernet Controller (FEC)
780 *
781 *********************************************************************/
782 
783 /* Register read/write macros */
784 #define MCF_FEC_EIR (*(vuint32*)(0xFC030004))
785 #define MCF_FEC_EIMR (*(vuint32*)(0xFC030008))
786 #define MCF_FEC_RDAR (*(vuint32*)(0xFC030010))
787 #define MCF_FEC_TDAR (*(vuint32*)(0xFC030014))
788 #define MCF_FEC_ECR (*(vuint32*)(0xFC030024))
789 #define MCF_FEC_MMFR (*(vuint32*)(0xFC030040))
790 #define MCF_FEC_MSCR (*(vuint32*)(0xFC030044))
791 #define MCF_FEC_MIBC (*(vuint32*)(0xFC030064))
792 #define MCF_FEC_RCR (*(vuint32*)(0xFC030084))
793 #define MCF_FEC_TCR (*(vuint32*)(0xFC0300C4))
794 #define MCF_FEC_PALR (*(vuint32*)(0xFC0300E4))
795 #define MCF_FEC_PAUR (*(vuint32*)(0xFC0300E8))
796 #define MCF_FEC_OPD (*(vuint32*)(0xFC0300EC))
797 #define MCF_FEC_IAUR (*(vuint32*)(0xFC030118))
798 #define MCF_FEC_IALR (*(vuint32*)(0xFC03011C))
799 #define MCF_FEC_GAUR (*(vuint32*)(0xFC030120))
800 #define MCF_FEC_GALR (*(vuint32*)(0xFC030124))
801 #define MCF_FEC_TFWR (*(vuint32*)(0xFC030144))
802 #define MCF_FEC_FRBR (*(vuint32*)(0xFC03014C))
803 #define MCF_FEC_FRSR (*(vuint32*)(0xFC030150))
804 #define MCF_FEC_ERDSR (*(vuint32*)(0xFC030180))
805 #define MCF_FEC_ETDSR (*(vuint32*)(0xFC030184))
806 #define MCF_FEC_EMRBR (*(vuint32*)(0xFC030188))
807 #define MCF_FEC_RMON_T_DROP (*(vuint32*)(0xFC030200))
808 #define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(0xFC030204))
809 #define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(0xFC030208))
810 #define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(0xFC03020C))
811 #define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(0xFC030210))
812 #define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(0xFC030214))
813 #define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(0xFC030218))
814 #define MCF_FEC_RMON_T_FRAG (*(vuint32*)(0xFC03021C))
815 #define MCF_FEC_RMON_T_JAB (*(vuint32*)(0xFC030220))
816 #define MCF_FEC_RMON_T_COL (*(vuint32*)(0xFC030224))
817 #define MCF_FEC_RMON_T_P64 (*(vuint32*)(0xFC030228))
818 #define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(0xFC03022C))
819 #define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(0xFC030230))
820 #define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(0xFC030234))
821 #define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(0xFC030238))
822 #define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(0xFC03023C))
823 #define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(0xFC030240))
824 #define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(0xFC030244))
825 #define MCF_FEC_IEEE_T_DROP (*(vuint32*)(0xFC030248))
826 #define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(0xFC03024C))
827 #define MCF_FEC_IEEE_T_1COL (*(vuint32*)(0xFC030250))
828 #define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(0xFC030254))
829 #define MCF_FEC_IEEE_T_DEF (*(vuint32*)(0xFC030258))
830 #define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(0xFC03025C))
831 #define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(0xFC030260))
832 #define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(0xFC030264))
833 #define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(0xFC030268))
834 #define MCF_FEC_IEEE_T_SQE (*(vuint32*)(0xFC03026C))
835 #define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(0xFC030270))
836 #define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(0xFC030274))
837 #define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(0xFC030284))
838 #define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(0xFC030288))
839 #define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(0xFC03028C))
840 #define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(0xFC030290))
841 #define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(0xFC030294))
842 #define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(0xFC030298))
843 #define MCF_FEC_RMON_R_FRAG (*(vuint32*)(0xFC03029C))
844 #define MCF_FEC_RMON_R_JAB (*(vuint32*)(0xFC0302A0))
845 #define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(0xFC0302A4))
846 #define MCF_FEC_RMON_R_P64 (*(vuint32*)(0xFC0302A8))
847 #define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(0xFC0302AC))
848 #define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(0xFC0302B0))
849 #define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(0xFC0302B4))
850 #define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(0xFC0302B8))
851 #define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(0xFC0302C0))
852 #define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(0xFC0302BC))
853 #define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(0xFC0302C4))
854 #define MCF_FEC_IEEE_R_DROP (*(vuint32*)(0xFC0302C8))
855 #define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(0xFC0302CC))
856 #define MCF_FEC_IEEE_R_CRC (*(vuint32*)(0xFC0302D0))
857 #define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(0xFC0302D4))
858 #define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(0xFC0302D8))
859 #define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(0xFC0302DC))
860 #define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(0xFC0302E0))
861 
862 /* Bit definitions and macros for MCF_FEC_EIR */
863 #define MCF_FEC_EIR_UN (0x00080000)
864 #define MCF_FEC_EIR_RL (0x00100000)
865 #define MCF_FEC_EIR_LC (0x00200000)
866 #define MCF_FEC_EIR_EBERR (0x00400000)
867 #define MCF_FEC_EIR_MII (0x00800000)
868 #define MCF_FEC_EIR_RXB (0x01000000)
869 #define MCF_FEC_EIR_RXF (0x02000000)
870 #define MCF_FEC_EIR_TXB (0x04000000)
871 #define MCF_FEC_EIR_TXF (0x08000000)
872 #define MCF_FEC_EIR_GRA (0x10000000)
873 #define MCF_FEC_EIR_BABT (0x20000000)
874 #define MCF_FEC_EIR_BABR (0x40000000)
875 #define MCF_FEC_EIR_HBERR (0x80000000)
876 #define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF)
877 
878 /* Bit definitions and macros for MCF_FEC_EIMR */
879 #define MCF_FEC_EIMR_UN (0x00080000)
880 #define MCF_FEC_EIMR_RL (0x00100000)
881 #define MCF_FEC_EIMR_LC (0x00200000)
882 #define MCF_FEC_EIMR_EBERR (0x00400000)
883 #define MCF_FEC_EIMR_MII (0x00800000)
884 #define MCF_FEC_EIMR_RXB (0x01000000)
885 #define MCF_FEC_EIMR_RXF (0x02000000)
886 #define MCF_FEC_EIMR_TXB (0x04000000)
887 #define MCF_FEC_EIMR_TXF (0x08000000)
888 #define MCF_FEC_EIMR_GRA (0x10000000)
889 #define MCF_FEC_EIMR_BABT (0x20000000)
890 #define MCF_FEC_EIMR_BABR (0x40000000)
891 #define MCF_FEC_EIMR_HBERR (0x80000000)
892 #define MCF_FEC_EIMR_MASK_ALL (0x00000000)
893 #define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF)
894 
895 /* Bit definitions and macros for MCF_FEC_RDAR */
896 #define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000)
897 
898 /* Bit definitions and macros for MCF_FEC_TDAR */
899 #define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000)
900 
901 /* Bit definitions and macros for MCF_FEC_ECR */
902 #define MCF_FEC_ECR_RESET (0x00000001)
903 #define MCF_FEC_ECR_ETHER_EN (0x00000002)
904 
905 /* Bit definitions and macros for MCF_FEC_MMFR */
906 #define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0)
907 #define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16)
908 #define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18)
909 #define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23)
910 #define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28)
911 #define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30)
912 #define MCF_FEC_MMFR_ST_01 (0x40000000)
913 #define MCF_FEC_MMFR_OP_READ (0x20000000)
914 #define MCF_FEC_MMFR_OP_WRITE (0x10000000)
915 #define MCF_FEC_MMFR_TA_10 (0x00020000)
916 
917 /* Bit definitions and macros for MCF_FEC_MSCR */
918 #define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1)
919 #define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080)
920 
921 /* Bit definitions and macros for MCF_FEC_MIBC */
922 #define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
923 #define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
924 
925 /* Bit definitions and macros for MCF_FEC_RCR */
926 #define MCF_FEC_RCR_LOOP (0x00000001)
927 #define MCF_FEC_RCR_DRT (0x00000002)
928 #define MCF_FEC_RCR_MII_MODE (0x00000004)
929 #define MCF_FEC_RCR_PROM (0x00000008)
930 #define MCF_FEC_RCR_BC_REJ (0x00000010)
931 #define MCF_FEC_RCR_FCE (0x00000020)
932 #define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16)
933 
934 /* Bit definitions and macros for MCF_FEC_TCR */
935 #define MCF_FEC_TCR_GTS (0x00000001)
936 #define MCF_FEC_TCR_HBC (0x00000002)
937 #define MCF_FEC_TCR_FDEN (0x00000004)
938 #define MCF_FEC_TCR_TFC_PAUSE (0x00000008)
939 #define MCF_FEC_TCR_RFC_PAUSE (0x00000010)
940 
941 /* Bit definitions and macros for MCF_FEC_PALR */
942 #define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0)
943 
944 /* Bit definitions and macros for MCF_FEC_PAUR */
945 #define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0)
946 #define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16)
947 
948 /* Bit definitions and macros for MCF_FEC_OPD */
949 #define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
950 #define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
951 
952 /* Bit definitions and macros for MCF_FEC_IAUR */
953 #define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0)
954 
955 /* Bit definitions and macros for MCF_FEC_IALR */
956 #define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0)
957 
958 /* Bit definitions and macros for MCF_FEC_GAUR */
959 #define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0)
960 
961 /* Bit definitions and macros for MCF_FEC_GALR */
962 #define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0)
963 
964 /* Bit definitions and macros for MCF_FEC_TFWR */
965 #define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0)
966 
967 /* Bit definitions and macros for MCF_FEC_FRBR */
968 #define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2)
969 
970 /* Bit definitions and macros for MCF_FEC_FRSR */
971 #define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2)
972 
973 /* Bit definitions and macros for MCF_FEC_ERDSR */
974 #define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
975 
976 /* Bit definitions and macros for MCF_FEC_ETDSR */
977 #define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
978 
979 /* Bit definitions and macros for MCF_FEC_EMRBR */
980 #define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4)
981 
982 #define MCF_FEC_TxBD_R 0x8000
983 #define MCF_FEC_TxBD_BUSY 0x4000
984 #define MCF_FEC_TxBD_TO1 0x4000
985 #define MCF_FEC_TxBD_W 0x2000
986 #define MCF_FEC_TxBD_TO2 0x1000
987 #define MCF_FEC_TxBD_FIRST 0x1000
988 #define MCF_FEC_TxBD_L 0x0800
989 #define MCF_FEC_TxBD_TC 0x0400
990 #define MCF_FEC_TxBD_DEF 0x0200
991 #define MCF_FEC_TxBD_HB 0x0100
992 #define MCF_FEC_TxBD_LC 0x0080
993 #define MCF_FEC_TxBD_RL 0x0040
994 #define MCF_FEC_TxBD_UN 0x0002
995 #define MCF_FEC_TxBD_CSL 0x0001
996 #define MCF_FEC_RxBD_E 0x8000
997 #define MCF_FEC_RxBD_INUSE 0x4000
998 #define MCF_FEC_RxBD_R01 0x4000
999 #define MCF_FEC_RxBD_W 0x2000
1000 #define MCF_FEC_RxBD_R02 0x1000
1001 #define MCF_FEC_RxBD_L 0x0800
1002 #define MCF_FEC_RxBD_M 0x0100
1003 #define MCF_FEC_RxBD_BC 0x0080
1004 #define MCF_FEC_RxBD_MC 0x0040
1005 #define MCF_FEC_RxBD_LG 0x0020
1006 #define MCF_FEC_RxBD_NO 0x0010
1007 #define MCF_FEC_RxBD_CR 0x0004
1008 #define MCF_FEC_RxBD_OV 0x0002
1009 #define MCF_FEC_RxBD_TR 0x0001
1010 
1011 /*********************************************************************
1012 *
1013 * Enhanced DMA (EDMA)
1014 *
1015 *********************************************************************/
1016 
1017 /* Register read/write macros */
1018 #define MCF_EDMA_CR (*(vuint32*)(0xFC044000))
1019 #define MCF_EDMA_ES (*(vuint32*)(0xFC044004))
1020 #define MCF_EDMA_ERQ (*(vuint16*)(0xFC04400E))
1021 #define MCF_EDMA_EEI (*(vuint16*)(0xFC044016))
1022 #define MCF_EDMA_SERQ (*(vuint8 *)(0xFC044018))
1023 #define MCF_EDMA_CERQ (*(vuint8 *)(0xFC044019))
1024 #define MCF_EDMA_SEEI (*(vuint8 *)(0xFC04401A))
1025 #define MCF_EDMA_CEEI (*(vuint8 *)(0xFC04401B))
1026 #define MCF_EDMA_CINT (*(vuint8 *)(0xFC04401C))
1027 #define MCF_EDMA_CERR (*(vuint8 *)(0xFC04401D))
1028 #define MCF_EDMA_SSRT (*(vuint8 *)(0xFC04401E))
1029 #define MCF_EDMA_CDNE (*(vuint8 *)(0xFC04401F))
1030 #define MCF_EDMA_INT (*(vuint16*)(0xFC044026))
1031 #define MCF_EDMA_ERR (*(vuint16*)(0xFC04402E))
1032 #define MCF_EDMA_DCHPRI0 (*(vuint8 *)(0xFC044100))
1033 #define MCF_EDMA_DCHPRI1 (*(vuint8 *)(0xFC044101))
1034 #define MCF_EDMA_DCHPRI2 (*(vuint8 *)(0xFC044102))
1035 #define MCF_EDMA_DCHPRI3 (*(vuint8 *)(0xFC044103))
1036 #define MCF_EDMA_DCHPRI4 (*(vuint8 *)(0xFC044104))
1037 #define MCF_EDMA_DCHPRI5 (*(vuint8 *)(0xFC044105))
1038 #define MCF_EDMA_DCHPRI6 (*(vuint8 *)(0xFC044106))
1039 #define MCF_EDMA_DCHPRI7 (*(vuint8 *)(0xFC044107))
1040 #define MCF_EDMA_DCHPRI8 (*(vuint8 *)(0xFC044108))
1041 #define MCF_EDMA_DCHPRI9 (*(vuint8 *)(0xFC044109))
1042 #define MCF_EDMA_DCHPRI10 (*(vuint8 *)(0xFC04410A))
1043 #define MCF_EDMA_DCHPRI11 (*(vuint8 *)(0xFC04410B))
1044 #define MCF_EDMA_DCHPRI12 (*(vuint8 *)(0xFC04410C))
1045 #define MCF_EDMA_DCHPRI13 (*(vuint8 *)(0xFC04410D))
1046 #define MCF_EDMA_DCHPRI14 (*(vuint8 *)(0xFC04410E))
1047 #define MCF_EDMA_DCHPRI15 (*(vuint8 *)(0xFC04410F))
1048 #define MCF_EDMA_DCHPRI(x) (*(vuint8 *)(0xFC044100+((x)*0x001)))
1049 #define MCF_EDMA_TCD0_SADDR (*(vuint32*)(0xFC045000))
1050 #define MCF_EDMA_TCD1_SADDR (*(vuint32*)(0xFC045020))
1051 #define MCF_EDMA_TCD2_SADDR (*(vuint32*)(0xFC045040))
1052 #define MCF_EDMA_TCD3_SADDR (*(vuint32*)(0xFC045060))
1053 #define MCF_EDMA_TCD4_SADDR (*(vuint32*)(0xFC045080))
1054 #define MCF_EDMA_TCD5_SADDR (*(vuint32*)(0xFC0450A0))
1055 #define MCF_EDMA_TCD6_SADDR (*(vuint32*)(0xFC0450C0))
1056 #define MCF_EDMA_TCD7_SADDR (*(vuint32*)(0xFC0450E0))
1057 #define MCF_EDMA_TCD8_SADDR (*(vuint32*)(0xFC045100))
1058 #define MCF_EDMA_TCD9_SADDR (*(vuint32*)(0xFC045120))
1059 #define MCF_EDMA_TCD10_SADDR (*(vuint32*)(0xFC045140))
1060 #define MCF_EDMA_TCD11_SADDR (*(vuint32*)(0xFC045160))
1061 #define MCF_EDMA_TCD12_SADDR (*(vuint32*)(0xFC045180))
1062 #define MCF_EDMA_TCD13_SADDR (*(vuint32*)(0xFC0451A0))
1063 #define MCF_EDMA_TCD14_SADDR (*(vuint32*)(0xFC0451C0))
1064 #define MCF_EDMA_TCD15_SADDR (*(vuint32*)(0xFC0451E0))
1065 #define MCF_EDMA_TCD_SADDR(x) (*(vuint32*)(0xFC045000+((x)*0x020)))
1066 #define MCF_EDMA_TCD0_ATTR (*(vuint16*)(0xFC045004))
1067 #define MCF_EDMA_TCD1_ATTR (*(vuint16*)(0xFC045024))
1068 #define MCF_EDMA_TCD2_ATTR (*(vuint16*)(0xFC045044))
1069 #define MCF_EDMA_TCD3_ATTR (*(vuint16*)(0xFC045064))
1070 #define MCF_EDMA_TCD4_ATTR (*(vuint16*)(0xFC045084))
1071 #define MCF_EDMA_TCD5_ATTR (*(vuint16*)(0xFC0450A4))
1072 #define MCF_EDMA_TCD6_ATTR (*(vuint16*)(0xFC0450C4))
1073 #define MCF_EDMA_TCD7_ATTR (*(vuint16*)(0xFC0450E4))
1074 #define MCF_EDMA_TCD8_ATTR (*(vuint16*)(0xFC045104))
1075 #define MCF_EDMA_TCD9_ATTR (*(vuint16*)(0xFC045124))
1076 #define MCF_EDMA_TCD10_ATTR (*(vuint16*)(0xFC045144))
1077 #define MCF_EDMA_TCD11_ATTR (*(vuint16*)(0xFC045164))
1078 #define MCF_EDMA_TCD12_ATTR (*(vuint16*)(0xFC045184))
1079 #define MCF_EDMA_TCD13_ATTR (*(vuint16*)(0xFC0451A4))
1080 #define MCF_EDMA_TCD14_ATTR (*(vuint16*)(0xFC0451C4))
1081 #define MCF_EDMA_TCD15_ATTR (*(vuint16*)(0xFC0451E4))
1082 #define MCF_EDMA_TCD_ATTR(x) (*(vuint16*)(0xFC045004+((x)*0x020)))
1083 #define MCF_EDMA_TCD0_SOFF (*(vuint16*)(0xFC045006))
1084 #define MCF_EDMA_TCD1_SOFF (*(vuint16*)(0xFC045026))
1085 #define MCF_EDMA_TCD2_SOFF (*(vuint16*)(0xFC045046))
1086 #define MCF_EDMA_TCD3_SOFF (*(vuint16*)(0xFC045066))
1087 #define MCF_EDMA_TCD4_SOFF (*(vuint16*)(0xFC045086))
1088 #define MCF_EDMA_TCD5_SOFF (*(vuint16*)(0xFC0450A6))
1089 #define MCF_EDMA_TCD6_SOFF (*(vuint16*)(0xFC0450C6))
1090 #define MCF_EDMA_TCD7_SOFF (*(vuint16*)(0xFC0450E6))
1091 #define MCF_EDMA_TCD8_SOFF (*(vuint16*)(0xFC045106))
1092 #define MCF_EDMA_TCD9_SOFF (*(vuint16*)(0xFC045126))
1093 #define MCF_EDMA_TCD10_SOFF (*(vuint16*)(0xFC045146))
1094 #define MCF_EDMA_TCD11_SOFF (*(vuint16*)(0xFC045166))
1095 #define MCF_EDMA_TCD12_SOFF (*(vuint16*)(0xFC045186))
1096 #define MCF_EDMA_TCD13_SOFF (*(vuint16*)(0xFC0451A6))
1097 #define MCF_EDMA_TCD14_SOFF (*(vuint16*)(0xFC0451C6))
1098 #define MCF_EDMA_TCD15_SOFF (*(vuint16*)(0xFC0451E6))
1099 #define MCF_EDMA_TCD_SOFF(x) (*(vuint16*)(0xFC045006+((x)*0x020)))
1100 #define MCF_EDMA_TCD0_NBYTES (*(vuint32*)(0xFC045008))
1101 #define MCF_EDMA_TCD1_NBYTES (*(vuint32*)(0xFC045028))
1102 #define MCF_EDMA_TCD2_NBYTES (*(vuint32*)(0xFC045048))
1103 #define MCF_EDMA_TCD3_NBYTES (*(vuint32*)(0xFC045068))
1104 #define MCF_EDMA_TCD4_NBYTES (*(vuint32*)(0xFC045088))
1105 #define MCF_EDMA_TCD5_NBYTES (*(vuint32*)(0xFC0450A8))
1106 #define MCF_EDMA_TCD6_NBYTES (*(vuint32*)(0xFC0450C8))
1107 #define MCF_EDMA_TCD7_NBYTES (*(vuint32*)(0xFC0450E8))
1108 #define MCF_EDMA_TCD8_NBYTES (*(vuint32*)(0xFC045108))
1109 #define MCF_EDMA_TCD9_NBYTES (*(vuint32*)(0xFC045128))
1110 #define MCF_EDMA_TCD10_NBYTES (*(vuint32*)(0xFC045148))
1111 #define MCF_EDMA_TCD11_NBYTES (*(vuint32*)(0xFC045168))
1112 #define MCF_EDMA_TCD12_NBYTES (*(vuint32*)(0xFC045188))
1113 #define MCF_EDMA_TCD13_NBYTES (*(vuint32*)(0xFC0451A8))
1114 #define MCF_EDMA_TCD14_NBYTES (*(vuint32*)(0xFC0451C8))
1115 #define MCF_EDMA_TCD15_NBYTES (*(vuint32*)(0xFC0451E8))
1116 #define MCF_EDMA_TCD_NBYTES(x) (*(vuint32*)(0xFC045008+((x)*0x020)))
1117 #define MCF_EDMA_TCD0_SLAST (*(vuint32*)(0xFC04500C))
1118 #define MCF_EDMA_TCD1_SLAST (*(vuint32*)(0xFC04502C))
1119 #define MCF_EDMA_TCD2_SLAST (*(vuint32*)(0xFC04504C))
1120 #define MCF_EDMA_TCD3_SLAST (*(vuint32*)(0xFC04506C))
1121 #define MCF_EDMA_TCD4_SLAST (*(vuint32*)(0xFC04508C))
1122 #define MCF_EDMA_TCD5_SLAST (*(vuint32*)(0xFC0450AC))
1123 #define MCF_EDMA_TCD6_SLAST (*(vuint32*)(0xFC0450CC))
1124 #define MCF_EDMA_TCD7_SLAST (*(vuint32*)(0xFC0450EC))
1125 #define MCF_EDMA_TCD8_SLAST (*(vuint32*)(0xFC04510C))
1126 #define MCF_EDMA_TCD9_SLAST (*(vuint32*)(0xFC04512C))
1127 #define MCF_EDMA_TCD10_SLAST (*(vuint32*)(0xFC04514C))
1128 #define MCF_EDMA_TCD11_SLAST (*(vuint32*)(0xFC04516C))
1129 #define MCF_EDMA_TCD12_SLAST (*(vuint32*)(0xFC04518C))
1130 #define MCF_EDMA_TCD13_SLAST (*(vuint32*)(0xFC0451AC))
1131 #define MCF_EDMA_TCD14_SLAST (*(vuint32*)(0xFC0451CC))
1132 #define MCF_EDMA_TCD15_SLAST (*(vuint32*)(0xFC0451EC))
1133 #define MCF_EDMA_TCD_SLAST(x) (*(vuint32*)(0xFC04500C+((x)*0x020)))
1134 #define MCF_EDMA_TCD0_DADDR (*(vuint32*)(0xFC045010))
1135 #define MCF_EDMA_TCD1_DADDR (*(vuint32*)(0xFC045030))
1136 #define MCF_EDMA_TCD2_DADDR (*(vuint32*)(0xFC045050))
1137 #define MCF_EDMA_TCD3_DADDR (*(vuint32*)(0xFC045070))
1138 #define MCF_EDMA_TCD4_DADDR (*(vuint32*)(0xFC045090))
1139 #define MCF_EDMA_TCD5_DADDR (*(vuint32*)(0xFC0450B0))
1140 #define MCF_EDMA_TCD6_DADDR (*(vuint32*)(0xFC0450D0))
1141 #define MCF_EDMA_TCD7_DADDR (*(vuint32*)(0xFC0450F0))
1142 #define MCF_EDMA_TCD8_DADDR (*(vuint32*)(0xFC045110))
1143 #define MCF_EDMA_TCD9_DADDR (*(vuint32*)(0xFC045130))
1144 #define MCF_EDMA_TCD10_DADDR (*(vuint32*)(0xFC045150))
1145 #define MCF_EDMA_TCD11_DADDR (*(vuint32*)(0xFC045170))
1146 #define MCF_EDMA_TCD12_DADDR (*(vuint32*)(0xFC045190))
1147 #define MCF_EDMA_TCD13_DADDR (*(vuint32*)(0xFC0451B0))
1148 #define MCF_EDMA_TCD14_DADDR (*(vuint32*)(0xFC0451D0))
1149 #define MCF_EDMA_TCD15_DADDR (*(vuint32*)(0xFC0451F0))
1150 #define MCF_EDMA_TCD_DADDR(x) (*(vuint32*)(0xFC045010+((x)*0x020)))
1151 #define MCF_EDMA_TCD0_CITER (*(vuint16*)(0xFC045014))
1152 #define MCF_EDMA_TCD1_CITER (*(vuint16*)(0xFC045034))
1153 #define MCF_EDMA_TCD2_CITER (*(vuint16*)(0xFC045054))
1154 #define MCF_EDMA_TCD3_CITER (*(vuint16*)(0xFC045074))
1155 #define MCF_EDMA_TCD4_CITER (*(vuint16*)(0xFC045094))
1156 #define MCF_EDMA_TCD5_CITER (*(vuint16*)(0xFC0450B4))
1157 #define MCF_EDMA_TCD6_CITER (*(vuint16*)(0xFC0450D4))
1158 #define MCF_EDMA_TCD7_CITER (*(vuint16*)(0xFC0450F4))
1159 #define MCF_EDMA_TCD8_CITER (*(vuint16*)(0xFC045114))
1160 #define MCF_EDMA_TCD9_CITER (*(vuint16*)(0xFC045134))
1161 #define MCF_EDMA_TCD10_CITER (*(vuint16*)(0xFC045154))
1162 #define MCF_EDMA_TCD11_CITER (*(vuint16*)(0xFC045174))
1163 #define MCF_EDMA_TCD12_CITER (*(vuint16*)(0xFC045194))
1164 #define MCF_EDMA_TCD13_CITER (*(vuint16*)(0xFC0451B4))
1165 #define MCF_EDMA_TCD14_CITER (*(vuint16*)(0xFC0451D4))
1166 #define MCF_EDMA_TCD15_CITER (*(vuint16*)(0xFC0451F4))
1167 #define MCF_EDMA_TCD_CITER(x) (*(vuint16*)(0xFC045014+((x)*0x020)))
1168 #define MCF_EDMA_TCD0_CITER_ELINK (*(vuint16*)(0xFC045014))
1169 #define MCF_EDMA_TCD1_CITER_ELINK (*(vuint16*)(0xFC045034))
1170 #define MCF_EDMA_TCD2_CITER_ELINK (*(vuint16*)(0xFC045054))
1171 #define MCF_EDMA_TCD3_CITER_ELINK (*(vuint16*)(0xFC045074))
1172 #define MCF_EDMA_TCD4_CITER_ELINK (*(vuint16*)(0xFC045094))
1173 #define MCF_EDMA_TCD5_CITER_ELINK (*(vuint16*)(0xFC0450B4))
1174 #define MCF_EDMA_TCD6_CITER_ELINK (*(vuint16*)(0xFC0450D4))
1175 #define MCF_EDMA_TCD7_CITER_ELINK (*(vuint16*)(0xFC0450F4))
1176 #define MCF_EDMA_TCD8_CITER_ELINK (*(vuint16*)(0xFC045114))
1177 #define MCF_EDMA_TCD9_CITER_ELINK (*(vuint16*)(0xFC045134))
1178 #define MCF_EDMA_TCD10_CITER_ELINK (*(vuint16*)(0xFC045154))
1179 #define MCF_EDMA_TCD11_CITER_ELINK (*(vuint16*)(0xFC045174))
1180 #define MCF_EDMA_TCD12_CITER_ELINK (*(vuint16*)(0xFC045194))
1181 #define MCF_EDMA_TCD13_CITER_ELINK (*(vuint16*)(0xFC0451B4))
1182 #define MCF_EDMA_TCD14_CITER_ELINK (*(vuint16*)(0xFC0451D4))
1183 #define MCF_EDMA_TCD15_CITER_ELINK (*(vuint16*)(0xFC0451F4))
1184 #define MCF_EDMA_TCD_CITER_ELINK(x) (*(vuint16*)(0xFC045014+((x)*0x020)))
1185 #define MCF_EDMA_TCD0_DOFF (*(vuint16*)(0xFC045016))
1186 #define MCF_EDMA_TCD1_DOFF (*(vuint16*)(0xFC045036))
1187 #define MCF_EDMA_TCD2_DOFF (*(vuint16*)(0xFC045056))
1188 #define MCF_EDMA_TCD3_DOFF (*(vuint16*)(0xFC045076))
1189 #define MCF_EDMA_TCD4_DOFF (*(vuint16*)(0xFC045096))
1190 #define MCF_EDMA_TCD5_DOFF (*(vuint16*)(0xFC0450B6))
1191 #define MCF_EDMA_TCD6_DOFF (*(vuint16*)(0xFC0450D6))
1192 #define MCF_EDMA_TCD7_DOFF (*(vuint16*)(0xFC0450F6))
1193 #define MCF_EDMA_TCD8_DOFF (*(vuint16*)(0xFC045116))
1194 #define MCF_EDMA_TCD9_DOFF (*(vuint16*)(0xFC045136))
1195 #define MCF_EDMA_TCD10_DOFF (*(vuint16*)(0xFC045156))
1196 #define MCF_EDMA_TCD11_DOFF (*(vuint16*)(0xFC045176))
1197 #define MCF_EDMA_TCD12_DOFF (*(vuint16*)(0xFC045196))
1198 #define MCF_EDMA_TCD13_DOFF (*(vuint16*)(0xFC0451B6))
1199 #define MCF_EDMA_TCD14_DOFF (*(vuint16*)(0xFC0451D6))
1200 #define MCF_EDMA_TCD15_DOFF (*(vuint16*)(0xFC0451F6))
1201 #define MCF_EDMA_TCD_DOFF(x) (*(vuint16*)(0xFC045016+((x)*0x020)))
1202 #define MCF_EDMA_TCD0_DLAST_SGA (*(vuint32*)(0xFC045018))
1203 #define MCF_EDMA_TCD1_DLAST_SGA (*(vuint32*)(0xFC045038))
1204 #define MCF_EDMA_TCD2_DLAST_SGA (*(vuint32*)(0xFC045058))
1205 #define MCF_EDMA_TCD3_DLAST_SGA (*(vuint32*)(0xFC045078))
1206 #define MCF_EDMA_TCD4_DLAST_SGA (*(vuint32*)(0xFC045098))
1207 #define MCF_EDMA_TCD5_DLAST_SGA (*(vuint32*)(0xFC0450B8))
1208 #define MCF_EDMA_TCD6_DLAST_SGA (*(vuint32*)(0xFC0450D8))
1209 #define MCF_EDMA_TCD7_DLAST_SGA (*(vuint32*)(0xFC0450F8))
1210 #define MCF_EDMA_TCD8_DLAST_SGA (*(vuint32*)(0xFC045118))
1211 #define MCF_EDMA_TCD9_DLAST_SGA (*(vuint32*)(0xFC045138))
1212 #define MCF_EDMA_TCD10_DLAST_SGA (*(vuint32*)(0xFC045158))
1213 #define MCF_EDMA_TCD11_DLAST_SGA (*(vuint32*)(0xFC045178))
1214 #define MCF_EDMA_TCD12_DLAST_SGA (*(vuint32*)(0xFC045198))
1215 #define MCF_EDMA_TCD13_DLAST_SGA (*(vuint32*)(0xFC0451B8))
1216 #define MCF_EDMA_TCD14_DLAST_SGA (*(vuint32*)(0xFC0451D8))
1217 #define MCF_EDMA_TCD15_DLAST_SGA (*(vuint32*)(0xFC0451F8))
1218 #define MCF_EDMA_TCD_DLAST_SGA(x) (*(vuint32*)(0xFC045018+((x)*0x020)))
1219 #define MCF_EDMA_TCD0_BITER (*(vuint16*)(0xFC04501C))
1220 #define MCF_EDMA_TCD1_BITER (*(vuint16*)(0xFC04503C))
1221 #define MCF_EDMA_TCD2_BITER (*(vuint16*)(0xFC04505C))
1222 #define MCF_EDMA_TCD3_BITER (*(vuint16*)(0xFC04507C))
1223 #define MCF_EDMA_TCD4_BITER (*(vuint16*)(0xFC04509C))
1224 #define MCF_EDMA_TCD5_BITER (*(vuint16*)(0xFC0450BC))
1225 #define MCF_EDMA_TCD6_BITER (*(vuint16*)(0xFC0450DC))
1226 #define MCF_EDMA_TCD7_BITER (*(vuint16*)(0xFC0450FC))
1227 #define MCF_EDMA_TCD8_BITER (*(vuint16*)(0xFC04511C))
1228 #define MCF_EDMA_TCD9_BITER (*(vuint16*)(0xFC04513C))
1229 #define MCF_EDMA_TCD10_BITER (*(vuint16*)(0xFC04515C))
1230 #define MCF_EDMA_TCD11_BITER (*(vuint16*)(0xFC04517C))
1231 #define MCF_EDMA_TCD12_BITER (*(vuint16*)(0xFC04519C))
1232 #define MCF_EDMA_TCD13_BITER (*(vuint16*)(0xFC0451BC))
1233 #define MCF_EDMA_TCD14_BITER (*(vuint16*)(0xFC0451DC))
1234 #define MCF_EDMA_TCD15_BITER (*(vuint16*)(0xFC0451FC))
1235 #define MCF_EDMA_TCD_BITER(x) (*(vuint16*)(0xFC04501C+((x)*0x020)))
1236 #define MCF_EDMA_TCD0_BITER_ELINK (*(vuint16*)(0xFC04501C))
1237 #define MCF_EDMA_TCD1_BITER_ELINK (*(vuint16*)(0xFC04503C))
1238 #define MCF_EDMA_TCD2_BITER_ELINK (*(vuint16*)(0xFC04505C))
1239 #define MCF_EDMA_TCD3_BITER_ELINK (*(vuint16*)(0xFC04507C))
1240 #define MCF_EDMA_TCD4_BITER_ELINK (*(vuint16*)(0xFC04509C))
1241 #define MCF_EDMA_TCD5_BITER_ELINK (*(vuint16*)(0xFC0450BC))
1242 #define MCF_EDMA_TCD6_BITER_ELINK (*(vuint16*)(0xFC0450DC))
1243 #define MCF_EDMA_TCD7_BITER_ELINK (*(vuint16*)(0xFC0450FC))
1244 #define MCF_EDMA_TCD8_BITER_ELINK (*(vuint16*)(0xFC04511C))
1245 #define MCF_EDMA_TCD9_BITER_ELINK (*(vuint16*)(0xFC04513C))
1246 #define MCF_EDMA_TCD10_BITER_ELINK (*(vuint16*)(0xFC04515C))
1247 #define MCF_EDMA_TCD11_BITER_ELINK (*(vuint16*)(0xFC04517C))
1248 #define MCF_EDMA_TCD12_BITER_ELINK (*(vuint16*)(0xFC04519C))
1249 #define MCF_EDMA_TCD13_BITER_ELINK (*(vuint16*)(0xFC0451BC))
1250 #define MCF_EDMA_TCD14_BITER_ELINK (*(vuint16*)(0xFC0451DC))
1251 #define MCF_EDMA_TCD15_BITER_ELINK (*(vuint16*)(0xFC0451FC))
1252 #define MCF_EDMA_TCD_BITER_ELINK(x) (*(vuint16*)(0xFC04501C+((x)*0x020)))
1253 #define MCF_EDMA_TCD0_CSR (*(vuint16*)(0xFC04501E))
1254 #define MCF_EDMA_TCD1_CSR (*(vuint16*)(0xFC04503E))
1255 #define MCF_EDMA_TCD2_CSR (*(vuint16*)(0xFC04505E))
1256 #define MCF_EDMA_TCD3_CSR (*(vuint16*)(0xFC04507E))
1257 #define MCF_EDMA_TCD4_CSR (*(vuint16*)(0xFC04509E))
1258 #define MCF_EDMA_TCD5_CSR (*(vuint16*)(0xFC0450BE))
1259 #define MCF_EDMA_TCD6_CSR (*(vuint16*)(0xFC0450DE))
1260 #define MCF_EDMA_TCD7_CSR (*(vuint16*)(0xFC0450FE))
1261 #define MCF_EDMA_TCD8_CSR (*(vuint16*)(0xFC04511E))
1262 #define MCF_EDMA_TCD9_CSR (*(vuint16*)(0xFC04513E))
1263 #define MCF_EDMA_TCD10_CSR (*(vuint16*)(0xFC04515E))
1264 #define MCF_EDMA_TCD11_CSR (*(vuint16*)(0xFC04517E))
1265 #define MCF_EDMA_TCD12_CSR (*(vuint16*)(0xFC04519E))
1266 #define MCF_EDMA_TCD13_CSR (*(vuint16*)(0xFC0451BE))
1267 #define MCF_EDMA_TCD14_CSR (*(vuint16*)(0xFC0451DE))
1268 #define MCF_EDMA_TCD15_CSR (*(vuint16*)(0xFC0451FE))
1269 #define MCF_EDMA_TCD_CSR(x) (*(vuint16*)(0xFC04501E +((x)*0x020)))
1270 
1271 /* Bit definitions and macros for MCF_EDMA_CR */
1272 #define MCF_EDMA_CR_EDBG (0x00000002)
1273 #define MCF_EDMA_CR_ERCA (0x00000004)
1274 
1275 /* Bit definitions and macros for MCF_EDMA_ES */
1276 #define MCF_EDMA_ES_DBE (0x00000001)
1277 #define MCF_EDMA_ES_SBE (0x00000002)
1278 #define MCF_EDMA_ES_SGE (0x00000004)
1279 #define MCF_EDMA_ES_NCE (0x00000008)
1280 #define MCF_EDMA_ES_DOE (0x00000010)
1281 #define MCF_EDMA_ES_DAE (0x00000020)
1282 #define MCF_EDMA_ES_SOE (0x00000040)
1283 #define MCF_EDMA_ES_SAE (0x00000080)
1284 #define MCF_EDMA_ES_ERRCHN(x) (((x)&0x0000000F)<<8)
1285 #define MCF_EDMA_ES_CPE (0x00004000)
1286 #define MCF_EDMA_ES_VLD (0x80000000)
1287 
1288 /* Bit definitions and macros for MCF_EDMA_ERQ */
1289 #define MCF_EDMA_ERQ_ERQ0 (0x0001)
1290 #define MCF_EDMA_ERQ_ERQ1 (0x0002)
1291 #define MCF_EDMA_ERQ_ERQ2 (0x0004)
1292 #define MCF_EDMA_ERQ_ERQ3 (0x0008)
1293 #define MCF_EDMA_ERQ_ERQ4 (0x0010)
1294 #define MCF_EDMA_ERQ_ERQ5 (0x0020)
1295 #define MCF_EDMA_ERQ_ERQ6 (0x0040)
1296 #define MCF_EDMA_ERQ_ERQ7 (0x0080)
1297 #define MCF_EDMA_ERQ_ERQ8 (0x0100)
1298 #define MCF_EDMA_ERQ_ERQ9 (0x0200)
1299 #define MCF_EDMA_ERQ_ERQ10 (0x0400)
1300 #define MCF_EDMA_ERQ_ERQ11 (0x0800)
1301 #define MCF_EDMA_ERQ_ERQ12 (0x1000)
1302 #define MCF_EDMA_ERQ_ERQ13 (0x2000)
1303 #define MCF_EDMA_ERQ_ERQ14 (0x4000)
1304 #define MCF_EDMA_ERQ_ERQ15 (0x8000)
1305 
1306 /* Bit definitions and macros for MCF_EDMA_EEI */
1307 #define MCF_EDMA_EEI_EEI0 (0x0001)
1308 #define MCF_EDMA_EEI_EEI1 (0x0002)
1309 #define MCF_EDMA_EEI_EEI2 (0x0004)
1310 #define MCF_EDMA_EEI_EEI3 (0x0008)
1311 #define MCF_EDMA_EEI_EEI4 (0x0010)
1312 #define MCF_EDMA_EEI_EEI5 (0x0020)
1313 #define MCF_EDMA_EEI_EEI6 (0x0040)
1314 #define MCF_EDMA_EEI_EEI7 (0x0080)
1315 #define MCF_EDMA_EEI_EEI8 (0x0100)
1316 #define MCF_EDMA_EEI_EEI9 (0x0200)
1317 #define MCF_EDMA_EEI_EEI10 (0x0400)
1318 #define MCF_EDMA_EEI_EEI11 (0x0800)
1319 #define MCF_EDMA_EEI_EEI12 (0x1000)
1320 #define MCF_EDMA_EEI_EEI13 (0x2000)
1321 #define MCF_EDMA_EEI_EEI14 (0x4000)
1322 #define MCF_EDMA_EEI_EEI15 (0x8000)
1323 
1324 /* Bit definitions and macros for MCF_EDMA_SERQ */
1325 #define MCF_EDMA_SERQ_SERQ(x) (((x)&0x0F)<<0)
1326 #define MCF_EDMA_SERQ_SAER (0x40)
1327 
1328 /* Bit definitions and macros for MCF_EDMA_CERQ */
1329 #define MCF_EDMA_CERQ_CERQ(x) (((x)&0x0F)<<0)
1330 #define MCF_EDMA_CERQ_CAER (0x40)
1331 
1332 /* Bit definitions and macros for MCF_EDMA_SEEI */
1333 #define MCF_EDMA_SEEI_SEEI(x) (((x)&0x0F)<<0)
1334 #define MCF_EDMA_SEEI_SAEE (0x40)
1335 
1336 /* Bit definitions and macros for MCF_EDMA_CEEI */
1337 #define MCF_EDMA_CEEI_CEEI(x) (((x)&0x0F)<<0)
1338 #define MCF_EDMA_CEEI_CAEE (0x40)
1339 
1340 /* Bit definitions and macros for MCF_EDMA_CINT */
1341 #define MCF_EDMA_CINT_CINT(x) (((x)&0x0F)<<0)
1342 #define MCF_EDMA_CINT_CAIR (0x40)
1343 
1344 /* Bit definitions and macros for MCF_EDMA_CERR */
1345 #define MCF_EDMA_CERR_CERR(x) (((x)&0x0F)<<0)
1346 #define MCF_EDMA_CERR_CAER (0x40)
1347 
1348 /* Bit definitions and macros for MCF_EDMA_SSRT */
1349 #define MCF_EDMA_SSRT_SSRT(x) (((x)&0x0F)<<0)
1350 #define MCF_EDMA_SSRT_SAST (0x40)
1351 
1352 /* Bit definitions and macros for MCF_EDMA_CDNE */
1353 #define MCF_EDMA_CDNE_CDNE(x) (((x)&0x0F)<<0)
1354 #define MCF_EDMA_CDNE_CADN (0x40)
1355 
1356 /* Bit definitions and macros for MCF_EDMA_INT */
1357 #define MCF_EDMA_INT_INT0 (0x0001)
1358 #define MCF_EDMA_INT_INT1 (0x0002)
1359 #define MCF_EDMA_INT_INT2 (0x0004)
1360 #define MCF_EDMA_INT_INT3 (0x0008)
1361 #define MCF_EDMA_INT_INT4 (0x0010)
1362 #define MCF_EDMA_INT_INT5 (0x0020)
1363 #define MCF_EDMA_INT_INT6 (0x0040)
1364 #define MCF_EDMA_INT_INT7 (0x0080)
1365 #define MCF_EDMA_INT_INT8 (0x0100)
1366 #define MCF_EDMA_INT_INT9 (0x0200)
1367 #define MCF_EDMA_INT_INT10 (0x0400)
1368 #define MCF_EDMA_INT_INT11 (0x0800)
1369 #define MCF_EDMA_INT_INT12 (0x1000)
1370 #define MCF_EDMA_INT_INT13 (0x2000)
1371 #define MCF_EDMA_INT_INT14 (0x4000)
1372 #define MCF_EDMA_INT_INT15 (0x8000)
1373 
1374 /* Bit definitions and macros for MCF_EDMA_ERR */
1375 #define MCF_EDMA_ERR_ERR0 (0x0001)
1376 #define MCF_EDMA_ERR_ERR1 (0x0002)
1377 #define MCF_EDMA_ERR_ERR2 (0x0004)
1378 #define MCF_EDMA_ERR_ERR3 (0x0008)
1379 #define MCF_EDMA_ERR_ERR4 (0x0010)
1380 #define MCF_EDMA_ERR_ERR5 (0x0020)
1381 #define MCF_EDMA_ERR_ERR6 (0x0040)
1382 #define MCF_EDMA_ERR_ERR7 (0x0080)
1383 #define MCF_EDMA_ERR_ERR8 (0x0100)
1384 #define MCF_EDMA_ERR_ERR9 (0x0200)
1385 #define MCF_EDMA_ERR_ERR10 (0x0400)
1386 #define MCF_EDMA_ERR_ERR11 (0x0800)
1387 #define MCF_EDMA_ERR_ERR12 (0x1000)
1388 #define MCF_EDMA_ERR_ERR13 (0x2000)
1389 #define MCF_EDMA_ERR_ERR14 (0x4000)
1390 #define MCF_EDMA_ERR_ERR15 (0x8000)
1391 
1392 /* Bit definitions and macros for MCF_EDMA_DCHPRI */
1393 #define MCF_EDMA_DCHPRI_CHPRI(x) (((x)&0x0F)<<0)
1394 #define MCF_EDMA_DCHPRI_ECP (0x80)
1395 
1396 /* Bit definitions and macros for MCF_EDMA_TCD_SADDR */
1397 #define MCF_EDMA_TCD_SADDR_SADDR(x) (((x)&0xFFFFFFFF)<<0)
1398 
1399 /* Bit definitions and macros for MCF_EDMA_TCD_ATTR */
1400 #define MCF_EDMA_TCD_ATTR_DSIZE(x) (((x)&0x0007)<<0)
1401 #define MCF_EDMA_TCD_ATTR_DMOD(x) (((x)&0x001F)<<3)
1402 #define MCF_EDMA_TCD_ATTR_SSIZE(x) (((x)&0x0007)<<8)
1403 #define MCF_EDMA_TCD_ATTR_SMOD(x) (((x)&0x001F)<<11)
1404 #define MCF_EDMA_TCD_ATTR_SSIZE_8BIT (0x0000)
1405 #define MCF_EDMA_TCD_ATTR_SSIZE_16BIT (0x0100)
1406 #define MCF_EDMA_TCD_ATTR_SSIZE_32BIT (0x0200)
1407 #define MCF_EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400)
1408 #define MCF_EDMA_TCD_ATTR_DSIZE_8BIT (0x0000)
1409 #define MCF_EDMA_TCD_ATTR_DSIZE_16BIT (0x0001)
1410 #define MCF_EDMA_TCD_ATTR_DSIZE_32BIT (0x0002)
1411 #define MCF_EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004)
1412 
1413 /* Bit definitions and macros for MCF_EDMA_TCD_SOFF */
1414 #define MCF_EDMA_TCD_SOFF_SOFF(x) (((x)&0xFFFF)<<0)
1415 
1416 /* Bit definitions and macros for MCF_EDMA_TCD_NBYTES */
1417 #define MCF_EDMA_TCD_NBYTES_NBYTES(x) (((x)&0xFFFFFFFF)<<0)
1418 
1419 /* Bit definitions and macros for MCF_EDMA_TCD_SLAST */
1420 #define MCF_EDMA_TCD_SLAST_SLAST(x) (((x)&0xFFFFFFFF)<<0)
1421 
1422 /* Bit definitions and macros for MCF_EDMA_TCD_DADDR */
1423 #define MCF_EDMA_TCD_DADDR_DADDR(x) (((x)&0xFFFFFFFF)<<0)
1424 
1425 /* Bit definitions and macros for MCF_EDMA_TCD_CITER */
1426 #define MCF_EDMA_TCD_CITER_CITER(x) (((x)&0x7FFF)<<0)
1427 #define MCF_EDMA_TCD_CITER_E_LINK (0x8000)
1428 
1429 /* Bit definitions and macros for MCF_EDMA_TCD_CITER_ELINK */
1430 #define MCF_EDMA_TCD_CITER_ELINK_CITER(x) (((x)&0x01FF)<<0)
1431 #define MCF_EDMA_TCD_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1432 #define MCF_EDMA_TCD_CITER_ELINK_E_LINK (0x8000)
1433 
1434 /* Bit definitions and macros for MCF_EDMA_TCD_DOFF */
1435 #define MCF_EDMA_TCD_DOFF_DOFF(x) (((x)&0xFFFF)<<0)
1436 
1437 /* Bit definitions and macros for MCF_EDMA_TCD_DLAST_SGA */
1438 #define MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (((x)&0xFFFFFFFF)<<0)
1439 
1440 /* Bit definitions and macros for MCF_EDMA_TCD_BITER */
1441 #define MCF_EDMA_TCD_BITER_BITER(x) (((x)&0x7FFF)<<0)
1442 #define MCF_EDMA_TCD_BITER_E_LINK (0x8000)
1443 
1444 /* Bit definitions and macros for MCF_EDMA_TCD_BITER_ELINK */
1445 #define MCF_EDMA_TCD_BITER_ELINK_BITER(x) (((x)&0x01FF)<<0)
1446 #define MCF_EDMA_TCD_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1447 #define MCF_EDMA_TCD_BITER_ELINK_E_LINK (0x8000)
1448 
1449 /* Bit definitions and macros for MCF_EDMA_TCD_CSR */
1450 #define MCF_EDMA_TCD_CSR_START (0x0001)
1451 #define MCF_EDMA_TCD_CSR_INT_MAJOR (0x0002)
1452 #define MCF_EDMA_TCD_CSR_INT_HALF (0x0004)
1453 #define MCF_EDMA_TCD_CSR_D_REQ (0x0008)
1454 #define MCF_EDMA_TCD_CSR_E_SG (0x0010)
1455 #define MCF_EDMA_TCD_CSR_E_LINK (0x0020)
1456 #define MCF_EDMA_TCD_CSR_ACTIVE (0x0040)
1457 #define MCF_EDMA_TCD_CSR_DONE (0x0080)
1458 #define MCF_EDMA_TCD_CSR_LINKCH(x) (((x)&0x003F)<<8)
1459 #define MCF_EDMA_TCD_CSR_BWC(x) (((x)&0x0003)<<14)
1460 #define MCF_EDMA_TCD_CSR_BWC_NO_STALL (0x0000)
1461 #define MCF_EDMA_TCD_CSR_BWC_4CYC_STALL (0x8000)
1462 #define MCF_EDMA_TCD_CSR_BWC_8CYC_STALL (0xC000)
1463 
1464 /*********************************************************************
1465 *
1466 * Interrupt Controller (INTC)
1467 *
1468 *********************************************************************/
1469 
1470 /* Register read/write macros */
1471 #define MCF_INTC0_IPRH (*(vuint32*)(0xFC048000))
1472 #define MCF_INTC0_IPRL (*(vuint32*)(0xFC048004))
1473 #define MCF_INTC0_IMRH (*(vuint32*)(0xFC048008))
1474 #define MCF_INTC0_IMRL (*(vuint32*)(0xFC04800C))
1475 #define MCF_INTC0_INTFRCH (*(vuint32*)(0xFC048010))
1476 #define MCF_INTC0_INTFRCL (*(vuint32*)(0xFC048014))
1477 #define MCF_INTC0_ICONFIG (*(vuint16*)(0xFC04801A))
1478 #define MCF_INTC0_SIMR (*(vuint8 *)(0xFC04801C))
1479 #define MCF_INTC0_CIMR (*(vuint8 *)(0xFC04801D))
1480 #define MCF_INTC0_CLMASK (*(vuint8 *)(0xFC04801E))
1481 #define MCF_INTC0_SLMASK (*(vuint8 *)(0xFC04801F))
1482 #define MCF_INTC0_ICR0 (*(vuint8 *)(0xFC048040))
1483 #define MCF_INTC0_ICR1 (*(vuint8 *)(0xFC048041))
1484 #define MCF_INTC0_ICR2 (*(vuint8 *)(0xFC048042))
1485 #define MCF_INTC0_ICR3 (*(vuint8 *)(0xFC048043))
1486 #define MCF_INTC0_ICR4 (*(vuint8 *)(0xFC048044))
1487 #define MCF_INTC0_ICR5 (*(vuint8 *)(0xFC048045))
1488 #define MCF_INTC0_ICR6 (*(vuint8 *)(0xFC048046))
1489 #define MCF_INTC0_ICR7 (*(vuint8 *)(0xFC048047))
1490 #define MCF_INTC0_ICR8 (*(vuint8 *)(0xFC048048))
1491 #define MCF_INTC0_ICR9 (*(vuint8 *)(0xFC048049))
1492 #define MCF_INTC0_ICR10 (*(vuint8 *)(0xFC04804A))
1493 #define MCF_INTC0_ICR11 (*(vuint8 *)(0xFC04804B))
1494 #define MCF_INTC0_ICR12 (*(vuint8 *)(0xFC04804C))
1495 #define MCF_INTC0_ICR13 (*(vuint8 *)(0xFC04804D))
1496 #define MCF_INTC0_ICR14 (*(vuint8 *)(0xFC04804E))
1497 #define MCF_INTC0_ICR15 (*(vuint8 *)(0xFC04804F))
1498 #define MCF_INTC0_ICR16 (*(vuint8 *)(0xFC048050))
1499 #define MCF_INTC0_ICR17 (*(vuint8 *)(0xFC048051))
1500 #define MCF_INTC0_ICR18 (*(vuint8 *)(0xFC048052))
1501 #define MCF_INTC0_ICR19 (*(vuint8 *)(0xFC048053))
1502 #define MCF_INTC0_ICR20 (*(vuint8 *)(0xFC048054))
1503 #define MCF_INTC0_ICR21 (*(vuint8 *)(0xFC048055))
1504 #define MCF_INTC0_ICR22 (*(vuint8 *)(0xFC048056))
1505 #define MCF_INTC0_ICR23 (*(vuint8 *)(0xFC048057))
1506 #define MCF_INTC0_ICR24 (*(vuint8 *)(0xFC048058))
1507 #define MCF_INTC0_ICR25 (*(vuint8 *)(0xFC048059))
1508 #define MCF_INTC0_ICR26 (*(vuint8 *)(0xFC04805A))
1509 #define MCF_INTC0_ICR27 (*(vuint8 *)(0xFC04805B))
1510 #define MCF_INTC0_ICR28 (*(vuint8 *)(0xFC04805C))
1511 #define MCF_INTC0_ICR29 (*(vuint8 *)(0xFC04805D))
1512 #define MCF_INTC0_ICR30 (*(vuint8 *)(0xFC04805E))
1513 #define MCF_INTC0_ICR31 (*(vuint8 *)(0xFC04805F))
1514 #define MCF_INTC0_ICR32 (*(vuint8 *)(0xFC048060))
1515 #define MCF_INTC0_ICR33 (*(vuint8 *)(0xFC048061))
1516 #define MCF_INTC0_ICR34 (*(vuint8 *)(0xFC048062))
1517 #define MCF_INTC0_ICR35 (*(vuint8 *)(0xFC048063))
1518 #define MCF_INTC0_ICR36 (*(vuint8 *)(0xFC048064))
1519 #define MCF_INTC0_ICR37 (*(vuint8 *)(0xFC048065))
1520 #define MCF_INTC0_ICR38 (*(vuint8 *)(0xFC048066))
1521 #define MCF_INTC0_ICR39 (*(vuint8 *)(0xFC048067))
1522 #define MCF_INTC0_ICR40 (*(vuint8 *)(0xFC048068))
1523 #define MCF_INTC0_ICR41 (*(vuint8 *)(0xFC048069))
1524 #define MCF_INTC0_ICR42 (*(vuint8 *)(0xFC04806A))
1525 #define MCF_INTC0_ICR43 (*(vuint8 *)(0xFC04806B))
1526 #define MCF_INTC0_ICR44 (*(vuint8 *)(0xFC04806C))
1527 #define MCF_INTC0_ICR45 (*(vuint8 *)(0xFC04806D))
1528 #define MCF_INTC0_ICR46 (*(vuint8 *)(0xFC04806E))
1529 #define MCF_INTC0_ICR47 (*(vuint8 *)(0xFC04806F))
1530 #define MCF_INTC0_ICR48 (*(vuint8 *)(0xFC048070))
1531 #define MCF_INTC0_ICR49 (*(vuint8 *)(0xFC048071))
1532 #define MCF_INTC0_ICR50 (*(vuint8 *)(0xFC048072))
1533 #define MCF_INTC0_ICR51 (*(vuint8 *)(0xFC048073))
1534 #define MCF_INTC0_ICR52 (*(vuint8 *)(0xFC048074))
1535 #define MCF_INTC0_ICR53 (*(vuint8 *)(0xFC048075))
1536 #define MCF_INTC0_ICR54 (*(vuint8 *)(0xFC048076))
1537 #define MCF_INTC0_ICR55 (*(vuint8 *)(0xFC048077))
1538 #define MCF_INTC0_ICR56 (*(vuint8 *)(0xFC048078))
1539 #define MCF_INTC0_ICR57 (*(vuint8 *)(0xFC048079))
1540 #define MCF_INTC0_ICR58 (*(vuint8 *)(0xFC04807A))
1541 #define MCF_INTC0_ICR59 (*(vuint8 *)(0xFC04807B))
1542 #define MCF_INTC0_ICR60 (*(vuint8 *)(0xFC04807C))
1543 #define MCF_INTC0_ICR61 (*(vuint8 *)(0xFC04807D))
1544 #define MCF_INTC0_ICR62 (*(vuint8 *)(0xFC04807E))
1545 #define MCF_INTC0_ICR63 (*(vuint8 *)(0xFC04807F))
1546 #define MCF_INTC0_ICR(x) (*(vuint8 *)(0xFC048040+((x)*0x001)))
1547 #define MCF_INTC0_SWIACK (*(vuint8 *)(0xFC0480E0))
1548 #define MCF_INTC0_L1IACK (*(vuint8 *)(0xFC0480E4))
1549 #define MCF_INTC0_L2IACK (*(vuint8 *)(0xFC0480E8))
1550 #define MCF_INTC0_L3IACK (*(vuint8 *)(0xFC0480EC))
1551 #define MCF_INTC0_L4IACK (*(vuint8 *)(0xFC0480F0))
1552 #define MCF_INTC0_L5IACK (*(vuint8 *)(0xFC0480F4))
1553 #define MCF_INTC0_L6IACK (*(vuint8 *)(0xFC0480F8))
1554 #define MCF_INTC0_L7IACK (*(vuint8 *)(0xFC0480FC))
1555 #define MCF_INTC0_LIACK(x) (*(vuint8 *)(0xFC0480E4+((x-1)*0x004)))
1556 #define MCF_INTC1_IPRH (*(vuint32*)(0xFC04C000))
1557 #define MCF_INTC1_IPRL (*(vuint32*)(0xFC04C004))
1558 #define MCF_INTC1_IMRH (*(vuint32*)(0xFC04C008))
1559 #define MCF_INTC1_IMRL (*(vuint32*)(0xFC04C00C))
1560 #define MCF_INTC1_INTFRCH (*(vuint32*)(0xFC04C010))
1561 #define MCF_INTC1_INTFRCL (*(vuint32*)(0xFC04C014))
1562 #define MCF_INTC1_ICONFIG (*(vuint16*)(0xFC04C01A))
1563 #define MCF_INTC1_SIMR (*(vuint8 *)(0xFC04C01C))
1564 #define MCF_INTC1_CIMR (*(vuint8 *)(0xFC04C01D))
1565 #define MCF_INTC1_CLMASK (*(vuint8 *)(0xFC04C01E))
1566 #define MCF_INTC1_SLMASK (*(vuint8 *)(0xFC04C01F))
1567 #define MCF_INTC1_ICR0 (*(vuint8 *)(0xFC04C040))
1568 #define MCF_INTC1_ICR1 (*(vuint8 *)(0xFC04C041))
1569 #define MCF_INTC1_ICR2 (*(vuint8 *)(0xFC04C042))
1570 #define MCF_INTC1_ICR3 (*(vuint8 *)(0xFC04C043))
1571 #define MCF_INTC1_ICR4 (*(vuint8 *)(0xFC04C044))
1572 #define MCF_INTC1_ICR5 (*(vuint8 *)(0xFC04C045))
1573 #define MCF_INTC1_ICR6 (*(vuint8 *)(0xFC04C046))
1574 #define MCF_INTC1_ICR7 (*(vuint8 *)(0xFC04C047))
1575 #define MCF_INTC1_ICR8 (*(vuint8 *)(0xFC04C048))
1576 #define MCF_INTC1_ICR9 (*(vuint8 *)(0xFC04C049))
1577 #define MCF_INTC1_ICR10 (*(vuint8 *)(0xFC04C04A))
1578 #define MCF_INTC1_ICR11 (*(vuint8 *)(0xFC04C04B))
1579 #define MCF_INTC1_ICR12 (*(vuint8 *)(0xFC04C04C))
1580 #define MCF_INTC1_ICR13 (*(vuint8 *)(0xFC04C04D))
1581 #define MCF_INTC1_ICR14 (*(vuint8 *)(0xFC04C04E))
1582 #define MCF_INTC1_ICR15 (*(vuint8 *)(0xFC04C04F))
1583 #define MCF_INTC1_ICR16 (*(vuint8 *)(0xFC04C050))
1584 #define MCF_INTC1_ICR17 (*(vuint8 *)(0xFC04C051))
1585 #define MCF_INTC1_ICR18 (*(vuint8 *)(0xFC04C052))
1586 #define MCF_INTC1_ICR19 (*(vuint8 *)(0xFC04C053))
1587 #define MCF_INTC1_ICR20 (*(vuint8 *)(0xFC04C054))
1588 #define MCF_INTC1_ICR21 (*(vuint8 *)(0xFC04C055))
1589 #define MCF_INTC1_ICR22 (*(vuint8 *)(0xFC04C056))
1590 #define MCF_INTC1_ICR23 (*(vuint8 *)(0xFC04C057))
1591 #define MCF_INTC1_ICR24 (*(vuint8 *)(0xFC04C058))
1592 #define MCF_INTC1_ICR25 (*(vuint8 *)(0xFC04C059))
1593 #define MCF_INTC1_ICR26 (*(vuint8 *)(0xFC04C05A))
1594 #define MCF_INTC1_ICR27 (*(vuint8 *)(0xFC04C05B))
1595 #define MCF_INTC1_ICR28 (*(vuint8 *)(0xFC04C05C))
1596 #define MCF_INTC1_ICR29 (*(vuint8 *)(0xFC04C05D))
1597 #define MCF_INTC1_ICR30 (*(vuint8 *)(0xFC04C05E))
1598 #define MCF_INTC1_ICR31 (*(vuint8 *)(0xFC04C05F))
1599 #define MCF_INTC1_ICR32 (*(vuint8 *)(0xFC04C060))
1600 #define MCF_INTC1_ICR33 (*(vuint8 *)(0xFC04C061))
1601 #define MCF_INTC1_ICR34 (*(vuint8 *)(0xFC04C062))
1602 #define MCF_INTC1_ICR35 (*(vuint8 *)(0xFC04C063))
1603 #define MCF_INTC1_ICR36 (*(vuint8 *)(0xFC04C064))
1604 #define MCF_INTC1_ICR37 (*(vuint8 *)(0xFC04C065))
1605 #define MCF_INTC1_ICR38 (*(vuint8 *)(0xFC04C066))
1606 #define MCF_INTC1_ICR39 (*(vuint8 *)(0xFC04C067))
1607 #define MCF_INTC1_ICR40 (*(vuint8 *)(0xFC04C068))
1608 #define MCF_INTC1_ICR41 (*(vuint8 *)(0xFC04C069))
1609 #define MCF_INTC1_ICR42 (*(vuint8 *)(0xFC04C06A))
1610 #define MCF_INTC1_ICR43 (*(vuint8 *)(0xFC04C06B))
1611 #define MCF_INTC1_ICR44 (*(vuint8 *)(0xFC04C06C))
1612 #define MCF_INTC1_ICR45 (*(vuint8 *)(0xFC04C06D))
1613 #define MCF_INTC1_ICR46 (*(vuint8 *)(0xFC04C06E))
1614 #define MCF_INTC1_ICR47 (*(vuint8 *)(0xFC04C06F))
1615 #define MCF_INTC1_ICR48 (*(vuint8 *)(0xFC04C070))
1616 #define MCF_INTC1_ICR49 (*(vuint8 *)(0xFC04C071))
1617 #define MCF_INTC1_ICR50 (*(vuint8 *)(0xFC04C072))
1618 #define MCF_INTC1_ICR51 (*(vuint8 *)(0xFC04C073))
1619 #define MCF_INTC1_ICR52 (*(vuint8 *)(0xFC04C074))
1620 #define MCF_INTC1_ICR53 (*(vuint8 *)(0xFC04C075))
1621 #define MCF_INTC1_ICR54 (*(vuint8 *)(0xFC04C076))
1622 #define MCF_INTC1_ICR55 (*(vuint8 *)(0xFC04C077))
1623 #define MCF_INTC1_ICR56 (*(vuint8 *)(0xFC04C078))
1624 #define MCF_INTC1_ICR57 (*(vuint8 *)(0xFC04C079))
1625 #define MCF_INTC1_ICR58 (*(vuint8 *)(0xFC04C07A))
1626 #define MCF_INTC1_ICR59 (*(vuint8 *)(0xFC04C07B))
1627 #define MCF_INTC1_ICR60 (*(vuint8 *)(0xFC04C07C))
1628 #define MCF_INTC1_ICR61 (*(vuint8 *)(0xFC04C07D))
1629 #define MCF_INTC1_ICR62 (*(vuint8 *)(0xFC04C07E))
1630 #define MCF_INTC1_ICR63 (*(vuint8 *)(0xFC04C07F))
1631 #define MCF_INTC1_ICR(x) (*(vuint8 *)(0xFC04C040+((x)*0x001)))
1632 #define MCF_INTC1_SWIACK (*(vuint8 *)(0xFC04C0E0))
1633 #define MCF_INTC1_L1IACK (*(vuint8 *)(0xFC04C0E4))
1634 #define MCF_INTC1_L2IACK (*(vuint8 *)(0xFC04C0E8))
1635 #define MCF_INTC1_L3IACK (*(vuint8 *)(0xFC04C0EC))
1636 #define MCF_INTC1_L4IACK (*(vuint8 *)(0xFC04C0F0))
1637 #define MCF_INTC1_L5IACK (*(vuint8 *)(0xFC04C0F4))
1638 #define MCF_INTC1_L6IACK (*(vuint8 *)(0xFC04C0F8))
1639 #define MCF_INTC1_L7IACK (*(vuint8 *)(0xFC04C0FC))
1640 #define MCF_INTC1_LIACK(x) (*(vuint8 *)(0xFC04C0E4+((x-1)*0x004)))
1641 #define MCF_INTC_IPRH(x) (*(vuint32*)(0xFC048000+((x)*0x4000)))
1642 #define MCF_INTC_IPRL(x) (*(vuint32*)(0xFC048004+((x)*0x4000)))
1643 #define MCF_INTC_IMRH(x) (*(vuint32*)(0xFC048008+((x)*0x4000)))
1644 #define MCF_INTC_IMRL(x) (*(vuint32*)(0xFC04800C+((x)*0x4000)))
1645 #define MCF_INTC_INTFRCH(x) (*(vuint32*)(0xFC048010+((x)*0x4000)))
1646 #define MCF_INTC_INTFRCL(x) (*(vuint32*)(0xFC048014+((x)*0x4000)))
1647 #define MCF_INTC_ICONFIG(x) (*(vuint16*)(0xFC04801A+((x)*0x4000)))
1648 #define MCF_INTC_SIMR(x) (*(vuint8 *)(0xFC04801C+((x)*0x4000)))
1649 #define MCF_INTC_CIMR(x) (*(vuint8 *)(0xFC04801D+((x)*0x4000)))
1650 #define MCF_INTC_CLMASK(x) (*(vuint8 *)(0xFC04801E+((x)*0x4000)))
1651 #define MCF_INTC_SLMASK(x) (*(vuint8 *)(0xFC04801F+((x)*0x4000)))
1652 #define MCF_INTC_ICR0(x) (*(vuint8 *)(0xFC048040+((x)*0x4000)))
1653 #define MCF_INTC_ICR1(x) (*(vuint8 *)(0xFC048041+((x)*0x4000)))
1654 #define MCF_INTC_ICR2(x) (*(vuint8 *)(0xFC048042+((x)*0x4000)))
1655 #define MCF_INTC_ICR3(x) (*(vuint8 *)(0xFC048043+((x)*0x4000)))
1656 #define MCF_INTC_ICR4(x) (*(vuint8 *)(0xFC048044+((x)*0x4000)))
1657 #define MCF_INTC_ICR5(x) (*(vuint8 *)(0xFC048045+((x)*0x4000)))
1658 #define MCF_INTC_ICR6(x) (*(vuint8 *)(0xFC048046+((x)*0x4000)))
1659 #define MCF_INTC_ICR7(x) (*(vuint8 *)(0xFC048047+((x)*0x4000)))
1660 #define MCF_INTC_ICR8(x) (*(vuint8 *)(0xFC048048+((x)*0x4000)))
1661 #define MCF_INTC_ICR9(x) (*(vuint8 *)(0xFC048049+((x)*0x4000)))
1662 #define MCF_INTC_ICR10(x) (*(vuint8 *)(0xFC04804A+((x)*0x4000)))
1663 #define MCF_INTC_ICR11(x) (*(vuint8 *)(0xFC04804B+((x)*0x4000)))
1664 #define MCF_INTC_ICR12(x) (*(vuint8 *)(0xFC04804C+((x)*0x4000)))
1665 #define MCF_INTC_ICR13(x) (*(vuint8 *)(0xFC04804D+((x)*0x4000)))
1666 #define MCF_INTC_ICR14(x) (*(vuint8 *)(0xFC04804E+((x)*0x4000)))
1667 #define MCF_INTC_ICR15(x) (*(vuint8 *)(0xFC04804F+((x)*0x4000)))
1668 #define MCF_INTC_ICR16(x) (*(vuint8 *)(0xFC048050+((x)*0x4000)))
1669 #define MCF_INTC_ICR17(x) (*(vuint8 *)(0xFC048051+((x)*0x4000)))
1670 #define MCF_INTC_ICR18(x) (*(vuint8 *)(0xFC048052+((x)*0x4000)))
1671 #define MCF_INTC_ICR19(x) (*(vuint8 *)(0xFC048053+((x)*0x4000)))
1672 #define MCF_INTC_ICR20(x) (*(vuint8 *)(0xFC048054+((x)*0x4000)))
1673 #define MCF_INTC_ICR21(x) (*(vuint8 *)(0xFC048055+((x)*0x4000)))
1674 #define MCF_INTC_ICR22(x) (*(vuint8 *)(0xFC048056+((x)*0x4000)))
1675 #define MCF_INTC_ICR23(x) (*(vuint8 *)(0xFC048057+((x)*0x4000)))
1676 #define MCF_INTC_ICR24(x) (*(vuint8 *)(0xFC048058+((x)*0x4000)))
1677 #define MCF_INTC_ICR25(x) (*(vuint8 *)(0xFC048059+((x)*0x4000)))
1678 #define MCF_INTC_ICR26(x) (*(vuint8 *)(0xFC04805A+((x)*0x4000)))
1679 #define MCF_INTC_ICR27(x) (*(vuint8 *)(0xFC04805B+((x)*0x4000)))
1680 #define MCF_INTC_ICR28(x) (*(vuint8 *)(0xFC04805C+((x)*0x4000)))
1681 #define MCF_INTC_ICR29(x) (*(vuint8 *)(0xFC04805D+((x)*0x4000)))
1682 #define MCF_INTC_ICR30(x) (*(vuint8 *)(0xFC04805E+((x)*0x4000)))
1683 #define MCF_INTC_ICR31(x) (*(vuint8 *)(0xFC04805F+((x)*0x4000)))
1684 #define MCF_INTC_ICR32(x) (*(vuint8 *)(0xFC048060+((x)*0x4000)))
1685 #define MCF_INTC_ICR33(x) (*(vuint8 *)(0xFC048061+((x)*0x4000)))
1686 #define MCF_INTC_ICR34(x) (*(vuint8 *)(0xFC048062+((x)*0x4000)))
1687 #define MCF_INTC_ICR35(x) (*(vuint8 *)(0xFC048063+((x)*0x4000)))
1688 #define MCF_INTC_ICR36(x) (*(vuint8 *)(0xFC048064+((x)*0x4000)))
1689 #define MCF_INTC_ICR37(x) (*(vuint8 *)(0xFC048065+((x)*0x4000)))
1690 #define MCF_INTC_ICR38(x) (*(vuint8 *)(0xFC048066+((x)*0x4000)))
1691 #define MCF_INTC_ICR39(x) (*(vuint8 *)(0xFC048067+((x)*0x4000)))
1692 #define MCF_INTC_ICR40(x) (*(vuint8 *)(0xFC048068+((x)*0x4000)))
1693 #define MCF_INTC_ICR41(x) (*(vuint8 *)(0xFC048069+((x)*0x4000)))
1694 #define MCF_INTC_ICR42(x) (*(vuint8 *)(0xFC04806A+((x)*0x4000)))
1695 #define MCF_INTC_ICR43(x) (*(vuint8 *)(0xFC04806B+((x)*0x4000)))
1696 #define MCF_INTC_ICR44(x) (*(vuint8 *)(0xFC04806C+((x)*0x4000)))
1697 #define MCF_INTC_ICR45(x) (*(vuint8 *)(0xFC04806D+((x)*0x4000)))
1698 #define MCF_INTC_ICR46(x) (*(vuint8 *)(0xFC04806E+((x)*0x4000)))
1699 #define MCF_INTC_ICR47(x) (*(vuint8 *)(0xFC04806F+((x)*0x4000)))
1700 #define MCF_INTC_ICR48(x) (*(vuint8 *)(0xFC048070+((x)*0x4000)))
1701 #define MCF_INTC_ICR49(x) (*(vuint8 *)(0xFC048071+((x)*0x4000)))
1702 #define MCF_INTC_ICR50(x) (*(vuint8 *)(0xFC048072+((x)*0x4000)))
1703 #define MCF_INTC_ICR51(x) (*(vuint8 *)(0xFC048073+((x)*0x4000)))
1704 #define MCF_INTC_ICR52(x) (*(vuint8 *)(0xFC048074+((x)*0x4000)))
1705 #define MCF_INTC_ICR53(x) (*(vuint8 *)(0xFC048075+((x)*0x4000)))
1706 #define MCF_INTC_ICR54(x) (*(vuint8 *)(0xFC048076+((x)*0x4000)))
1707 #define MCF_INTC_ICR55(x) (*(vuint8 *)(0xFC048077+((x)*0x4000)))
1708 #define MCF_INTC_ICR56(x) (*(vuint8 *)(0xFC048078+((x)*0x4000)))
1709 #define MCF_INTC_ICR57(x) (*(vuint8 *)(0xFC048079+((x)*0x4000)))
1710 #define MCF_INTC_ICR58(x) (*(vuint8 *)(0xFC04807A+((x)*0x4000)))
1711 #define MCF_INTC_ICR59(x) (*(vuint8 *)(0xFC04807B+((x)*0x4000)))
1712 #define MCF_INTC_ICR60(x) (*(vuint8 *)(0xFC04807C+((x)*0x4000)))
1713 #define MCF_INTC_ICR61(x) (*(vuint8 *)(0xFC04807D+((x)*0x4000)))
1714 #define MCF_INTC_ICR62(x) (*(vuint8 *)(0xFC04807E+((x)*0x4000)))
1715 #define MCF_INTC_ICR63(x) (*(vuint8 *)(0xFC04807F+((x)*0x4000)))
1716 #define MCF_INTC_SWIACK(x) (*(vuint8 *)(0xFC0480E0+((x)*0x4000)))
1717 #define MCF_INTC_L1IACK(x) (*(vuint8 *)(0xFC0480E4+((x)*0x4000)))
1718 #define MCF_INTC_L2IACK(x) (*(vuint8 *)(0xFC0480E8+((x)*0x4000)))
1719 #define MCF_INTC_L3IACK(x) (*(vuint8 *)(0xFC0480EC+((x)*0x4000)))
1720 #define MCF_INTC_L4IACK(x) (*(vuint8 *)(0xFC0480F0+((x)*0x4000)))
1721 #define MCF_INTC_L5IACK(x) (*(vuint8 *)(0xFC0480F4+((x)*0x4000)))
1722 #define MCF_INTC_L6IACK(x) (*(vuint8 *)(0xFC0480F8+((x)*0x4000)))
1723 #define MCF_INTC_L7IACK(x) (*(vuint8 *)(0xFC0480FC+((x)*0x4000)))
1724 
1725 /* Bit definitions and macros for MCF_INTC_IPRH */
1726 #define MCF_INTC_IPRH_INT32 (0x00000001)
1727 #define MCF_INTC_IPRH_INT33 (0x00000002)
1728 #define MCF_INTC_IPRH_INT34 (0x00000004)
1729 #define MCF_INTC_IPRH_INT35 (0x00000008)
1730 #define MCF_INTC_IPRH_INT36 (0x00000010)
1731 #define MCF_INTC_IPRH_INT37 (0x00000020)
1732 #define MCF_INTC_IPRH_INT38 (0x00000040)
1733 #define MCF_INTC_IPRH_INT39 (0x00000080)
1734 #define MCF_INTC_IPRH_INT40 (0x00000100)
1735 #define MCF_INTC_IPRH_INT41 (0x00000200)
1736 #define MCF_INTC_IPRH_INT42 (0x00000400)
1737 #define MCF_INTC_IPRH_INT43 (0x00000800)
1738 #define MCF_INTC_IPRH_INT44 (0x00001000)
1739 #define MCF_INTC_IPRH_INT45 (0x00002000)
1740 #define MCF_INTC_IPRH_INT46 (0x00004000)
1741 #define MCF_INTC_IPRH_INT47 (0x00008000)
1742 #define MCF_INTC_IPRH_INT48 (0x00010000)
1743 #define MCF_INTC_IPRH_INT49 (0x00020000)
1744 #define MCF_INTC_IPRH_INT50 (0x00040000)
1745 #define MCF_INTC_IPRH_INT51 (0x00080000)
1746 #define MCF_INTC_IPRH_INT52 (0x00100000)
1747 #define MCF_INTC_IPRH_INT53 (0x00200000)
1748 #define MCF_INTC_IPRH_INT54 (0x00400000)
1749 #define MCF_INTC_IPRH_INT55 (0x00800000)
1750 #define MCF_INTC_IPRH_INT56 (0x01000000)
1751 #define MCF_INTC_IPRH_INT57 (0x02000000)
1752 #define MCF_INTC_IPRH_INT58 (0x04000000)
1753 #define MCF_INTC_IPRH_INT59 (0x08000000)
1754 #define MCF_INTC_IPRH_INT60 (0x10000000)
1755 #define MCF_INTC_IPRH_INT61 (0x20000000)
1756 #define MCF_INTC_IPRH_INT62 (0x40000000)
1757 #define MCF_INTC_IPRH_INT63 (0x80000000)
1758 
1759 /* Bit definitions and macros for MCF_INTC_IPRL */
1760 #define MCF_INTC_IPRL_INT0 (0x00000001)
1761 #define MCF_INTC_IPRL_INT1 (0x00000002)
1762 #define MCF_INTC_IPRL_INT2 (0x00000004)
1763 #define MCF_INTC_IPRL_INT3 (0x00000008)
1764 #define MCF_INTC_IPRL_INT4 (0x00000010)
1765 #define MCF_INTC_IPRL_INT5 (0x00000020)
1766 #define MCF_INTC_IPRL_INT6 (0x00000040)
1767 #define MCF_INTC_IPRL_INT7 (0x00000080)
1768 #define MCF_INTC_IPRL_INT8 (0x00000100)
1769 #define MCF_INTC_IPRL_INT9 (0x00000200)
1770 #define MCF_INTC_IPRL_INT10 (0x00000400)
1771 #define MCF_INTC_IPRL_INT11 (0x00000800)
1772 #define MCF_INTC_IPRL_INT12 (0x00001000)
1773 #define MCF_INTC_IPRL_INT13 (0x00002000)
1774 #define MCF_INTC_IPRL_INT14 (0x00004000)
1775 #define MCF_INTC_IPRL_INT15 (0x00008000)
1776 #define MCF_INTC_IPRL_INT16 (0x00010000)
1777 #define MCF_INTC_IPRL_INT17 (0x00020000)
1778 #define MCF_INTC_IPRL_INT18 (0x00040000)
1779 #define MCF_INTC_IPRL_INT19 (0x00080000)
1780 #define MCF_INTC_IPRL_INT20 (0x00100000)
1781 #define MCF_INTC_IPRL_INT21 (0x00200000)
1782 #define MCF_INTC_IPRL_INT22 (0x00400000)
1783 #define MCF_INTC_IPRL_INT23 (0x00800000)
1784 #define MCF_INTC_IPRL_INT24 (0x01000000)
1785 #define MCF_INTC_IPRL_INT25 (0x02000000)
1786 #define MCF_INTC_IPRL_INT26 (0x04000000)
1787 #define MCF_INTC_IPRL_INT27 (0x08000000)
1788 #define MCF_INTC_IPRL_INT28 (0x10000000)
1789 #define MCF_INTC_IPRL_INT29 (0x20000000)
1790 #define MCF_INTC_IPRL_INT30 (0x40000000)
1791 #define MCF_INTC_IPRL_INT31 (0x80000000)
1792 
1793 /* Bit definitions and macros for MCF_INTC_IMRH */
1794 #define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
1795 #define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
1796 #define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
1797 #define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
1798 #define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
1799 #define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
1800 #define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
1801 #define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
1802 #define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
1803 #define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
1804 #define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
1805 #define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
1806 #define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
1807 #define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
1808 #define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
1809 #define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
1810 #define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
1811 #define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
1812 #define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
1813 #define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
1814 #define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
1815 #define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
1816 #define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
1817 #define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
1818 #define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
1819 #define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
1820 #define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
1821 #define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
1822 #define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
1823 #define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
1824 #define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
1825 #define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
1826 
1827 /* Bit definitions and macros for MCF_INTC_IMRL */
1828 #define MCF_INTC_IMRL_INT_MASK0 (0x00000001)
1829 #define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
1830 #define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
1831 #define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
1832 #define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
1833 #define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
1834 #define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
1835 #define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
1836 #define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
1837 #define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
1838 #define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
1839 #define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
1840 #define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
1841 #define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
1842 #define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
1843 #define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
1844 #define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
1845 #define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
1846 #define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
1847 #define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
1848 #define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
1849 #define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
1850 #define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
1851 #define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
1852 #define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
1853 #define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
1854 #define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
1855 #define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
1856 #define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
1857 #define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
1858 #define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
1859 #define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
1860 
1861 /* Bit definitions and macros for MCF_INTC_INTFRCH */
1862 #define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
1863 #define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
1864 #define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
1865 #define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
1866 #define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
1867 #define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
1868 #define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
1869 #define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
1870 #define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
1871 #define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
1872 #define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
1873 #define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
1874 #define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
1875 #define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
1876 #define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
1877 #define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
1878 #define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
1879 #define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
1880 #define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
1881 #define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
1882 #define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
1883 #define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
1884 #define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
1885 #define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
1886 #define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
1887 #define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
1888 #define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
1889 #define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
1890 #define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
1891 #define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
1892 #define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
1893 #define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
1894 
1895 /* Bit definitions and macros for MCF_INTC_INTFRCL */
1896 #define MCF_INTC_INTFRCL_INTFRC0 (0x00000001)
1897 #define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
1898 #define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
1899 #define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
1900 #define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
1901 #define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
1902 #define MCF_INTC_INTFRCL_INTFRC6 (0x00000040)
1903 #define MCF_INTC_INTFRCL_INTFRC7 (0x00000080)
1904 #define MCF_INTC_INTFRCL_INTFRC8 (0x00000100)
1905 #define MCF_INTC_INTFRCL_INTFRC9 (0x00000200)
1906 #define MCF_INTC_INTFRCL_INTFRC10 (0x00000400)
1907 #define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
1908 #define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
1909 #define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
1910 #define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
1911 #define MCF_INTC_INTFRCL_INTFRC15 (0x00008000)
1912 #define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
1913 #define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
1914 #define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
1915 #define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
1916 #define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
1917 #define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
1918 #define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
1919 #define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
1920 #define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
1921 #define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
1922 #define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
1923 #define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
1924 #define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
1925 #define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
1926 #define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
1927 #define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
1928 
1929 /* Bit definitions and macros for MCF_INTC_ICONFIG */
1930 #define MCF_INTC_ICONFIG_EMASK (0x0020)
1931 #define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200)
1932 #define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400)
1933 #define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800)
1934 #define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000)
1935 #define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000)
1936 #define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000)
1937 #define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000)
1938 
1939 /* Bit definitions and macros for MCF_INTC_SIMR */
1940 #define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)<<0)
1941 
1942 /* Bit definitions and macros for MCF_INTC_CIMR */
1943 #define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)<<0)
1944 
1945 /* Bit definitions and macros for MCF_INTC_CLMASK */
1946 #define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)<<0)
1947 
1948 /* Bit definitions and macros for MCF_INTC_SLMASK */
1949 #define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)<<0)
1950 
1951 /* Bit definitions and macros for MCF_INTC_ICR */
1952 #define MCF_INTC_ICR_IL(x) (((x)&0x07)<<0)
1953 
1954 /* Bit definitions and macros for MCF_INTC_SWIACK */
1955 #define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
1956 
1957 /* Bit definitions and macros for MCF_INTC_LIACK */
1958 #define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
1959 
1960 /*********************************************************************
1961 *
1962 * Interrupt Controller (INTC_IACK)
1963 *
1964 *********************************************************************/
1965 
1966 /* Register read/write macros */
1967 #define MCF_INTC_IACK_GSWIACK (*(vuint8 *)(0xFC0540E0))
1968 #define MCF_INTC_IACK_GL1IACK (*(vuint8 *)(0xFC0540E4))
1969 #define MCF_INTC_IACK_GL2IACK (*(vuint8 *)(0xFC0540E8))
1970 #define MCF_INTC_IACK_GL3IACK (*(vuint8 *)(0xFC0540EC))
1971 #define MCF_INTC_IACK_GL4IACK (*(vuint8 *)(0xFC0540F0))
1972 #define MCF_INTC_IACK_GL5IACK (*(vuint8 *)(0xFC0540F4))
1973 #define MCF_INTC_IACK_GL6IACK (*(vuint8 *)(0xFC0540F8))
1974 #define MCF_INTC_IACK_GL7IACK (*(vuint8 *)(0xFC0540FC))
1975 #define MCF_INTC_IACK_GLIACK(x) (*(vuint8 *)(0xFC0540E4+((x-1)*0x004)))
1976 
1977 /* Bit definitions and macros for MCF_INTC_IACK_GSWIACK */
1978 #define MCF_INTC_IACK_GSWIACK_VECTOR(x) (((x)&0xFF)<<0)
1979 
1980 /* Bit definitions and macros for MCF_INTC_IACK_GLIACK */
1981 #define MCF_INTC_IACK_GLIACK_VECTOR(x) (((x)&0xFF)<<0)
1982 
1983 /*********************************************************************
1984 *
1985 * I2C Module (I2C)
1986 *
1987 *********************************************************************/
1988 
1989 /* Register read/write macros */
1990 #define MCF_I2C_I2AR (*(vuint8 *)(0xFC058000))
1991 #define MCF_I2C_I2FDR (*(vuint8 *)(0xFC058004))
1992 #define MCF_I2C_I2CR (*(vuint8 *)(0xFC058008))
1993 #define MCF_I2C_I2SR (*(vuint8 *)(0xFC05800C))
1994 #define MCF_I2C_I2DR (*(vuint8 *)(0xFC058010))
1995 
1996 /* Bit definitions and macros for MCF_I2C_I2AR */
1997 #define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1)
1998 
1999 /* Bit definitions and macros for MCF_I2C_I2FDR */
2000 #define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
2001 
2002 /* Bit definitions and macros for MCF_I2C_I2CR */
2003 #define MCF_I2C_I2CR_RSTA (0x04)
2004 #define MCF_I2C_I2CR_TXAK (0x08)
2005 #define MCF_I2C_I2CR_MTX (0x10)
2006 #define MCF_I2C_I2CR_MSTA (0x20)
2007 #define MCF_I2C_I2CR_IIEN (0x40)
2008 #define MCF_I2C_I2CR_IEN (0x80)
2009 
2010 /* Bit definitions and macros for MCF_I2C_I2SR */
2011 #define MCF_I2C_I2SR_RXAK (0x01)
2012 #define MCF_I2C_I2SR_IIF (0x02)
2013 #define MCF_I2C_I2SR_SRW (0x04)
2014 #define MCF_I2C_I2SR_IAL (0x10)
2015 #define MCF_I2C_I2SR_IBB (0x20)
2016 #define MCF_I2C_I2SR_IAAS (0x40)
2017 #define MCF_I2C_I2SR_ICF (0x80)
2018 
2019 /* Bit definitions and macros for MCF_I2C_I2DR */
2020 #define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0)
2021 
2022 /*********************************************************************
2023 *
2024 * Queued Serial Peripheral Interface (QSPI)
2025 *
2026 *********************************************************************/
2027 
2028 /* Register read/write macros */
2029 #define MCF_QSPI_QMR (*(vuint16*)(0xFC05C000))
2030 #define MCF_QSPI_QDLYR (*(vuint16*)(0xFC05C004))
2031 #define MCF_QSPI_QWR (*(vuint16*)(0xFC05C008))
2032 #define MCF_QSPI_QIR (*(vuint16*)(0xFC05C00C))
2033 #define MCF_QSPI_QAR (*(vuint16*)(0xFC05C010))
2034 #define MCF_QSPI_QDR (*(vuint16*)(0xFC05C014))
2035 
2036 /* Bit definitions and macros for MCF_QSPI_QMR */
2037 #define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0)
2038 #define MCF_QSPI_QMR_CPHA (0x0100)
2039 #define MCF_QSPI_QMR_CPOL (0x0200)
2040 #define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
2041 #define MCF_QSPI_QMR_DOHIE (0x4000)
2042 #define MCF_QSPI_QMR_MSTR (0x8000)
2043 
2044 /* Bit definitions and macros for MCF_QSPI_QDLYR */
2045 #define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0)
2046 #define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
2047 #define MCF_QSPI_QDLYR_SPE (0x8000)
2048 
2049 /* Bit definitions and macros for MCF_QSPI_QWR */
2050 #define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0)
2051 #define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
2052 #define MCF_QSPI_QWR_CSIV (0x1000)
2053 #define MCF_QSPI_QWR_WRTO (0x2000)
2054 #define MCF_QSPI_QWR_WREN (0x4000)
2055 #define MCF_QSPI_QWR_HALT (0x8000)
2056 
2057 /* Bit definitions and macros for MCF_QSPI_QIR */
2058 #define MCF_QSPI_QIR_SPIF (0x0001)
2059 #define MCF_QSPI_QIR_ABRT (0x0004)
2060 #define MCF_QSPI_QIR_WCEF (0x0008)
2061 #define MCF_QSPI_QIR_SPIFE (0x0100)
2062 #define MCF_QSPI_QIR_ABRTE (0x0400)
2063 #define MCF_QSPI_QIR_WCEFE (0x0800)
2064 #define MCF_QSPI_QIR_ABRTL (0x1000)
2065 #define MCF_QSPI_QIR_ABRTB (0x4000)
2066 #define MCF_QSPI_QIR_WCEFB (0x8000)
2067 
2068 /* Bit definitions and macros for MCF_QSPI_QAR */
2069 #define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0)
2070 #define MCF_QSPI_QAR_TRANS (0x0000)
2071 #define MCF_QSPI_QAR_RECV (0x0010)
2072 #define MCF_QSPI_QAR_CMD (0x0020)
2073 
2074 /* Bit definitions and macros for MCF_QSPI_QDR */
2075 #define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0)
2076 #define MCF_QSPI_QDR_CONT (0x8000)
2077 #define MCF_QSPI_QDR_BITSE (0x4000)
2078 #define MCF_QSPI_QDR_DT (0x2000)
2079 #define MCF_QSPI_QDR_DSCK (0x1000)
2080 #define MCF_QSPI_QDR_QSPI_CS3 (0x0800)
2081 #define MCF_QSPI_QDR_QSPI_CS2 (0x0400)
2082 #define MCF_QSPI_QDR_QSPI_CS1 (0x0200)
2083 #define MCF_QSPI_QDR_QSPI_CS0 (0x0100)
2084 
2085 /*********************************************************************
2086 *
2087 * Universal Asynchronous Receiver Transmitter (UART)
2088 *
2089 *********************************************************************/
2090 
2091 /* Register read/write macros */
2092 #define MCF_UART0_UMR (*(vuint8 *)(0xFC060000))
2093 #define MCF_UART0_USR (*(vuint8 *)(0xFC060004))
2094 #define MCF_UART0_UCSR (*(vuint8 *)(0xFC060004))
2095 #define MCF_UART0_UCR (*(vuint8 *)(0xFC060008))
2096 #define MCF_UART0_URB (*(vuint8 *)(0xFC06000C))
2097 #define MCF_UART0_UTB (*(vuint8 *)(0xFC06000C))
2098 #define MCF_UART0_UIPCR (*(vuint8 *)(0xFC060010))
2099 #define MCF_UART0_UACR (*(vuint8 *)(0xFC060010))
2100 #define MCF_UART0_UISR (*(vuint8 *)(0xFC060014))
2101 #define MCF_UART0_UIMR (*(vuint8 *)(0xFC060014))
2102 #define MCF_UART0_UBG1 (*(vuint8 *)(0xFC060018))
2103 #define MCF_UART0_UBG2 (*(vuint8 *)(0xFC06001C))
2104 #define MCF_UART0_UIP (*(vuint8 *)(0xFC060034))
2105 #define MCF_UART0_UOP1 (*(vuint8 *)(0xFC060038))
2106 #define MCF_UART0_UOP0 (*(vuint8 *)(0xFC06003C))
2107 #define MCF_UART1_UMR (*(vuint8 *)(0xFC064000))
2108 #define MCF_UART1_USR (*(vuint8 *)(0xFC064004))
2109 #define MCF_UART1_UCSR (*(vuint8 *)(0xFC064004))
2110 #define MCF_UART1_UCR (*(vuint8 *)(0xFC064008))
2111 #define MCF_UART1_URB (*(vuint8 *)(0xFC06400C))
2112 #define MCF_UART1_UTB (*(vuint8 *)(0xFC06400C))
2113 #define MCF_UART1_UIPCR (*(vuint8 *)(0xFC064010))
2114 #define MCF_UART1_UACR (*(vuint8 *)(0xFC064010))
2115 #define MCF_UART1_UISR (*(vuint8 *)(0xFC064014))
2116 #define MCF_UART1_UIMR (*(vuint8 *)(0xFC064014))
2117 #define MCF_UART1_UBG1 (*(vuint8 *)(0xFC064018))
2118 #define MCF_UART1_UBG2 (*(vuint8 *)(0xFC06401C))
2119 #define MCF_UART1_UIP (*(vuint8 *)(0xFC064034))
2120 #define MCF_UART1_UOP1 (*(vuint8 *)(0xFC064038))
2121 #define MCF_UART1_UOP0 (*(vuint8 *)(0xFC06403C))
2122 #define MCF_UART2_UMR (*(vuint8 *)(0xFC068000))
2123 #define MCF_UART2_USR (*(vuint8 *)(0xFC068004))
2124 #define MCF_UART2_UCSR (*(vuint8 *)(0xFC068004))
2125 #define MCF_UART2_UCR (*(vuint8 *)(0xFC068008))
2126 #define MCF_UART2_URB (*(vuint8 *)(0xFC06800C))
2127 #define MCF_UART2_UTB (*(vuint8 *)(0xFC06800C))
2128 #define MCF_UART2_UIPCR (*(vuint8 *)(0xFC068010))
2129 #define MCF_UART2_UACR (*(vuint8 *)(0xFC068010))
2130 #define MCF_UART2_UISR (*(vuint8 *)(0xFC068014))
2131 #define MCF_UART2_UIMR (*(vuint8 *)(0xFC068014))
2132 #define MCF_UART2_UBG1 (*(vuint8 *)(0xFC068018))
2133 #define MCF_UART2_UBG2 (*(vuint8 *)(0xFC06801C))
2134 #define MCF_UART2_UIP (*(vuint8 *)(0xFC068034))
2135 #define MCF_UART2_UOP1 (*(vuint8 *)(0xFC068038))
2136 #define MCF_UART2_UOP0 (*(vuint8 *)(0xFC06803C))
2137 #define MCF_UART_UMR(x) (*(vuint8 *)(0xFC060000+((x)*0x4000)))
2138 #define MCF_UART_USR(x) (*(vuint8 *)(0xFC060004+((x)*0x4000)))
2139 #define MCF_UART_UCSR(x) (*(vuint8 *)(0xFC060004+((x)*0x4000)))
2140 #define MCF_UART_UCR(x) (*(vuint8 *)(0xFC060008+((x)*0x4000)))
2141 #define MCF_UART_URB(x) (*(vuint8 *)(0xFC06000C+((x)*0x4000)))
2142 #define MCF_UART_UTB(x) (*(vuint8 *)(0xFC06000C+((x)*0x4000)))
2143 #define MCF_UART_UIPCR(x) (*(vuint8 *)(0xFC060010+((x)*0x4000)))
2144 #define MCF_UART_UACR(x) (*(vuint8 *)(0xFC060010+((x)*0x4000)))
2145 #define MCF_UART_UISR(x) (*(vuint8 *)(0xFC060014+((x)*0x4000)))
2146 #define MCF_UART_UIMR(x) (*(vuint8 *)(0xFC060014+((x)*0x4000)))
2147 #define MCF_UART_UBG1(x) (*(vuint8 *)(0xFC060018+((x)*0x4000)))
2148 #define MCF_UART_UBG2(x) (*(vuint8 *)(0xFC06001C+((x)*0x4000)))
2149 #define MCF_UART_UIP(x) (*(vuint8 *)(0xFC060034+((x)*0x4000)))
2150 #define MCF_UART_UOP1(x) (*(vuint8 *)(0xFC060038+((x)*0x4000)))
2151 #define MCF_UART_UOP0(x) (*(vuint8 *)(0xFC06003C+((x)*0x4000)))
2152 
2153 /* Bit definitions and macros for MCF_UART_UMR */
2154 #define MCF_UART_UMR_BC(x) (((x)&0x03)<<0)
2155 #define MCF_UART_UMR_PT (0x04)
2156 #define MCF_UART_UMR_PM(x) (((x)&0x03)<<3)
2157 #define MCF_UART_UMR_ERR (0x20)
2158 #define MCF_UART_UMR_RXIRQ (0x40)
2159 #define MCF_UART_UMR_RXRTS (0x80)
2160 #define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0)
2161 #define MCF_UART_UMR_TXCTS (0x10)
2162 #define MCF_UART_UMR_TXRTS (0x20)
2163 #define MCF_UART_UMR_CM(x) (((x)&0x03)<<6)
2164 #define MCF_UART_UMR_PM_MULTI_ADDR (0x1C)
2165 #define MCF_UART_UMR_PM_MULTI_DATA (0x18)
2166 #define MCF_UART_UMR_PM_NONE (0x10)
2167 #define MCF_UART_UMR_PM_FORCE_HI (0x0C)
2168 #define MCF_UART_UMR_PM_FORCE_LO (0x08)
2169 #define MCF_UART_UMR_PM_ODD (0x04)
2170 #define MCF_UART_UMR_PM_EVEN (0x00)
2171 #define MCF_UART_UMR_BC_5 (0x00)
2172 #define MCF_UART_UMR_BC_6 (0x01)
2173 #define MCF_UART_UMR_BC_7 (0x02)
2174 #define MCF_UART_UMR_BC_8 (0x03)
2175 #define MCF_UART_UMR_CM_NORMAL (0x00)
2176 #define MCF_UART_UMR_CM_ECHO (0x40)
2177 #define MCF_UART_UMR_CM_LOCAL_LOOP (0x80)
2178 #define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0)
2179 #define MCF_UART_UMR_SB_STOP_BITS_1 (0x07)
2180 #define MCF_UART_UMR_SB_STOP_BITS_15 (0x08)
2181 #define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F)
2182 
2183 /* Bit definitions and macros for MCF_UART_USR */
2184 #define MCF_UART_USR_RXRDY (0x01)
2185 #define MCF_UART_USR_FFULL (0x02)
2186 #define MCF_UART_USR_TXRDY (0x04)
2187 #define MCF_UART_USR_TXEMP (0x08)
2188 #define MCF_UART_USR_OE (0x10)
2189 #define MCF_UART_USR_PE (0x20)
2190 #define MCF_UART_USR_FE (0x40)
2191 #define MCF_UART_USR_RB (0x80)
2192 
2193 /* Bit definitions and macros for MCF_UART_UCSR */
2194 #define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0)
2195 #define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4)
2196 #define MCF_UART_UCSR_RCS_SYS_CLK (0xD0)
2197 #define MCF_UART_UCSR_RCS_CTM16 (0xE0)
2198 #define MCF_UART_UCSR_RCS_CTM (0xF0)
2199 #define MCF_UART_UCSR_TCS_SYS_CLK (0x0D)
2200 #define MCF_UART_UCSR_TCS_CTM16 (0x0E)
2201 #define MCF_UART_UCSR_TCS_CTM (0x0F)
2202 
2203 /* Bit definitions and macros for MCF_UART_UCR */
2204 #define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0)
2205 #define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2)
2206 #define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4)
2207 #define MCF_UART_UCR_NONE (0x00)
2208 #define MCF_UART_UCR_STOP_BREAK (0x70)
2209 #define MCF_UART_UCR_START_BREAK (0x60)
2210 #define MCF_UART_UCR_BKCHGINT (0x50)
2211 #define MCF_UART_UCR_RESET_ERROR (0x40)
2212 #define MCF_UART_UCR_RESET_TX (0x30)
2213 #define MCF_UART_UCR_RESET_RX (0x20)
2214 #define MCF_UART_UCR_RESET_MR (0x10)
2215 #define MCF_UART_UCR_TX_DISABLED (0x08)
2216 #define MCF_UART_UCR_TX_ENABLED (0x04)
2217 #define MCF_UART_UCR_RX_DISABLED (0x02)
2218 #define MCF_UART_UCR_RX_ENABLED (0x01)
2219 
2220 /* Bit definitions and macros for MCF_UART_UIPCR */
2221 #define MCF_UART_UIPCR_CTS (0x01)
2222 #define MCF_UART_UIPCR_COS (0x10)
2223 
2224 /* Bit definitions and macros for MCF_UART_UACR */
2225 #define MCF_UART_UACR_IEC (0x01)
2226 
2227 /* Bit definitions and macros for MCF_UART_UISR */
2228 #define MCF_UART_UISR_TXRDY (0x01)
2229 #define MCF_UART_UISR_RXRDY_FU (0x02)
2230 #define MCF_UART_UISR_DB (0x04)
2231 #define MCF_UART_UISR_RXFTO (0x08)
2232 #define MCF_UART_UISR_TXFIFO (0x10)
2233 #define MCF_UART_UISR_RXFIFO (0x20)
2234 #define MCF_UART_UISR_COS (0x80)
2235 
2236 /* Bit definitions and macros for MCF_UART_UIMR */
2237 #define MCF_UART_UIMR_TXRDY (0x01)
2238 #define MCF_UART_UIMR_RXRDY_FU (0x02)
2239 #define MCF_UART_UIMR_DB (0x04)
2240 #define MCF_UART_UIMR_COS (0x80)
2241 
2242 /* Bit definitions and macros for MCF_UART_UIP */
2243 #define MCF_UART_UIP_CTS (0x01)
2244 
2245 /* Bit definitions and macros for MCF_UART_UOP1 */
2246 #define MCF_UART_UOP1_RTS (0x01)
2247 
2248 /* Bit definitions and macros for MCF_UART_UOP0 */
2249 #define MCF_UART_UOP0_RTS (0x01)
2250 
2251 /*********************************************************************
2252 *
2253 * DMA Timers (DTIM)
2254 *
2255 *********************************************************************/
2256 
2257 /* Register read/write macros */
2258 #define MCF_DTIM0_DTMR (*(vuint16*)(0xFC070000))
2259 #define MCF_DTIM0_DTXMR (*(vuint8 *)(0xFC070002))
2260 #define MCF_DTIM0_DTER (*(vuint8 *)(0xFC070003))
2261 #define MCF_DTIM0_DTRR (*(vuint32*)(0xFC070004))
2262 #define MCF_DTIM0_DTCR (*(vuint32*)(0xFC070008))
2263 #define MCF_DTIM0_DTCN (*(vuint32*)(0xFC07000C))
2264 #define MCF_DTIM1_DTMR (*(vuint16*)(0xFC074000))
2265 #define MCF_DTIM1_DTXMR (*(vuint8 *)(0xFC074002))
2266 #define MCF_DTIM1_DTER (*(vuint8 *)(0xFC074003))
2267 #define MCF_DTIM1_DTRR (*(vuint32*)(0xFC074004))
2268 #define MCF_DTIM1_DTCR (*(vuint32*)(0xFC074008))
2269 #define MCF_DTIM1_DTCN (*(vuint32*)(0xFC07400C))
2270 #define MCF_DTIM2_DTMR (*(vuint16*)(0xFC078000))
2271 #define MCF_DTIM2_DTXMR (*(vuint8 *)(0xFC078002))
2272 #define MCF_DTIM2_DTER (*(vuint8 *)(0xFC078003))
2273 #define MCF_DTIM2_DTRR (*(vuint32*)(0xFC078004))
2274 #define MCF_DTIM2_DTCR (*(vuint32*)(0xFC078008))
2275 #define MCF_DTIM2_DTCN (*(vuint32*)(0xFC07800C))
2276 #define MCF_DTIM3_DTMR (*(vuint16*)(0xFC07C000))
2277 #define MCF_DTIM3_DTXMR (*(vuint8 *)(0xFC07C002))
2278 #define MCF_DTIM3_DTER (*(vuint8 *)(0xFC07C003))
2279 #define MCF_DTIM3_DTRR (*(vuint32*)(0xFC07C004))
2280 #define MCF_DTIM3_DTCR (*(vuint32*)(0xFC07C008))
2281 #define MCF_DTIM3_DTCN (*(vuint32*)(0xFC07C00C))
2282 #define MCF_DTIM_DTMR(x) (*(vuint16*)(0xFC070000+((x)*0x4000)))
2283 #define MCF_DTIM_DTXMR(x) (*(vuint8 *)(0xFC070002+((x)*0x4000)))
2284 #define MCF_DTIM_DTER(x) (*(vuint8 *)(0xFC070003+((x)*0x4000)))
2285 #define MCF_DTIM_DTRR(x) (*(vuint32*)(0xFC070004+((x)*0x4000)))
2286 #define MCF_DTIM_DTCR(x) (*(vuint32*)(0xFC070008+((x)*0x4000)))
2287 #define MCF_DTIM_DTCN(x) (*(vuint32*)(0xFC07000C+((x)*0x4000)))
2288 
2289 /* Bit definitions and macros for MCF_DTIM_DTMR */
2290 #define MCF_DTIM_DTMR_RST (0x0001)
2291 #define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1)
2292 #define MCF_DTIM_DTMR_FRR (0x0008)
2293 #define MCF_DTIM_DTMR_ORRI (0x0010)
2294 #define MCF_DTIM_DTMR_OM (0x0020)
2295 #define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6)
2296 #define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8)
2297 #define MCF_DTIM_DTMR_CE_ANY (0x00C0)
2298 #define MCF_DTIM_DTMR_CE_FALL (0x0080)
2299 #define MCF_DTIM_DTMR_CE_RISE (0x0040)
2300 #define MCF_DTIM_DTMR_CE_NONE (0x0000)
2301 #define MCF_DTIM_DTMR_CLK_DTIN (0x0006)
2302 #define MCF_DTIM_DTMR_CLK_DIV16 (0x0004)
2303 #define MCF_DTIM_DTMR_CLK_DIV1 (0x0002)
2304 #define MCF_DTIM_DTMR_CLK_STOP (0x0000)
2305 
2306 /* Bit definitions and macros for MCF_DTIM_DTXMR */
2307 #define MCF_DTIM_DTXMR_MODE16 (0x01)
2308 #define MCF_DTIM_DTXMR_DMAEN (0x80)
2309 
2310 /* Bit definitions and macros for MCF_DTIM_DTER */
2311 #define MCF_DTIM_DTER_CAP (0x01)
2312 #define MCF_DTIM_DTER_REF (0x02)
2313 
2314 /* Bit definitions and macros for MCF_DTIM_DTRR */
2315 #define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)
2316 
2317 /* Bit definitions and macros for MCF_DTIM_DTCR */
2318 #define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)
2319 
2320 /* Bit definitions and macros for MCF_DTIM_DTCN */
2321 #define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)
2322 
2323 /*********************************************************************
2324 *
2325 * Programmable Interrupt Timer Modules (PIT)
2326 *
2327 *********************************************************************/
2328 
2329 /* Register read/write macros */
2330 #define MCF_PIT0_PCSR (*(vuint16*)(0xFC080000))
2331 #define MCF_PIT0_PMR (*(vuint16*)(0xFC080002))
2332 #define MCF_PIT0_PCNTR (*(vuint16*)(0xFC080004))
2333 #define MCF_PIT1_PCSR (*(vuint16*)(0xFC084000))
2334 #define MCF_PIT1_PMR (*(vuint16*)(0xFC084002))
2335 #define MCF_PIT1_PCNTR (*(vuint16*)(0xFC084004))
2336 #define MCF_PIT2_PCSR (*(vuint16*)(0xFC088000))
2337 #define MCF_PIT2_PMR (*(vuint16*)(0xFC088002))
2338 #define MCF_PIT2_PCNTR (*(vuint16*)(0xFC088004))
2339 #define MCF_PIT3_PCSR (*(vuint16*)(0xFC08C000))
2340 #define MCF_PIT3_PMR (*(vuint16*)(0xFC08C002))
2341 #define MCF_PIT3_PCNTR (*(vuint16*)(0xFC08C004))
2342 #define MCF_PIT_PCSR(x) (*(vuint16*)(0xFC080000+((x)*0x4000)))
2343 #define MCF_PIT_PMR(x) (*(vuint16*)(0xFC080002+((x)*0x4000)))
2344 #define MCF_PIT_PCNTR(x) (*(vuint16*)(0xFC080004+((x)*0x4000)))
2345 
2346 /* Bit definitions and macros for MCF_PIT_PCSR */
2347 #define MCF_PIT_PCSR_EN (0x0001)
2348 #define MCF_PIT_PCSR_RLD (0x0002)
2349 #define MCF_PIT_PCSR_PIF (0x0004)
2350 #define MCF_PIT_PCSR_PIE (0x0008)
2351 #define MCF_PIT_PCSR_OVW (0x0010)
2352 #define MCF_PIT_PCSR_HALTED (0x0020)
2353 #define MCF_PIT_PCSR_DOZE (0x0040)
2354 #define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8)
2355 
2356 /* Bit definitions and macros for MCF_PIT_PMR */
2357 #define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0)
2358 
2359 /* Bit definitions and macros for MCF_PIT_PCNTR */
2360 #define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0)
2361 
2362 /*********************************************************************
2363 *
2364 * Pulse Width Modulation (PWM)
2365 *
2366 *********************************************************************/
2367 
2368 /* Register read/write macros */
2369 #define MCF_PWM_PWME (*(vuint8 *)(0xFC090020))
2370 #define MCF_PWM_PWMPOL (*(vuint8 *)(0xFC090021))
2371 #define MCF_PWM_PWMCLK (*(vuint8 *)(0xFC090022))
2372 #define MCF_PWM_PWMPRCLK (*(vuint8 *)(0xFC090023))
2373 #define MCF_PWM_PWMCAE (*(vuint8 *)(0xFC090024))
2374 #define MCF_PWM_PWMCTL (*(vuint8 *)(0xFC090025))
2375 #define MCF_PWM_PWMSCLA (*(vuint8 *)(0xFC090028))
2376 #define MCF_PWM_PWMSCLB (*(vuint8 *)(0xFC090029))
2377 #define MCF_PWM_PWMCNT0 (*(vuint8 *)(0xFC09002C))
2378 #define MCF_PWM_PWMCNT1 (*(vuint8 *)(0xFC09002D))
2379 #define MCF_PWM_PWMCNT2 (*(vuint8 *)(0xFC09002E))
2380 #define MCF_PWM_PWMCNT3 (*(vuint8 *)(0xFC09002F))
2381 #define MCF_PWM_PWMCNT4 (*(vuint8 *)(0xFC090030))
2382 #define MCF_PWM_PWMCNT5 (*(vuint8 *)(0xFC090031))
2383 #define MCF_PWM_PWMCNT6 (*(vuint8 *)(0xFC090032))
2384 #define MCF_PWM_PWMCNT7 (*(vuint8 *)(0xFC090033))
2385 #define MCF_PWM_PWMCNT(x) (*(vuint8 *)(0xFC09002C+((x)*0x001)))
2386 #define MCF_PWM_PWMPER0 (*(vuint8 *)(0xFC090034))
2387 #define MCF_PWM_PWMPER1 (*(vuint8 *)(0xFC090035))
2388 #define MCF_PWM_PWMPER2 (*(vuint8 *)(0xFC090036))
2389 #define MCF_PWM_PWMPER3 (*(vuint8 *)(0xFC090037))
2390 #define MCF_PWM_PWMPER4 (*(vuint8 *)(0xFC090038))
2391 #define MCF_PWM_PWMPER5 (*(vuint8 *)(0xFC090039))
2392 #define MCF_PWM_PWMPER6 (*(vuint8 *)(0xFC09003A))
2393 #define MCF_PWM_PWMPER7 (*(vuint8 *)(0xFC09003B))
2394 #define MCF_PWM_PWMPER(x) (*(vuint8 *)(0xFC090034+((x)*0x001)))
2395 #define MCF_PWM_PWMDTY0 (*(vuint8 *)(0xFC09003C))
2396 #define MCF_PWM_PWMDTY1 (*(vuint8 *)(0xFC09003D))
2397 #define MCF_PWM_PWMDTY2 (*(vuint8 *)(0xFC09003E))
2398 #define MCF_PWM_PWMDTY3 (*(vuint8 *)(0xFC09003F))
2399 #define MCF_PWM_PWMDTY4 (*(vuint8 *)(0xFC090040))
2400 #define MCF_PWM_PWMDTY5 (*(vuint8 *)(0xFC090041))
2401 #define MCF_PWM_PWMDTY6 (*(vuint8 *)(0xFC090042))
2402 #define MCF_PWM_PWMDTY7 (*(vuint8 *)(0xFC090043))
2403 #define MCF_PWM_PWMDTY(x) (*(vuint8 *)(0xFC09003C+((x)*0x001)))
2404 #define MCF_PWM_PWMSDN (*(vuint8 *)(0xFC090044))
2405 
2406 /* Bit definitions and macros for MCF_PWM_PWME */
2407 #define MCF_PWM_PWME_PWME0 (0x01)
2408 #define MCF_PWM_PWME_PWME1 (0x02)
2409 #define MCF_PWM_PWME_PWME2 (0x04)
2410 #define MCF_PWM_PWME_PWME3 (0x08)
2411 #define MCF_PWM_PWME_PWME4 (0x10)
2412 #define MCF_PWM_PWME_PWME5 (0x20)
2413 #define MCF_PWM_PWME_PWME6 (0x40)
2414 #define MCF_PWM_PWME_PWME7 (0x80)
2415 
2416 /* Bit definitions and macros for MCF_PWM_PWMPOL */
2417 #define MCF_PWM_PWMPOL_PPOL0 (0x01)
2418 #define MCF_PWM_PWMPOL_PPOL1 (0x02)
2419 #define MCF_PWM_PWMPOL_PPOL2 (0x04)
2420 #define MCF_PWM_PWMPOL_PPOL3 (0x08)
2421 #define MCF_PWM_PWMPOL_PPOL4 (0x10)
2422 #define MCF_PWM_PWMPOL_PPOL5 (0x20)
2423 #define MCF_PWM_PWMPOL_PPOL6 (0x40)
2424 #define MCF_PWM_PWMPOL_PPOL7 (0x80)
2425 
2426 /* Bit definitions and macros for MCF_PWM_PWMCLK */
2427 #define MCF_PWM_PWMCLK_PCLK0 (0x01)
2428 #define MCF_PWM_PWMCLK_PCLK1 (0x02)
2429 #define MCF_PWM_PWMCLK_PCLK2 (0x04)
2430 #define MCF_PWM_PWMCLK_PCLK3 (0x08)
2431 #define MCF_PWM_PWMCLK_PCLK4 (0x10)
2432 #define MCF_PWM_PWMCLK_PCLK5 (0x20)
2433 #define MCF_PWM_PWMCLK_PCLK6 (0x40)
2434 #define MCF_PWM_PWMCLK_PCLK7 (0x80)
2435 
2436 /* Bit definitions and macros for MCF_PWM_PWMPRCLK */
2437 #define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x07)<<0)
2438 #define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x07)<<4)
2439 
2440 /* Bit definitions and macros for MCF_PWM_PWMCAE */
2441 #define MCF_PWM_PWMCAE_CAE0 (0x01)
2442 #define MCF_PWM_PWMCAE_CAE1 (0x02)
2443 #define MCF_PWM_PWMCAE_CAE2 (0x04)
2444 #define MCF_PWM_PWMCAE_CAE3 (0x08)
2445 #define MCF_PWM_PWMCAE_CAE4 (0x10)
2446 #define MCF_PWM_PWMCAE_CAE5 (0x20)
2447 #define MCF_PWM_PWMCAE_CAE6 (0x40)
2448 #define MCF_PWM_PWMCAE_CAE7 (0x80)
2449 
2450 /* Bit definitions and macros for MCF_PWM_PWMCTL */
2451 #define MCF_PWM_PWMCTL_PFRZ (0x04)
2452 #define MCF_PWM_PWMCTL_PSWAI (0x08)
2453 #define MCF_PWM_PWMCTL_CON01 (0x10)
2454 #define MCF_PWM_PWMCTL_CON23 (0x20)
2455 #define MCF_PWM_PWMCTL_CON45 (0x40)
2456 #define MCF_PWM_PWMCTL_CON67 (0x80)
2457 
2458 /* Bit definitions and macros for MCF_PWM_PWMSCLA */
2459 #define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0)
2460 
2461 /* Bit definitions and macros for MCF_PWM_PWMSCLB */
2462 #define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0)
2463 
2464 /* Bit definitions and macros for MCF_PWM_PWMCNT */
2465 #define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0)
2466 
2467 /* Bit definitions and macros for MCF_PWM_PWMPER */
2468 #define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0)
2469 
2470 /* Bit definitions and macros for MCF_PWM_PWMDTY */
2471 #define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0)
2472 
2473 /* Bit definitions and macros for MCF_PWM_PWMSDN */
2474 #define MCF_PWM_PWMSDN_SDNEN (0x01)
2475 #define MCF_PWM_PWMSDN_PWM7IL (0x02)
2476 #define MCF_PWM_PWMSDN_PWM7IN (0x04)
2477 #define MCF_PWM_PWMSDN_LVL (0x10)
2478 #define MCF_PWM_PWMSDN_RESTART (0x20)
2479 #define MCF_PWM_PWMSDN_IE (0x40)
2480 #define MCF_PWM_PWMSDN_IF (0x80)
2481 
2482 /*********************************************************************
2483 *
2484 * Edge Port Module (EPORT)
2485 *
2486 *********************************************************************/
2487 
2488 /* Register read/write macros */
2489 #define MCF_EPORT_EPPAR (*(vuint16*)(0xFC094000))
2490 #define MCF_EPORT_EPDDR (*(vuint8 *)(0xFC094002))
2491 #define MCF_EPORT_EPIER (*(vuint8 *)(0xFC094003))
2492 #define MCF_EPORT_EPDR (*(vuint8 *)(0xFC094004))
2493 #define MCF_EPORT_EPPDR (*(vuint8 *)(0xFC094005))
2494 #define MCF_EPORT_EPFR (*(vuint8 *)(0xFC094006))
2495 
2496 /* Bit definitions and macros for MCF_EPORT_EPPAR */
2497 #define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
2498 #define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
2499 #define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
2500 #define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
2501 #define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
2502 #define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
2503 #define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
2504 #define MCF_EPORT_EPPAR_LEVEL (0)
2505 #define MCF_EPORT_EPPAR_RISING (1)
2506 #define MCF_EPORT_EPPAR_FALLING (2)
2507 #define MCF_EPORT_EPPAR_BOTH (3)
2508 #define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000)
2509 #define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
2510 #define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
2511 #define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
2512 #define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000)
2513 #define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
2514 #define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
2515 #define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
2516 #define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000)
2517 #define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400)
2518 #define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800)
2519 #define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00)
2520 #define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000)
2521 #define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100)
2522 #define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200)
2523 #define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300)
2524 #define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000)
2525 #define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040)
2526 #define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080)
2527 #define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0)
2528 #define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000)
2529 #define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010)
2530 #define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020)
2531 #define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030)
2532 #define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000)
2533 #define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004)
2534 #define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008)
2535 #define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C)
2536 
2537 /* Bit definitions and macros for MCF_EPORT_EPDDR */
2538 #define MCF_EPORT_EPDDR_EPDD1 (0x02)
2539 #define MCF_EPORT_EPDDR_EPDD2 (0x04)
2540 #define MCF_EPORT_EPDDR_EPDD3 (0x08)
2541 #define MCF_EPORT_EPDDR_EPDD4 (0x10)
2542 #define MCF_EPORT_EPDDR_EPDD5 (0x20)
2543 #define MCF_EPORT_EPDDR_EPDD6 (0x40)
2544 #define MCF_EPORT_EPDDR_EPDD7 (0x80)
2545 
2546 /* Bit definitions and macros for MCF_EPORT_EPIER */
2547 #define MCF_EPORT_EPIER_EPIE1 (0x02)
2548 #define MCF_EPORT_EPIER_EPIE2 (0x04)
2549 #define MCF_EPORT_EPIER_EPIE3 (0x08)
2550 #define MCF_EPORT_EPIER_EPIE4 (0x10)
2551 #define MCF_EPORT_EPIER_EPIE5 (0x20)
2552 #define MCF_EPORT_EPIER_EPIE6 (0x40)
2553 #define MCF_EPORT_EPIER_EPIE7 (0x80)
2554 
2555 /* Bit definitions and macros for MCF_EPORT_EPDR */
2556 #define MCF_EPORT_EPDR_EPD1 (0x02)
2557 #define MCF_EPORT_EPDR_EPD2 (0x04)
2558 #define MCF_EPORT_EPDR_EPD3 (0x08)
2559 #define MCF_EPORT_EPDR_EPD4 (0x10)
2560 #define MCF_EPORT_EPDR_EPD5 (0x20)
2561 #define MCF_EPORT_EPDR_EPD6 (0x40)
2562 #define MCF_EPORT_EPDR_EPD7 (0x80)
2563 
2564 /* Bit definitions and macros for MCF_EPORT_EPPDR */
2565 #define MCF_EPORT_EPPDR_EPPD1 (0x02)
2566 #define MCF_EPORT_EPPDR_EPPD2 (0x04)
2567 #define MCF_EPORT_EPPDR_EPPD3 (0x08)
2568 #define MCF_EPORT_EPPDR_EPPD4 (0x10)
2569 #define MCF_EPORT_EPPDR_EPPD5 (0x20)
2570 #define MCF_EPORT_EPPDR_EPPD6 (0x40)
2571 #define MCF_EPORT_EPPDR_EPPD7 (0x80)
2572 
2573 /* Bit definitions and macros for MCF_EPORT_EPFR */
2574 #define MCF_EPORT_EPFR_EPF1 (0x02)
2575 #define MCF_EPORT_EPFR_EPF2 (0x04)
2576 #define MCF_EPORT_EPFR_EPF3 (0x08)
2577 #define MCF_EPORT_EPFR_EPF4 (0x10)
2578 #define MCF_EPORT_EPFR_EPF5 (0x20)
2579 #define MCF_EPORT_EPFR_EPF6 (0x40)
2580 #define MCF_EPORT_EPFR_EPF7 (0x80)
2581 
2582 /*********************************************************************
2583 *
2584 * Watchdog Timer Modules (WTM)
2585 *
2586 *********************************************************************/
2587 
2588 /* Register read/write macros */
2589 #define MCF_WTM_WCR (*(vuint16*)(0xFC098000))
2590 #define MCF_WTM_WMR (*(vuint16*)(0xFC098002))
2591 #define MCF_WTM_WCNTR (*(vuint16*)(0xFC098004))
2592 #define MCF_WTM_WSR (*(vuint16*)(0xFC098006))
2593 
2594 /* Bit definitions and macros for MCF_WTM_WCR */
2595 #define MCF_WTM_WCR_EN (0x0001)
2596 #define MCF_WTM_WCR_HALTED (0x0002)
2597 #define MCF_WTM_WCR_DOZE (0x0004)
2598 #define MCF_WTM_WCR_WAIT (0x0008)
2599 
2600 /* Bit definitions and macros for MCF_WTM_WMR */
2601 #define MCF_WTM_WMR_WM(x) (((x)&0xFFFF)<<0)
2602 
2603 /* Bit definitions and macros for MCF_WTM_WCNTR */
2604 #define MCF_WTM_WCNTR_WC(x) (((x)&0xFFFF)<<0)
2605 
2606 /* Bit definitions and macros for MCF_WTM_WSR */
2607 #define MCF_WTM_WSR_WS(x) (((x)&0xFFFF)<<0)
2608 
2609 /*********************************************************************
2610 *
2611 * Chip Configuration Module (CCM)
2612 *
2613 *********************************************************************/
2614 
2615 /* Register read/write macros */
2616 #define MCF_CCM_CCR (*(vuint16*)(0xFC0A0004))
2617 #define MCF_CCM_RCON (*(vuint16*)(0xFC0A0008))
2618 #define MCF_CCM_CIR (*(vuint16*)(0xFC0A000A))
2619 #define MCF_CCM_MISCCR (*(vuint16*)(0xFC0A0010))
2620 #define MCF_CCM_CDR (*(vuint16*)(0xFC0A0012))
2621 #define MCF_CCM_UHCSR (*(vuint16*)(0xFC0A0014))
2622 #define MCF_CCM_UOCSR (*(vuint16*)(0xFC0A0016))
2623 
2624 /* Bit definitions and macros for MCF_CCM_CCR */
2625 #define MCF_CCM_CCR_RESERVED (0x0001)
2626 #define MCF_CCM_CCR_PLL_MODE (0x0003)
2627 #define MCF_CCM_CCR_OSC_MODE (0x0005)
2628 #define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
2629 #define MCF_CCM_CCR_LOAD (0x0021)
2630 #define MCF_CCM_CCR_LIMP (0x0041)
2631 #define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001)
2632 
2633 /* Bit definitions and macros for MCF_CCM_RCON */
2634 #define MCF_CCM_RCON_RESERVED (0x0001)
2635 #define MCF_CCM_RCON_PLL_MODE (0x0003)
2636 #define MCF_CCM_RCON_OSC_MODE (0x0005)
2637 #define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
2638 #define MCF_CCM_RCON_LOAD (0x0021)
2639 #define MCF_CCM_RCON_LIMP (0x0041)
2640 #define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001)
2641 
2642 /* Bit definitions and macros for MCF_CCM_CIR */
2643 #define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0)
2644 #define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
2645 
2646 /* Bit definitions and macros for MCF_CCM_MISCCR */
2647 #define MCF_CCM_MISCCR_USBSRC (0x0001)
2648 #define MCF_CCM_MISCCR_USBDIV (0x0002)
2649 #define MCF_CCM_MISCCR_SSI_SRC (0x0010)
2650 #define MCF_CCM_MISCCR_TIM_DMA (0x0020)
2651 #define MCF_CCM_MISCCR_SSI_PUS (0x0040)
2652 #define MCF_CCM_MISCCR_SSI_PUE (0x0080)
2653 #define MCF_CCM_MISCCR_LCD_CHEN (0x0100)
2654 #define MCF_CCM_MISCCR_LIMP (0x1000)
2655 #define MCF_CCM_MISCCR_PLL_LOCK (0x2000)
2656 
2657 /* Bit definitions and macros for MCF_CCM_CDR */
2658 #define MCF_CCM_CDR_SSIDIV(x) (((x)&0x003F)<<0)
2659 #define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8)
2660 
2661 /* Bit definitions and macros for MCF_CCM_UHCSR */
2662 #define MCF_CCM_UHCSR_XPDE (0x0001)
2663 #define MCF_CCM_UHCSR_UHMIE (0x0002)
2664 #define MCF_CCM_UHCSR_WKUP (0x0004)
2665 #define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14)
2666 
2667 /* Bit definitions and macros for MCF_CCM_UOCSR */
2668 #define MCF_CCM_UOCSR_XPDE (0x0001)
2669 #define MCF_CCM_UOCSR_UOMIE (0x0002)
2670 #define MCF_CCM_UOCSR_WKUP (0x0004)
2671 #define MCF_CCM_UOCSR_PWRFLT (0x0008)
2672 #define MCF_CCM_UOCSR_SEND (0x0010)
2673 #define MCF_CCM_UOCSR_VVLD (0x0020)
2674 #define MCF_CCM_UOCSR_BVLD (0x0040)
2675 #define MCF_CCM_UOCSR_AVLD (0x0080)
2676 #define MCF_CCM_UOCSR_DPPU (0x0100)
2677 #define MCF_CCM_UOCSR_DCR_VBUS (0x0200)
2678 #define MCF_CCM_UOCSR_CRG_VBUS (0x0400)
2679 #define MCF_CCM_UOCSR_DRV_VBUS (0x0800)
2680 #define MCF_CCM_UOCSR_DMPD (0x1000)
2681 #define MCF_CCM_UOCSR_DPPD (0x2000)
2682 #define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14)
2683 
2684 /*********************************************************************
2685 *
2686 * Reset Controller Module (RCM)
2687 *
2688 *********************************************************************/
2689 
2690 /* Register read/write macros */
2691 #define MCF_RCM_RCR (*(vuint8 *)(0xFC0A0000))
2692 #define MCF_RCM_RSR (*(vuint8 *)(0xFC0A0001))
2693 
2694 /* Bit definitions and macros for MCF_RCM_RCR */
2695 #define MCF_RCM_RCR_FRCRSTOUT (0x40)
2696 #define MCF_RCM_RCR_SOFTRST (0x80)
2697 
2698 /* Bit definitions and macros for MCF_RCM_RSR */
2699 #define MCF_RCM_RSR_LOL (0x01)
2700 #define MCF_RCM_RSR_WDR_CORE (0x02)
2701 #define MCF_RCM_RSR_EXT (0x04)
2702 #define MCF_RCM_RSR_POR (0x08)
2703 #define MCF_RCM_RSR_WDR_CHIP (0x10)
2704 #define MCF_RCM_RSR_SOFT (0x20)
2705 
2706 /*********************************************************************
2707 *
2708 * General Purpose I/O (GPIO)
2709 *
2710 *********************************************************************/
2711 
2712 /* Register read/write macros */
2713 #define MCF_GPIO_PODR_FECH (*(vuint8 *)(0xFC0A4000))
2714 #define MCF_GPIO_PODR_FECL (*(vuint8 *)(0xFC0A4001))
2715 #define MCF_GPIO_PODR_SSI (*(vuint8 *)(0xFC0A4002))
2716 #define MCF_GPIO_PODR_BUSCTL (*(vuint8 *)(0xFC0A4003))
2717 #define MCF_GPIO_PODR_BE (*(vuint8 *)(0xFC0A4004))
2718 #define MCF_GPIO_PODR_CS (*(vuint8 *)(0xFC0A4005))
2719 #define MCF_GPIO_PODR_PWM (*(vuint8 *)(0xFC0A4006))
2720 #define MCF_GPIO_PODR_FECI2C (*(vuint8 *)(0xFC0A4007))
2721 #define MCF_GPIO_PODR_UART (*(vuint8 *)(0xFC0A4009))
2722 #define MCF_GPIO_PODR_QSPI (*(vuint8 *)(0xFC0A400A))
2723 #define MCF_GPIO_PODR_TIMER (*(vuint8 *)(0xFC0A400B))
2724 #define MCF_GPIO_PODR_LCDDATAH (*(vuint8 *)(0xFC0A400D))
2725 #define MCF_GPIO_PODR_LCDDATAM (*(vuint8 *)(0xFC0A400E))
2726 #define MCF_GPIO_PODR_LCDDATAL (*(vuint8 *)(0xFC0A400F))
2727 #define MCF_GPIO_PODR_LCDCTLH (*(vuint8 *)(0xFC0A4010))
2728 #define MCF_GPIO_PODR_LCDCTLL (*(vuint8 *)(0xFC0A4011))
2729 #define MCF_GPIO_PDDR_FECH (*(vuint8 *)(0xFC0A4014))
2730 #define MCF_GPIO_PDDR_FECL (*(vuint8 *)(0xFC0A4015))
2731 #define MCF_GPIO_PDDR_SSI (*(vuint8 *)(0xFC0A4016))
2732 #define MCF_GPIO_PDDR_BUSCTL (*(vuint8 *)(0xFC0A4017))
2733 #define MCF_GPIO_PDDR_BE (*(vuint8 *)(0xFC0A4018))
2734 #define MCF_GPIO_PDDR_CS (*(vuint8 *)(0xFC0A4019))
2735 #define MCF_GPIO_PDDR_PWM (*(vuint8 *)(0xFC0A401A))
2736 #define MCF_GPIO_PDDR_FECI2C (*(vuint8 *)(0xFC0A401B))
2737 #define MCF_GPIO_PDDR_UART (*(vuint8 *)(0xFC0A401D))
2738 #define MCF_GPIO_PDDR_QSPI (*(vuint8 *)(0xFC0A401E))
2739 #define MCF_GPIO_PDDR_TIMER (*(vuint8 *)(0xFC0A401F))
2740 #define MCF_GPIO_PDDR_LCDDATAH (*(vuint8 *)(0xFC0A4021))
2741 #define MCF_GPIO_PDDR_LCDDATAM (*(vuint8 *)(0xFC0A4022))
2742 #define MCF_GPIO_PDDR_LCDDATAL (*(vuint8 *)(0xFC0A4023))
2743 #define MCF_GPIO_PDDR_LCDCTLH (*(vuint8 *)(0xFC0A4024))
2744 #define MCF_GPIO_PDDR_LCDCTLL (*(vuint8 *)(0xFC0A4025))
2745 #define MCF_GPIO_PPDSDR_FECH (*(vuint8 *)(0xFC0A4028))
2746 #define MCF_GPIO_PPDSDR_FECL (*(vuint8 *)(0xFC0A4029))
2747 #define MCF_GPIO_PPDSDR_SSI (*(vuint8 *)(0xFC0A402A))
2748 #define MCF_GPIO_PPDSDR_BUSCTL (*(vuint8 *)(0xFC0A402B))
2749 #define MCF_GPIO_PPDSDR_BE (*(vuint8 *)(0xFC0A402C))
2750 #define MCF_GPIO_PPDSDR_CS (*(vuint8 *)(0xFC0A402D))
2751 #define MCF_GPIO_PPDSDR_PWM (*(vuint8 *)(0xFC0A402E))
2752 #define MCF_GPIO_PPDSDR_FECI2C (*(vuint8 *)(0xFC0A402F))
2753 #define MCF_GPIO_PPDSDR_UART (*(vuint8 *)(0xFC0A4031))
2754 #define MCF_GPIO_PPDSDR_QSPI (*(vuint8 *)(0xFC0A4032))
2755 #define MCF_GPIO_PPDSDR_TIMER (*(vuint8 *)(0xFC0A4033))
2756 #define MCF_GPIO_PPDSDR_LCDDATAH (*(vuint8 *)(0xFC0A4035))
2757 #define MCF_GPIO_PPDSDR_LCDDATAM (*(vuint8 *)(0xFC0A4036))
2758 #define MCF_GPIO_PPDSDR_LCDDATAL (*(vuint8 *)(0xFC0A4037))
2759 #define MCF_GPIO_PPDSDR_LCDCTLH (*(vuint8 *)(0xFC0A4038))
2760 #define MCF_GPIO_PPDSDR_LCDCTLL (*(vuint8 *)(0xFC0A4039))
2761 #define MCF_GPIO_PCLRR_FECH (*(vuint8 *)(0xFC0A403C))
2762 #define MCF_GPIO_PCLRR_FECL (*(vuint8 *)(0xFC0A403D))
2763 #define MCF_GPIO_PCLRR_SSI (*(vuint8 *)(0xFC0A403E))
2764 #define MCF_GPIO_PCLRR_BUSCTL (*(vuint8 *)(0xFC0A403F))
2765 #define MCF_GPIO_PCLRR_BE (*(vuint8 *)(0xFC0A4040))
2766 #define MCF_GPIO_PCLRR_CS (*(vuint8 *)(0xFC0A4041))
2767 #define MCF_GPIO_PCLRR_PWM (*(vuint8 *)(0xFC0A4042))
2768 #define MCF_GPIO_PCLRR_FECI2C (*(vuint8 *)(0xFC0A4043))
2769 #define MCF_GPIO_PCLRR_UART (*(vuint8 *)(0xFC0A4045))
2770 #define MCF_GPIO_PCLRR_QSPI (*(vuint8 *)(0xFC0A4046))
2771 #define MCF_GPIO_PCLRR_TIMER (*(vuint8 *)(0xFC0A4047))
2772 #define MCF_GPIO_PCLRR_LCDDATAH (*(vuint8 *)(0xFC0A4049))
2773 #define MCF_GPIO_PCLRR_LCDDATAM (*(vuint8 *)(0xFC0A404A))
2774 #define MCF_GPIO_PCLRR_LCDDATAL (*(vuint8 *)(0xFC0A404B))
2775 #define MCF_GPIO_PCLRR_LCDCTLH (*(vuint8 *)(0xFC0A404C))
2776 #define MCF_GPIO_PCLRR_LCDCTLL (*(vuint8 *)(0xFC0A404D))
2777 #define MCF_GPIO_PAR_FEC (*(vuint8 *)(0xFC0A4050))
2778 #define MCF_GPIO_PAR_PWM (*(vuint8 *)(0xFC0A4051))
2779 #define MCF_GPIO_PAR_BUSCTL (*(vuint8 *)(0xFC0A4052))
2780 #define MCF_GPIO_PAR_FECI2C (*(vuint8 *)(0xFC0A4053))
2781 #define MCF_GPIO_PAR_BE (*(vuint8 *)(0xFC0A4054))
2782 #define MCF_GPIO_PAR_CS (*(vuint8 *)(0xFC0A4055))
2783 #define MCF_GPIO_PAR_SSI (*(vuint16*)(0xFC0A4056))
2784 #define MCF_GPIO_PAR_UART (*(vuint16*)(0xFC0A4058))
2785 #define MCF_GPIO_PAR_QSPI (*(vuint16*)(0xFC0A405A))
2786 #define MCF_GPIO_PAR_TIMER (*(vuint8 *)(0xFC0A405C))
2787 #define MCF_GPIO_PAR_LCDDATA (*(vuint8 *)(0xFC0A405D))
2788 #define MCF_GPIO_PAR_LCDCTL (*(vuint16*)(0xFC0A405E))
2789 #define MCF_GPIO_PAR_IRQ (*(vuint16*)(0xFC0A4060))
2790 #define MCF_GPIO_MSCR_FLEXBUS (*(vuint8 *)(0xFC0A4064))
2791 #define MCF_GPIO_MSCR_SDRAM (*(vuint8 *)(0xFC0A4065))
2792 #define MCF_GPIO_DSCR_I2C (*(vuint8 *)(0xFC0A4068))
2793 #define MCF_GPIO_DSCR_PWM (*(vuint8 *)(0xFC0A4069))
2794 #define MCF_GPIO_DSCR_FEC (*(vuint8 *)(0xFC0A406A))
2795 #define MCF_GPIO_DSCR_UART (*(vuint8 *)(0xFC0A406B))
2796 #define MCF_GPIO_DSCR_QSPI (*(vuint8 *)(0xFC0A406C))
2797 #define MCF_GPIO_DSCR_TIMER (*(vuint8 *)(0xFC0A406D))
2798 #define MCF_GPIO_DSCR_SSI (*(vuint8 *)(0xFC0A406E))
2799 #define MCF_GPIO_DSCR_LCD (*(vuint8 *)(0xFC0A406F))
2800 #define MCF_GPIO_DSCR_DEBUG (*(vuint8 *)(0xFC0A4070))
2801 #define MCF_GPIO_DSCR_CLKRST (*(vuint8 *)(0xFC0A4071))
2802 #define MCF_GPIO_DSCR_IRQ (*(vuint8 *)(0xFC0A4072))
2803 
2804 /* Bit definitions and macros for MCF_GPIO_PODR_FECH */
2805 #define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01)
2806 #define MCF_GPIO_PODR_FECH_PODR_FECH1 (0x02)
2807 #define MCF_GPIO_PODR_FECH_PODR_FECH2 (0x04)
2808 #define MCF_GPIO_PODR_FECH_PODR_FECH3 (0x08)
2809 #define MCF_GPIO_PODR_FECH_PODR_FECH4 (0x10)
2810 #define MCF_GPIO_PODR_FECH_PODR_FECH5 (0x20)
2811 #define MCF_GPIO_PODR_FECH_PODR_FECH6 (0x40)
2812 #define MCF_GPIO_PODR_FECH_PODR_FECH7 (0x80)
2813 
2814 /* Bit definitions and macros for MCF_GPIO_PODR_FECL */
2815 #define MCF_GPIO_PODR_FECL_PODR_FECL0 (0x01)
2816 #define MCF_GPIO_PODR_FECL_PODR_FECL1 (0x02)
2817 #define MCF_GPIO_PODR_FECL_PODR_FECL2 (0x04)
2818 #define MCF_GPIO_PODR_FECL_PODR_FECL3 (0x08)
2819 #define MCF_GPIO_PODR_FECL_PODR_FECL4 (0x10)
2820 #define MCF_GPIO_PODR_FECL_PODR_FECL5 (0x20)
2821 #define MCF_GPIO_PODR_FECL_PODR_FECL6 (0x40)
2822 #define MCF_GPIO_PODR_FECL_PODR_FECL7 (0x80)
2823 
2824 /* Bit definitions and macros for MCF_GPIO_PODR_SSI */
2825 #define MCF_GPIO_PODR_SSI_PODR_SSI0 (0x01)
2826 #define MCF_GPIO_PODR_SSI_PODR_SSI1 (0x02)
2827 #define MCF_GPIO_PODR_SSI_PODR_SSI2 (0x04)
2828 #define MCF_GPIO_PODR_SSI_PODR_SSI3 (0x08)
2829 #define MCF_GPIO_PODR_SSI_PODR_SSI4 (0x10)
2830 
2831 /* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */
2832 #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL0 (0x01)
2833 #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02)
2834 #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04)
2835 #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08)
2836 
2837 /* Bit definitions and macros for MCF_GPIO_PODR_BE */
2838 #define MCF_GPIO_PODR_BE_PODR_BE0 (0x01)
2839 #define MCF_GPIO_PODR_BE_PODR_BE1 (0x02)
2840 #define MCF_GPIO_PODR_BE_PODR_BE2 (0x04)
2841 #define MCF_GPIO_PODR_BE_PODR_BE3 (0x08)
2842 
2843 /* Bit definitions and macros for MCF_GPIO_PODR_CS */
2844 #define MCF_GPIO_PODR_CS_PODR_CS1 (0x02)
2845 #define MCF_GPIO_PODR_CS_PODR_CS2 (0x04)
2846 #define MCF_GPIO_PODR_CS_PODR_CS3 (0x08)
2847 #define MCF_GPIO_PODR_CS_PODR_CS4 (0x10)
2848 #define MCF_GPIO_PODR_CS_PODR_CS5 (0x20)
2849 
2850 /* Bit definitions and macros for MCF_GPIO_PODR_PWM */
2851 #define MCF_GPIO_PODR_PWM_PODR_PWM2 (0x04)
2852 #define MCF_GPIO_PODR_PWM_PODR_PWM3 (0x08)
2853 #define MCF_GPIO_PODR_PWM_PODR_PWM4 (0x10)
2854 #define MCF_GPIO_PODR_PWM_PODR_PWM5 (0x20)
2855 
2856 /* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
2857 #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01)
2858 #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02)
2859 #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04)
2860 #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08)
2861 
2862 /* Bit definitions and macros for MCF_GPIO_PODR_UART */
2863 #define MCF_GPIO_PODR_UART_PODR_UART0 (0x01)
2864 #define MCF_GPIO_PODR_UART_PODR_UART1 (0x02)
2865 #define MCF_GPIO_PODR_UART_PODR_UART2 (0x04)
2866 #define MCF_GPIO_PODR_UART_PODR_UART3 (0x08)
2867 #define MCF_GPIO_PODR_UART_PODR_UART4 (0x10)
2868 #define MCF_GPIO_PODR_UART_PODR_UART5 (0x20)
2869 #define MCF_GPIO_PODR_UART_PODR_UART6 (0x40)
2870 #define MCF_GPIO_PODR_UART_PODR_UART7 (0x80)
2871 
2872 /* Bit definitions and macros for MCF_GPIO_PODR_QSPI */
2873 #define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01)
2874 #define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02)
2875 #define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04)
2876 #define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08)
2877 #define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10)
2878 #define MCF_GPIO_PODR_QSPI_PODR_QSPI5 (0x20)
2879 
2880 /* Bit definitions and macros for MCF_GPIO_PODR_TIMER */
2881 #define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01)
2882 #define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02)
2883 #define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04)
2884 #define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08)
2885 
2886 /* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */
2887 #define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0 (0x01)
2888 #define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1 (0x02)
2889 
2890 /* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */
2891 #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0 (0x01)
2892 #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1 (0x02)
2893 #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2 (0x04)
2894 #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3 (0x08)
2895 #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4 (0x10)
2896 #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5 (0x20)
2897 #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6 (0x40)
2898 #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7 (0x80)
2899 
2900 /* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */
2901 #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0 (0x01)
2902 #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1 (0x02)
2903 #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2 (0x04)
2904 #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3 (0x08)
2905 #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4 (0x10)
2906 #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5 (0x20)
2907 #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6 (0x40)
2908 #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7 (0x80)
2909 
2910 /* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */
2911 #define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0 (0x01)
2912 
2913 /* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */
2914 #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0 (0x01)
2915 #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1 (0x02)
2916 #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2 (0x04)
2917 #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3 (0x08)
2918 #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4 (0x10)
2919 #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5 (0x20)
2920 #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6 (0x40)
2921 #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7 (0x80)
2922 
2923 /* Bit definitions and macros for MCF_GPIO_PDDR_FECH */
2924 #define MCF_GPIO_PDDR_FECH_PDDR_FECH0 (0x01)
2925 #define MCF_GPIO_PDDR_FECH_PDDR_FECH1 (0x02)
2926 #define MCF_GPIO_PDDR_FECH_PDDR_FECH2 (0x04)
2927 #define MCF_GPIO_PDDR_FECH_PDDR_FECH3 (0x08)
2928 #define MCF_GPIO_PDDR_FECH_PDDR_FECH4 (0x10)
2929 #define MCF_GPIO_PDDR_FECH_PDDR_FECH5 (0x20)
2930 #define MCF_GPIO_PDDR_FECH_PDDR_FECH6 (0x40)
2931 #define MCF_GPIO_PDDR_FECH_PDDR_FECH7 (0x80)
2932 
2933 /* Bit definitions and macros for MCF_GPIO_PDDR_FECL */
2934 #define MCF_GPIO_PDDR_FECL_PDDR_FECL0 (0x01)
2935 #define MCF_GPIO_PDDR_FECL_PDDR_FECL1 (0x02)
2936 #define MCF_GPIO_PDDR_FECL_PDDR_FECL2 (0x04)
2937 #define MCF_GPIO_PDDR_FECL_PDDR_FECL3 (0x08)
2938 #define MCF_GPIO_PDDR_FECL_PDDR_FECL4 (0x10)
2939 #define MCF_GPIO_PDDR_FECL_PDDR_FECL5 (0x20)
2940 #define MCF_GPIO_PDDR_FECL_PDDR_FECL6 (0x40)
2941 #define MCF_GPIO_PDDR_FECL_PDDR_FECL7 (0x80)
2942 
2943 /* Bit definitions and macros for MCF_GPIO_PDDR_SSI */
2944 #define MCF_GPIO_PDDR_SSI_PDDR_SSI0 (0x01)
2945 #define MCF_GPIO_PDDR_SSI_PDDR_SSI1 (0x02)
2946 #define MCF_GPIO_PDDR_SSI_PDDR_SSI2 (0x04)
2947 #define MCF_GPIO_PDDR_SSI_PDDR_SSI3 (0x08)
2948 #define MCF_GPIO_PDDR_SSI_PDDR_SSI4 (0x10)
2949 
2950 /* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */
2951 #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL0 (0x01)
2952 #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02)
2953 #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04)
2954 #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08)
2955 
2956 /* Bit definitions and macros for MCF_GPIO_PDDR_BE */
2957 #define MCF_GPIO_PDDR_BE_PDDR_BE0 (0x01)
2958 #define MCF_GPIO_PDDR_BE_PDDR_BE1 (0x02)
2959 #define MCF_GPIO_PDDR_BE_PDDR_BE2 (0x04)
2960 #define MCF_GPIO_PDDR_BE_PDDR_BE3 (0x08)
2961 
2962 /* Bit definitions and macros for MCF_GPIO_PDDR_CS */
2963 #define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02)
2964 #define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04)
2965 #define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08)
2966 #define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10)
2967 #define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20)
2968 
2969 /* Bit definitions and macros for MCF_GPIO_PDDR_PWM */
2970 #define MCF_GPIO_PDDR_PWM_PDDR_PWM2 (0x04)
2971 #define MCF_GPIO_PDDR_PWM_PDDR_PWM3 (0x08)
2972 #define MCF_GPIO_PDDR_PWM_PDDR_PWM4 (0x10)
2973 #define MCF_GPIO_PDDR_PWM_PDDR_PWM5 (0x20)
2974 
2975 /* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
2976 #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01)
2977 #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02)
2978 #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04)
2979 #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08)
2980 
2981 /* Bit definitions and macros for MCF_GPIO_PDDR_UART */
2982 #define MCF_GPIO_PDDR_UART_PDDR_UART0 (0x01)
2983 #define MCF_GPIO_PDDR_UART_PDDR_UART1 (0x02)
2984 #define MCF_GPIO_PDDR_UART_PDDR_UART2 (0x04)
2985 #define MCF_GPIO_PDDR_UART_PDDR_UART3 (0x08)
2986 #define MCF_GPIO_PDDR_UART_PDDR_UART4 (0x10)
2987 #define MCF_GPIO_PDDR_UART_PDDR_UART5 (0x20)
2988 #define MCF_GPIO_PDDR_UART_PDDR_UART6 (0x40)
2989 #define MCF_GPIO_PDDR_UART_PDDR_UART7 (0x80)
2990 
2991 /* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */
2992 #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01)
2993 #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02)
2994 #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04)
2995 #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08)
2996 #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10)
2997 #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5 (0x20)
2998 
2999 /* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */
3000 #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01)
3001 #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02)
3002 #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04)
3003 #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08)
3004 
3005 /* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */
3006 #define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0 (0x01)
3007 #define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1 (0x02)
3008 
3009 /* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */
3010 #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0 (0x01)
3011 #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1 (0x02)
3012 #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2 (0x04)
3013 #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3 (0x08)
3014 #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4 (0x10)
3015 #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5 (0x20)
3016 #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6 (0x40)
3017 #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7 (0x80)
3018 
3019 /* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */
3020 #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0 (0x01)
3021 #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1 (0x02)
3022 #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2 (0x04)
3023 #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3 (0x08)
3024 #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4 (0x10)
3025 #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5 (0x20)
3026 #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6 (0x40)
3027 #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7 (0x80)
3028 
3029 /* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */
3030 #define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0 (0x01)
3031 
3032 /* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */
3033 #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0 (0x01)
3034 #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1 (0x02)
3035 #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2 (0x04)
3036 #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3 (0x08)
3037 #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4 (0x10)
3038 #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5 (0x20)
3039 #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6 (0x40)
3040 #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7 (0x80)
3041 
3042 /* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */
3043 #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0 (0x01)
3044 #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1 (0x02)
3045 #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2 (0x04)
3046 #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3 (0x08)
3047 #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4 (0x10)
3048 #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5 (0x20)
3049 #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6 (0x40)
3050 #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7 (0x80)
3051 
3052 /* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */
3053 #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0 (0x01)
3054 #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1 (0x02)
3055 #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2 (0x04)
3056 #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3 (0x08)
3057 #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4 (0x10)
3058 #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5 (0x20)
3059 #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6 (0x40)
3060 #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7 (0x80)
3061 
3062 /* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */
3063 #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0 (0x01)
3064 #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1 (0x02)
3065 #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2 (0x04)
3066 #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3 (0x08)
3067 #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4 (0x10)
3068 
3069 /* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */
3070 #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL0 (0x01)
3071 #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02)
3072 #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04)
3073 #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08)
3074 
3075 /* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */
3076 #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0 (0x01)
3077 #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1 (0x02)
3078 #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2 (0x04)
3079 #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3 (0x08)
3080 
3081 /* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */
3082 #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02)
3083 #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04)
3084 #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08)
3085 #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10)
3086 #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20)
3087 
3088 /* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */
3089 #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2 (0x04)
3090 #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3 (0x08)
3091 #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4 (0x10)
3092 #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5 (0x20)
3093 
3094 /* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
3095 #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01)
3096 #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02)
3097 #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04)
3098 #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08)
3099 
3100 /* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */
3101 #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0 (0x01)
3102 #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1 (0x02)
3103 #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2 (0x04)
3104 #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3 (0x08)
3105 #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4 (0x10)
3106 #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5 (0x20)
3107 #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6 (0x40)
3108 #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7 (0x80)
3109 
3110 /* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */
3111 #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01)
3112 #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02)
3113 #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04)
3114 #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08)
3115 #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10)
3116 #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5 (0x20)
3117 
3118 /* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */
3119 #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01)
3120 #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02)
3121 #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04)
3122 #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08)
3123 
3124 /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */
3125 #define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0 (0x01)
3126 #define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1 (0x02)
3127 
3128 /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */
3129 #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0 (0x01)
3130 #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1 (0x02)
3131 #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2 (0x04)
3132 #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3 (0x08)
3133 #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4 (0x10)
3134 #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5 (0x20)
3135 #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6 (0x40)
3136 #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7 (0x80)
3137 
3138 /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */
3139 #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0 (0x01)
3140 #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1 (0x02)
3141 #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2 (0x04)
3142 #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3 (0x08)
3143 #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4 (0x10)
3144 #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5 (0x20)
3145 #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6 (0x40)
3146 #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7 (0x80)
3147 
3148 /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */
3149 #define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0 (0x01)
3150 
3151 /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */
3152 #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0 (0x01)
3153 #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1 (0x02)
3154 #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2 (0x04)
3155 #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3 (0x08)
3156 #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4 (0x10)
3157 #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5 (0x20)
3158 #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6 (0x40)
3159 #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7 (0x80)
3160 
3161 /* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */
3162 #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0 (0x01)
3163 #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1 (0x02)
3164 #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2 (0x04)
3165 #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3 (0x08)
3166 #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4 (0x10)
3167 #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5 (0x20)
3168 #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6 (0x40)
3169 #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7 (0x80)
3170 
3171 /* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */
3172 #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0 (0x01)
3173 #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1 (0x02)
3174 #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2 (0x04)
3175 #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3 (0x08)
3176 #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4 (0x10)
3177 #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5 (0x20)
3178 #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6 (0x40)
3179 #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7 (0x80)
3180 
3181 /* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */
3182 #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0 (0x01)
3183 #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1 (0x02)
3184 #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2 (0x04)
3185 #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3 (0x08)
3186 #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4 (0x10)
3187 
3188 /* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */
3189 #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL0 (0x01)
3190 #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02)
3191 #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04)
3192 #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08)
3193 
3194 /* Bit definitions and macros for MCF_GPIO_PCLRR_BE */
3195 #define MCF_GPIO_PCLRR_BE_PCLRR_BE0 (0x01)
3196 #define MCF_GPIO_PCLRR_BE_PCLRR_BE1 (0x02)
3197 #define MCF_GPIO_PCLRR_BE_PCLRR_BE2 (0x04)
3198 #define MCF_GPIO_PCLRR_BE_PCLRR_BE3 (0x08)
3199 
3200 /* Bit definitions and macros for MCF_GPIO_PCLRR_CS */
3201 #define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02)
3202 #define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04)
3203 #define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08)
3204 #define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10)
3205 #define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20)
3206 
3207 /* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */
3208 #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2 (0x04)
3209 #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3 (0x08)
3210 #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4 (0x10)
3211 #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5 (0x20)
3212 
3213 /* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
3214 #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01)
3215 #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02)
3216 #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04)
3217 #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08)
3218 
3219 /* Bit definitions and macros for MCF_GPIO_PCLRR_UART */
3220 #define MCF_GPIO_PCLRR_UART_PCLRR_UART0 (0x01)
3221 #define MCF_GPIO_PCLRR_UART_PCLRR_UART1 (0x02)
3222 #define MCF_GPIO_PCLRR_UART_PCLRR_UART2 (0x04)
3223 #define MCF_GPIO_PCLRR_UART_PCLRR_UART3 (0x08)
3224 #define MCF_GPIO_PCLRR_UART_PCLRR_UART4 (0x10)
3225 #define MCF_GPIO_PCLRR_UART_PCLRR_UART5 (0x20)
3226 #define MCF_GPIO_PCLRR_UART_PCLRR_UART6 (0x40)
3227 #define MCF_GPIO_PCLRR_UART_PCLRR_UART7 (0x80)
3228 
3229 /* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */
3230 #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01)
3231 #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02)
3232 #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04)
3233 #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08)
3234 #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10)
3235 #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5 (0x20)
3236 
3237 /* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */
3238 #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01)
3239 #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02)
3240 #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04)
3241 #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08)
3242 
3243 /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */
3244 #define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0 (0x01)
3245 #define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1 (0x02)
3246 
3247 /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */
3248 #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0 (0x01)
3249 #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1 (0x02)
3250 #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2 (0x04)
3251 #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3 (0x08)
3252 #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4 (0x10)
3253 #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5 (0x20)
3254 #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6 (0x40)
3255 #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7 (0x80)
3256 
3257 /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */
3258 #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0 (0x01)
3259 #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1 (0x02)
3260 #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2 (0x04)
3261 #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3 (0x08)
3262 #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4 (0x10)
3263 #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5 (0x20)
3264 #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6 (0x40)
3265 #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7 (0x80)
3266 
3267 /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */
3268 #define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01)
3269 
3270 /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */
3271 #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0 (0x01)
3272 #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1 (0x02)
3273 #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2 (0x04)
3274 #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3 (0x08)
3275 #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4 (0x10)
3276 #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5 (0x20)
3277 #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6 (0x40)
3278 #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7 (0x80)
3279 
3280 /* Bit definitions and macros for MCF_GPIO_PAR_FEC */
3281 #define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x) (((x)&0x03)<<0)
3282 #define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x) (((x)&0x03)<<2)
3283 #define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO (0x00)
3284 #define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1 (0x04)
3285 #define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC (0x0C)
3286 #define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO (0x00)
3287 #define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART (0x01)
3288 #define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC (0x03)
3289 
3290 /* Bit definitions and macros for MCF_GPIO_PAR_PWM */
3291 #define MCF_GPIO_PAR_PWM_PAR_PWM1(x) (((x)&0x03)<<0)
3292 #define MCF_GPIO_PAR_PWM_PAR_PWM3(x) (((x)&0x03)<<2)
3293 #define MCF_GPIO_PAR_PWM_PAR_PWM5 (0x10)
3294 #define MCF_GPIO_PAR_PWM_PAR_PWM7 (0x20)
3295 
3296 /* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */
3297 #define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x03)<<3)
3298 #define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x20)
3299 #define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x40)
3300 #define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x80)
3301 #define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO (0x00)
3302 #define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE (0x80)
3303 #define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO (0x00)
3304 #define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA (0x40)
3305 #define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO (0x00)
3306 #define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB (0x20)
3307 #define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x00)
3308 #define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0 (0x10)
3309 #define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x18)
3310 
3311 /* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */
3312 #define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0)
3313 #define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2)
3314 #define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x) (((x)&0x03)<<4)
3315 #define MCF_GPIO_PAR_FECI2C_PAR_MDC(x) (((x)&0x03)<<6)
3316 #define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO (0x00)
3317 #define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2 (0x40)
3318 #define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL (0x80)
3319 #define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC (0xC0)
3320 #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO (0x00)
3321 #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2 (0x10)
3322 #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA (0x20)
3323 #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO (0x30)
3324 #define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00)
3325 #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
3326 #define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL (0x0C)
3327 #define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00)
3328 #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x01)
3329 #define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA (0x03)
3330 
3331 /* Bit definitions and macros for MCF_GPIO_PAR_BE */
3332 #define MCF_GPIO_PAR_BE_PAR_BE0 (0x01)
3333 #define MCF_GPIO_PAR_BE_PAR_BE1 (0x02)
3334 #define MCF_GPIO_PAR_BE_PAR_BE2 (0x04)
3335 #define MCF_GPIO_PAR_BE_PAR_BE3 (0x08)
3336 
3337 /* Bit definitions and macros for MCF_GPIO_PAR_CS */
3338 #define MCF_GPIO_PAR_CS_PAR_CS1 (0x02)
3339 #define MCF_GPIO_PAR_CS_PAR_CS2 (0x04)
3340 #define MCF_GPIO_PAR_CS_PAR_CS3 (0x08)
3341 #define MCF_GPIO_PAR_CS_PAR_CS4 (0x10)
3342 #define MCF_GPIO_PAR_CS_PAR_CS5 (0x20)
3343 #define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO (0x00)
3344 #define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1 (0x01)
3345 #define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1 (0x03)
3346 
3347 /* Bit definitions and macros for MCF_GPIO_PAR_SSI */
3348 #define MCF_GPIO_PAR_SSI_PAR_MCLK (0x0080)
3349 #define MCF_GPIO_PAR_SSI_PAR_TXD(x) (((x)&0x0003)<<8)
3350 #define MCF_GPIO_PAR_SSI_PAR_RXD(x) (((x)&0x0003)<<10)
3351 #define MCF_GPIO_PAR_SSI_PAR_FS(x) (((x)&0x0003)<<12)
3352 #define MCF_GPIO_PAR_SSI_PAR_BCLK(x) (((x)&0x0003)<<14)
3353 
3354 /* Bit definitions and macros for MCF_GPIO_PAR_UART */
3355 #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0001)
3356 #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0002)
3357 #define MCF_GPIO_PAR_UART_PAR_URTS0 (0x0004)
3358 #define MCF_GPIO_PAR_UART_PAR_UCTS0 (0x0008)
3359 #define MCF_GPIO_PAR_UART_PAR_UTXD1(x) (((x)&0x0003)<<4)
3360 #define MCF_GPIO_PAR_UART_PAR_URXD1(x) (((x)&0x0003)<<6)
3361 #define MCF_GPIO_PAR_UART_PAR_URTS1(x) (((x)&0x0003)<<8)
3362 #define MCF_GPIO_PAR_UART_PAR_UCTS1(x) (((x)&0x0003)<<10)
3363 #define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO (0x0000)
3364 #define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK (0x0800)
3365 #define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7 (0x0400)
3366 #define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1 (0x0C00)
3367 #define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO (0x0000)
3368 #define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS (0x0200)
3369 #define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6 (0x0100)
3370 #define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1 (0x0300)
3371 #define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO (0x0000)
3372 #define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD (0x0080)
3373 #define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5 (0x0040)
3374 #define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1 (0x00C0)
3375 #define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO (0x0000)
3376 #define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD (0x0020)
3377 #define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4 (0x0010)
3378 #define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1 (0x0030)
3379 
3380 /* Bit definitions and macros for MCF_GPIO_PAR_QSPI */
3381 #define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x0003)<<4)
3382 #define MCF_GPIO_PAR_QSPI_PAR_DOUT(x) (((x)&0x0003)<<6)
3383 #define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x0003)<<8)
3384 #define MCF_GPIO_PAR_QSPI_PAR_PCS0(x) (((x)&0x0003)<<10)
3385 #define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x0003)<<12)
3386 #define MCF_GPIO_PAR_QSPI_PAR_PCS2(x) (((x)&0x0003)<<14)
3387 
3388 /* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
3389 #define MCF_GPIO_PAR_TIMER_PAR_TIN0(x) (((x)&0x03)<<0)
3390 #define MCF_GPIO_PAR_TIMER_PAR_TIN1(x) (((x)&0x03)<<2)
3391 #define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<4)
3392 #define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<6)
3393 #define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO (0x00)
3394 #define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3 (0x80)
3395 #define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2 (0x40)
3396 #define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3 (0xC0)
3397 #define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO (0x00)
3398 #define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2 (0x20)
3399 #define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2 (0x10)
3400 #define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2 (0x30)
3401 #define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO (0x00)
3402 #define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1 (0x08)
3403 #define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1 (0x04)
3404 #define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1 (0x0C)
3405 #define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO (0x00)
3406 #define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0 (0x02)
3407 #define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0 (0x01)
3408 #define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0 (0x03)
3409 
3410 /* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */
3411 #define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x) (((x)&0x03)<<0)
3412 #define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x) (((x)&0x03)<<2)
3413 #define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x) (((x)&0x03)<<4)
3414 #define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x) (((x)&0x03)<<6)
3415 
3416 /* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */
3417 #define MCF_GPIO_PAR_LCDCTL_PAR_CLS (0x0001)
3418 #define MCF_GPIO_PAR_LCDCTL_PAR_PS (0x0002)
3419 #define MCF_GPIO_PAR_LCDCTL_PAR_REV (0x0004)
3420 #define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR (0x0008)
3421 #define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST (0x0010)
3422 #define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK (0x0020)
3423 #define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC (0x0040)
3424 #define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC (0x0080)
3425 #define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE (0x0100)
3426 
3427 /* Bit definitions and macros for MCF_GPIO_PAR_IRQ */
3428 #define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x) (((x)&0x0003)<<4)
3429 #define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x) (((x)&0x0003)<<6)
3430 #define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x) (((x)&0x0003)<<8)
3431 #define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x) (((x)&0x0003)<<10)
3432 #define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x) (((x)&0x0003)<<12)
3433 
3434 /* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */
3435 #define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x) (((x)&0x03)<<0)
3436 #define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x) (((x)&0x03)<<2)
3437 #define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x) (((x)&0x03)<<4)
3438 
3439 /* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */
3440 #define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x) (((x)&0x03)<<0)
3441 #define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x) (((x)&0x03)<<2)
3442 #define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x) (((x)&0x03)<<4)
3443 
3444 /* Bit definitions and macros for MCF_GPIO_DSCR_I2C */
3445 #define MCF_GPIO_DSCR_I2C_I2C_DSE(x) (((x)&0x03)<<0)
3446 
3447 /* Bit definitions and macros for MCF_GPIO_DSCR_PWM */
3448 #define MCF_GPIO_DSCR_PWM_PWM_DSE(x) (((x)&0x03)<<0)
3449 
3450 /* Bit definitions and macros for MCF_GPIO_DSCR_FEC */
3451 #define MCF_GPIO_DSCR_FEC_FEC_DSE(x) (((x)&0x03)<<0)
3452 
3453 /* Bit definitions and macros for MCF_GPIO_DSCR_UART */
3454 #define MCF_GPIO_DSCR_UART_UART0_DSE(x) (((x)&0x03)<<0)
3455 #define MCF_GPIO_DSCR_UART_UART1_DSE(x) (((x)&0x03)<<2)
3456 
3457 /* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */
3458 #define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x) (((x)&0x03)<<0)
3459 
3460 /* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */
3461 #define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x) (((x)&0x03)<<0)
3462 
3463 /* Bit definitions and macros for MCF_GPIO_DSCR_SSI */
3464 #define MCF_GPIO_DSCR_SSI_SSI_DSE(x) (((x)&0x03)<<0)
3465 
3466 /* Bit definitions and macros for MCF_GPIO_DSCR_LCD */
3467 #define MCF_GPIO_DSCR_LCD_LCD_DSE(x) (((x)&0x03)<<0)
3468 
3469 /* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */
3470 #define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x) (((x)&0x03)<<0)
3471 
3472 /* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */
3473 #define MCF_GPIO_DSCR_CLKRST_MSCR_FBCLK(x) (((x)&0x03)<<0)
3474 #define MCF_GPIO_DSCR_CLKRST_RSTOUT_DSE(x) (((x)&0x03)<<2)
3475 
3476 /* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */
3477 #define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0)
3478 
3479 /*********************************************************************
3480 *
3481 * Real-time Clock (RTC)
3482 *
3483 *********************************************************************/
3484 
3485 /* Register read/write macros */
3486 #define MCF_RTC_HOURMIN (*(vuint32*)(0xFC0A8000))
3487 #define MCF_RTC_SECONDS (*(vuint32*)(0xFC0A8004))
3488 #define MCF_RTC_ALRM_HM (*(vuint32*)(0xFC0A8008))
3489 #define MCF_RTC_ALRM_SEC (*(vuint32*)(0xFC0A800C))
3490 #define MCF_RTC_CR (*(vuint32*)(0xFC0A8010))
3491 #define MCF_RTC_ISR (*(vuint32*)(0xFC0A8014))
3492 #define MCF_RTC_IER (*(vuint32*)(0xFC0A8018))
3493 #define MCF_RTC_STPWCH (*(vuint32*)(0xFC0A801C))
3494 #define MCF_RTC_DAYS (*(vuint32*)(0xFC0A8020))
3495 #define MCF_RTC_ALRM_DAY (*(vuint32*)(0xFC0A8024))
3496 
3497 /* Bit definitions and macros for MCF_RTC_HOURMIN */
3498 #define MCF_RTC_HOURMIN_MINUTES(x) (((x)&0x0000003F)<<0)
3499 #define MCF_RTC_HOURMIN_HOURS(x) (((x)&0x0000001F)<<8)
3500 
3501 /* Bit definitions and macros for MCF_RTC_SECONDS */
3502 #define MCF_RTC_SECONDS_SECONDS(x) (((x)&0x0000003F)<<0)
3503 
3504 /* Bit definitions and macros for MCF_RTC_ALRM_HM */
3505 #define MCF_RTC_ALRM_HM_MINUTES(x) (((x)&0x0000003F)<<0)
3506 #define MCF_RTC_ALRM_HM_HOURS(x) (((x)&0x0000001F)<<8)
3507 
3508 /* Bit definitions and macros for MCF_RTC_ALRM_SEC */
3509 #define MCF_RTC_ALRM_SEC_SECONDS(x) (((x)&0x0000003F)<<0)
3510 
3511 /* Bit definitions and macros for MCF_RTC_CR */
3512 #define MCF_RTC_CR_SWR (0x00000001)
3513 #define MCF_RTC_CR_XTL(x) (((x)&0x00000003)<<5)
3514 #define MCF_RTC_CR_EN (0x00000080)
3515 #define MCF_RTC_CR_32768 (0x0)
3516 #define MCF_RTC_CR_32000 (0x1)
3517 #define MCF_RTC_CR_38400 (0x2)
3518 
3519 /* Bit definitions and macros for MCF_RTC_ISR */
3520 #define MCF_RTC_ISR_SW (0x00000001)
3521 #define MCF_RTC_ISR_MIN (0x00000002)
3522 #define MCF_RTC_ISR_ALM (0x00000004)
3523 #define MCF_RTC_ISR_DAY (0x00000008)
3524 #define MCF_RTC_ISR_1HZ (0x00000010)
3525 #define MCF_RTC_ISR_HR (0x00000020)
3526 #define MCF_RTC_ISR_2HZ (0x00000080)
3527 #define MCF_RTC_ISR_SAM0 (0x00000100)
3528 #define MCF_RTC_ISR_SAM1 (0x00000200)
3529 #define MCF_RTC_ISR_SAM2 (0x00000400)
3530 #define MCF_RTC_ISR_SAM3 (0x00000800)
3531 #define MCF_RTC_ISR_SAM4 (0x00001000)
3532 #define MCF_RTC_ISR_SAM5 (0x00002000)
3533 #define MCF_RTC_ISR_SAM6 (0x00004000)
3534 #define MCF_RTC_ISR_SAM7 (0x00008000)
3535 
3536 /* Bit definitions and macros for MCF_RTC_IER */
3537 #define MCF_RTC_IER_SW (0x00000001)
3538 #define MCF_RTC_IER_MIN (0x00000002)
3539 #define MCF_RTC_IER_ALM (0x00000004)
3540 #define MCF_RTC_IER_DAY (0x00000008)
3541 #define MCF_RTC_IER_1HZ (0x00000010)
3542 #define MCF_RTC_IER_HR (0x00000020)
3543 #define MCF_RTC_IER_2HZ (0x00000080)
3544 #define MCF_RTC_IER_SAM0 (0x00000100)
3545 #define MCF_RTC_IER_SAM1 (0x00000200)
3546 #define MCF_RTC_IER_SAM2 (0x00000400)
3547 #define MCF_RTC_IER_SAM3 (0x00000800)
3548 #define MCF_RTC_IER_SAM4 (0x00001000)
3549 #define MCF_RTC_IER_SAM5 (0x00002000)
3550 #define MCF_RTC_IER_SAM6 (0x00004000)
3551 #define MCF_RTC_IER_SAM7 (0x00008000)
3552 
3553 /* Bit definitions and macros for MCF_RTC_STPWCH */
3554 #define MCF_RTC_STPWCH_CNT(x) (((x)&0x0000003F)<<0)
3555 
3556 /* Bit definitions and macros for MCF_RTC_DAYS */
3557 #define MCF_RTC_DAYS_DAYS(x) (((x)&0x0000FFFF)<<0)
3558 
3559 /* Bit definitions and macros for MCF_RTC_ALRM_DAY */
3560 #define MCF_RTC_ALRM_DAY_DAYS(x) (((x)&0x0000FFFF)<<0)
3561 
3562 /*********************************************************************
3563 *
3564 * LCD Controller (LCDC)
3565 *
3566 *********************************************************************/
3567 
3568 /* Register read/write macros */
3569 #define MCF_LCDC_LSSAR (*(vuint32*)(0xFC0AC000))
3570 #define MCF_LCDC_LSR (*(vuint32*)(0xFC0AC004))
3571 #define MCF_LCDC_LVPWR (*(vuint32*)(0xFC0AC008))
3572 #define MCF_LCDC_LCPR (*(vuint32*)(0xFC0AC00C))
3573 #define MCF_LCDC_LCWHBR (*(vuint32*)(0xFC0AC010))
3574 #define MCF_LCDC_LCCMR (*(vuint32*)(0xFC0AC014))
3575 #define MCF_LCDC_LPCR (*(vuint32*)(0xFC0AC018))
3576 #define MCF_LCDC_LHCR (*(vuint32*)(0xFC0AC01C))
3577 #define MCF_LCDC_LVCR (*(vuint32*)(0xFC0AC020))
3578 #define MCF_LCDC_LPOR (*(vuint32*)(0xFC0AC024))
3579 #define MCF_LCDC_LSCR (*(vuint32*)(0xFC0AC028))
3580 #define MCF_LCDC_LPCCR (*(vuint32*)(0xFC0AC02C))
3581 #define MCF_LCDC_LDCR (*(vuint32*)(0xFC0AC030))
3582 #define MCF_LCDC_LRMCR (*(vuint32*)(0xFC0AC034))
3583 #define MCF_LCDC_LICR (*(vuint32*)(0xFC0AC038))
3584 #define MCF_LCDC_LIER (*(vuint32*)(0xFC0AC03C))
3585 #define MCF_LCDC_LISR (*(vuint32*)(0xFC0AC040))
3586 #define MCF_LCDC_LGWSAR (*(vuint32*)(0xFC0AC050))
3587 #define MCF_LCDC_LGWSR (*(vuint32*)(0xFC0AC054))
3588 #define MCF_LCDC_LGWVPWR (*(vuint32*)(0xFC0AC058))
3589 #define MCF_LCDC_LGWPOR (*(vuint32*)(0xFC0AC05C))
3590 #define MCF_LCDC_LGWPR (*(vuint32*)(0xFC0AC060))
3591 #define MCF_LCDC_LGWCR (*(vuint32*)(0xFC0AC064))
3592 #define MCF_LCDC_LGWDCR (*(vuint32*)(0xFC0AC068))
3593 #define MCF_LCDC_BPLUT_BASE (*(vuint32*)(0xFC0AC800))
3594 #define MCF_LCDC_GWLUT_BASE (*(vuint32*)(0xFC0ACC00))
3595 
3596 /* Bit definitions and macros for MCF_LCDC_LSSAR */
3597 #define MCF_LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
3598 
3599 /* Bit definitions and macros for MCF_LCDC_LSR */
3600 #define MCF_LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0)
3601 #define MCF_LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20)
3602 
3603 /* Bit definitions and macros for MCF_LCDC_LVPWR */
3604 #define MCF_LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0)
3605 
3606 /* Bit definitions and macros for MCF_LCDC_LCPR */
3607 #define MCF_LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0)
3608 #define MCF_LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16)
3609 #define MCF_LCDC_LCPR_OP (0x10000000)
3610 #define MCF_LCDC_LCPR_CC(x) (((x)&0x00000003)<<30)
3611 #define MCF_LCDC_LCPR_CC_TRANSPARENT (0x00000000)
3612 #define MCF_LCDC_LCPR_CC_OR (0x40000000)
3613 #define MCF_LCDC_LCPR_CC_XOR (0x80000000)
3614 #define MCF_LCDC_LCPR_CC_AND (0xC0000000)
3615 #define MCF_LCDC_LCPR_OP_ON (0x10000000)
3616 #define MCF_LCDC_LCPR_OP_OFF (0x00000000)
3617 
3618 /* Bit definitions and macros for MCF_LCDC_LCWHBR */
3619 #define MCF_LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0)
3620 #define MCF_LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16)
3621 #define MCF_LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24)
3622 #define MCF_LCDC_LCWHBR_BK_EN (0x80000000)
3623 #define MCF_LCDC_LCWHBR_BK_EN_ON (0x80000000)
3624 #define MCF_LCDC_LCWHBR_BK_EN_OFF (0x00000000)
3625 
3626 /* Bit definitions and macros for MCF_LCDC_LCCMR */
3627 #define MCF_LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0)
3628 #define MCF_LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
3629 #define MCF_LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
3630 
3631 /* Bit definitions and macros for MCF_LCDC_LPCR */
3632 #define MCF_LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0)
3633 #define MCF_LCDC_LPCR_SHARP (0x00000040)
3634 #define MCF_LCDC_LPCR_SCLKSEL (0x00000080)
3635 #define MCF_LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8)
3636 #define MCF_LCDC_LPCR_ACDSEL (0x00008000)
3637 #define MCF_LCDC_LPCR_REV_VS (0x00010000)
3638 #define MCF_LCDC_LPCR_SWAP_SEL (0x00020000)
3639 #define MCF_LCDC_LPCR_ENDSEL (0x00040000)
3640 #define MCF_LCDC_LPCR_SCLKIDLE (0x00080000)
3641 #define MCF_LCDC_LPCR_OEPOL (0x00100000)
3642 #define MCF_LCDC_LPCR_CLKPOL (0x00200000)
3643 #define MCF_LCDC_LPCR_LPPOL (0x00400000)
3644 #define MCF_LCDC_LPCR_FLM (0x00800000)
3645 #define MCF_LCDC_LPCR_PIXPOL (0x01000000)
3646 #define MCF_LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25)
3647 #define MCF_LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28)
3648 #define MCF_LCDC_LPCR_COLOR (0x40000000)
3649 #define MCF_LCDC_LPCR_TFT (0x80000000)
3650 #define MCF_LCDC_LPCR_MODE_MONOCHROME (0x00000000)
3651 #define MCF_LCDC_LPCR_MODE_CSTN (0x40000000)
3652 #define MCF_LCDC_LPCR_MODE_TFT (0xC0000000)
3653 #define MCF_LCDC_LPCR_PBSIZ_1 (0x00000000)
3654 #define MCF_LCDC_LPCR_PBSIZ_2 (0x10000000)
3655 #define MCF_LCDC_LPCR_PBSIZ_4 (0x20000000)
3656 #define MCF_LCDC_LPCR_PBSIZ_8 (0x30000000)
3657 #define MCF_LCDC_LPCR_BPIX_1bpp (0x00000000)
3658 #define MCF_LCDC_LPCR_BPIX_2bpp (0x02000000)
3659 #define MCF_LCDC_LPCR_BPIX_4bpp (0x04000000)
3660 #define MCF_LCDC_LPCR_BPIX_8bpp (0x06000000)
3661 #define MCF_LCDC_LPCR_BPIX_12bpp (0x08000000)
3662 #define MCF_LCDC_LPCR_BPIX_16bpp (0x0A000000)
3663 #define MCF_LCDC_LPCR_BPIX_18bpp (0x0C000000)
3664 
3665 /* Bit definitions and macros for MCF_LCDC_LHCR */
3666 #define MCF_LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0)
3667 #define MCF_LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
3668 #define MCF_LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
3669 
3670 /* Bit definitions and macros for MCF_LCDC_LVCR */
3671 #define MCF_LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0)
3672 #define MCF_LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
3673 #define MCF_LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
3674 
3675 /* Bit definitions and macros for MCF_LCDC_LPOR */
3676 #define MCF_LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0)
3677 
3678 /* Bit definitions and macros for MCF_LCDC_LPCCR */
3679 #define MCF_LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0)
3680 #define MCF_LCDC_LPCCR_CC_EN (0x00000100)
3681 #define MCF_LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9)
3682 #define MCF_LCDC_LPCCR_LDMSK (0x00008000)
3683 #define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16)
3684 #define MCF_LCDC_LPCCR_SCR_LINEPULSE (0x00000000)
3685 #define MCF_LCDC_LPCCR_SCR_PIXELCLK (0x00002000)
3686 #define MCF_LCDC_LPCCR_SCR_LCDCLOCK (0x00004000)
3687 
3688 /* Bit definitions and macros for MCF_LCDC_LDCR */
3689 #define MCF_LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0)
3690 #define MCF_LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16)
3691 #define MCF_LCDC_LDCR_BURST (0x80000000)
3692 
3693 /* Bit definitions and macros for MCF_LCDC_LRMCR */
3694 #define MCF_LCDC_LRMCR_SEL_REF (0x00000001)
3695 
3696 /* Bit definitions and macros for MCF_LCDC_LICR */
3697 #define MCF_LCDC_LICR_INTCON (0x00000001)
3698 #define MCF_LCDC_LICR_INTSYN (0x00000004)
3699 #define MCF_LCDC_LICR_GW_INT_CON (0x00000010)
3700 
3701 /* Bit definitions and macros for MCF_LCDC_LIER */
3702 #define MCF_LCDC_LIER_BOF_EN (0x00000001)
3703 #define MCF_LCDC_LIER_EOF_EN (0x00000002)
3704 #define MCF_LCDC_LIER_ERR_RES_EN (0x00000004)
3705 #define MCF_LCDC_LIER_UDR_ERR_EN (0x00000008)
3706 #define MCF_LCDC_LIER_GW_BOF_EN (0x00000010)
3707 #define MCF_LCDC_LIER_GW_EOF_EN (0x00000020)
3708 #define MCF_LCDC_LIER_GW_ERR_RES_EN (0x00000040)
3709 #define MCF_LCDC_LIER_GW_UDR_ERR_EN (0x00000080)
3710 
3711 /* Bit definitions and macros for MCF_LCDC_LISR */
3712 #define MCF_LCDC_LISR_BOF (0x00000001)
3713 #define MCF_LCDC_LISR_EOF (0x00000002)
3714 #define MCF_LCDC_LISR_ERR_RES (0x00000004)
3715 #define MCF_LCDC_LISR_UDR_ERR (0x00000008)
3716 #define MCF_LCDC_LISR_GW_BOF (0x00000010)
3717 #define MCF_LCDC_LISR_GW_EOF (0x00000020)
3718 #define MCF_LCDC_LISR_GW_ERR_RES (0x00000040)
3719 #define MCF_LCDC_LISR_GW_UDR_ERR (0x00000080)
3720 
3721 /* Bit definitions and macros for MCF_LCDC_LGWSAR */
3722 #define MCF_LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
3723 
3724 /* Bit definitions and macros for MCF_LCDC_LGWSR */
3725 #define MCF_LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0)
3726 #define MCF_LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20)
3727 
3728 /* Bit definitions and macros for MCF_LCDC_LGWVPWR */
3729 #define MCF_LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0)
3730 
3731 /* Bit definitions and macros for MCF_LCDC_LGWPOR */
3732 #define MCF_LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0)
3733 
3734 /* Bit definitions and macros for MCF_LCDC_LGWPR */
3735 #define MCF_LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0)
3736 #define MCF_LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16)
3737 
3738 /* Bit definitions and macros for MCF_LCDC_LGWCR */
3739 #define MCF_LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0)
3740 #define MCF_LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
3741 #define MCF_LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
3742 #define MCF_LCDC_LGWCR_GW_RVS (0x00200000)
3743 #define MCF_LCDC_LGWCR_GWE (0x00400000)
3744 #define MCF_LCDC_LGWCR_GWCKE (0x00800000)
3745 #define MCF_LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24)
3746 
3747 /* Bit definitions and macros for MCF_LCDC_LGWDCR */
3748 #define MCF_LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0)
3749 #define MCF_LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
3750 #define MCF_LCDC_LGWDCR_GWBT (0x80000000)
3751 
3752 /* Bit definitions and macros for MCF_LCDC_LSCR */
3753 #define MCF_LCDC_LSCR_PS_RISE_DELAY(x) (((x)&0x0000003F)<<26)
3754 #define MCF_LCDC_LSCR_CLS_RISE_DELAY(x) (((x)&0x000000FF)<<16)
3755 #define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8)
3756 #define MCF_LCDC_LSCR_GRAY_2(x) (((x)&0x0000000F)<<4)
3757 #define MCF_LCDC_LSCR_GRAY_1(x) (((x)&0x0000000F)<<0)
3758 
3759 /* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */
3760 #define MCF_LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0)
3761 
3762 /* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */
3763 #define MCF_LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0)
3764 
3765 /*********************************************************************
3766 *
3767 * USB Controller (USB)
3768 *
3769 *********************************************************************/
3770 
3771 /* Register read/write macros */
3772 #define MCF_USB0_ID (*(vuint32*)(0xFC0B0000))
3773 #define MCF_USB0_HWGENERAL (*(vuint32*)(0xFC0B0004))
3774 #define MCF_USB0_HWHOST (*(vuint32*)(0xFC0B0008))
3775 #define MCF_USB0_HWDEVICE (*(vuint32*)(0xFC0B000C))
3776 #define MCF_USB0_HWTXBUF (*(vuint32*)(0xFC0B0010))
3777 #define MCF_USB0_HWRXBUF (*(vuint32*)(0xFC0B0014))
3778 #define MCF_USB0_CAPLENGTH (*(vuint8 *)(0xFC0B0100))
3779 #define MCF_USB0_HCIVERSION (*(vuint16*)(0xFC0B0102))
3780 #define MCF_USB0_HCSPARAMS (*(vuint32*)(0xFC0B0104))
3781 #define MCF_USB0_HCCPARAMS (*(vuint32*)(0xFC0B0108))
3782 #define MCF_USB0_DCIVERSION (*(vuint16*)(0xFC0B0120))
3783 #define MCF_USB0_DCCPARAMS (*(vuint32*)(0xFC0B0124))
3784 #define MCF_USB0_USBCMD (*(vuint32*)(0xFC0B0140))
3785 #define MCF_USB0_USBSTS (*(vuint32*)(0xFC0B0144))
3786 #define MCF_USB0_USBINTR (*(vuint32*)(0xFC0B0148))
3787 #define MCF_USB0_FRINDEX (*(vuint32*)(0xFC0B014C))
3788 #define MCF_USB0_PERIODICLISTBASE (*(vuint32*)(0xFC0B0154))
3789 #define MCF_USB0_DEVICEADDR (*(vuint32*)(0xFC0B0154))
3790 #define MCF_USB0_ASYNCLISTADDR (*(vuint32*)(0xFC0B0158))
3791 #define MCF_USB0_EPLISTADDR (*(vuint32*)(0xFC0B0158))
3792 #define MCF_USB0_ASYNCTTSTS (*(vuint32*)(0xFC0B015C))
3793 #define MCF_USB0_BURSTSIZE (*(vuint32*)(0xFC0B0160))
3794 #define MCF_USB0_TXFILLTUNING (*(vuint32*)(0xFC0B0164))
3795 #define MCF_USB0_TXTTFILLTUNING (*(vuint32*)(0xFC0B0168))
3796 #define MCF_USB_ULPI0_VIEWPORT (*(vuint32*)(0xFC0B0170))
3797 #define MCF_USB0_CONFIGFLAG (*(vuint32*)(0xFC0B0180))
3798 #define MCF_USB0_PORTSC (*(vuint32*)(0xFC0B0184))
3799 #define MCF_USB0_OTGSC (*(vuint32*)(0xFC0B01A4))
3800 #define MCF_USB0_USBMODE (*(vuint32*)(0xFC0B01A8))
3801 #define MCF_USB0_EPSETUPSR (*(vuint32*)(0xFC0B01AC))
3802 #define MCF_USB0_EPPRIME (*(vuint32*)(0xFC0B01B0))
3803 #define MCF_USB0_EPFLUSH (*(vuint32*)(0xFC0B01B4))
3804 #define MCF_USB0_EPSR (*(vuint32*)(0xFC0B01B8))
3805 #define MCF_USB0_EPCOMPLETE (*(vuint32*)(0xFC0B01BC))
3806 #define MCF_USB0_EPCR0 (*(vuint32*)(0xFC0B01C0))
3807 #define MCF_USB0_EPCR1 (*(vuint32*)(0xFC0B01C4))
3808 #define MCF_USB0_EPCR2 (*(vuint32*)(0xFC0B01C8))
3809 #define MCF_USB0_EPCR3 (*(vuint32*)(0xFC0B01CC))
3810 #define MCF_USB0_EPCR(x) (*(vuint32*)(0xFC0B01C4+((x-1)*0x004)))
3811 #define MCF_USB1_ID (*(vuint32*)(0xFC0B4000))
3812 #define MCF_USB1_HWGENERAL (*(vuint32*)(0xFC0B4004))
3813 #define MCF_USB1_HWHOST (*(vuint32*)(0xFC0B4008))
3814 #define MCF_USB1_HWDEVICE (*(vuint32*)(0xFC0B400C))
3815 #define MCF_USB1_HWTXBUF (*(vuint32*)(0xFC0B4010))
3816 #define MCF_USB1_HWRXBUF (*(vuint32*)(0xFC0B4014))
3817 #define MCF_USB1_CAPLENGTH (*(vuint8 *)(0xFC0B4100))
3818 #define MCF_USB1_HCIVERSION (*(vuint16*)(0xFC0B4102))
3819 #define MCF_USB1_HCSPARAMS (*(vuint32*)(0xFC0B4104))
3820 #define MCF_USB1_HCCPARAMS (*(vuint32*)(0xFC0B4108))
3821 #define MCF_USB1_DCIVERSION (*(vuint16*)(0xFC0B4120))
3822 #define MCF_USB1_DCCPARAMS (*(vuint32*)(0xFC0B4124))
3823 #define MCF_USB1_USBCMD (*(vuint32*)(0xFC0B4140))
3824 #define MCF_USB1_USBSTS (*(vuint32*)(0xFC0B4144))
3825 #define MCF_USB1_USBINTR (*(vuint32*)(0xFC0B4148))
3826 #define MCF_USB1_FRINDEX (*(vuint32*)(0xFC0B414C))
3827 #define MCF_USB1_PERIODICLISTBASE (*(vuint32*)(0xFC0B4154))
3828 #define MCF_USB1_DEVICEADDR (*(vuint32*)(0xFC0B4154))
3829 #define MCF_USB1_ASYNCLISTADDR (*(vuint32*)(0xFC0B4158))
3830 #define MCF_USB1_EPLISTADDR (*(vuint32*)(0xFC0B4158))
3831 #define MCF_USB1_ASYNCTTSTS (*(vuint32*)(0xFC0B415C))
3832 #define MCF_USB1_BURSTSIZE (*(vuint32*)(0xFC0B4160))
3833 #define MCF_USB1_TXFILLTUNING (*(vuint32*)(0xFC0B4164))
3834 #define MCF_USB1_TXTTFILLTUNING (*(vuint32*)(0xFC0B4168))
3835 #define MCF_USB_ULPI1_VIEWPORT (*(vuint32*)(0xFC0B4170))
3836 #define MCF_USB1_CONFIGFLAG (*(vuint32*)(0xFC0B4180))
3837 #define MCF_USB1_PORTSC (*(vuint32*)(0xFC0B4184))
3838 #define MCF_USB1_OTGSC (*(vuint32*)(0xFC0B41A4))
3839 #define MCF_USB1_USBMODE (*(vuint32*)(0xFC0B41A8))
3840 #define MCF_USB1_EPSETUPSR (*(vuint32*)(0xFC0B41AC))
3841 #define MCF_USB1_EPPRIME (*(vuint32*)(0xFC0B41B0))
3842 #define MCF_USB1_EPFLUSH (*(vuint32*)(0xFC0B41B4))
3843 #define MCF_USB1_EPSR (*(vuint32*)(0xFC0B41B8))
3844 #define MCF_USB1_EPCOMPLETE (*(vuint32*)(0xFC0B41BC))
3845 #define MCF_USB1_EPCR0 (*(vuint32*)(0xFC0B41C0))
3846 #define MCF_USB1_EPCR1 (*(vuint32*)(0xFC0B41C4))
3847 #define MCF_USB1_EPCR2 (*(vuint32*)(0xFC0B41C8))
3848 #define MCF_USB1_EPCR3 (*(vuint32*)(0xFC0B41CC))
3849 #define MCF_USB1_EPCR(x) (*(vuint32*)(0xFC0B41C4+((x-1)*0x004)))
3850 #define MCF_USB_ID(x) (*(vuint32*)(0xFC0B0000+((x)*0x4000)))
3851 #define MCF_USB_HWGENERAL(x) (*(vuint32*)(0xFC0B0004+((x)*0x4000)))
3852 #define MCF_USB_HWHOST(x) (*(vuint32*)(0xFC0B0008+((x)*0x4000)))
3853 #define MCF_USB_HWDEVICE(x) (*(vuint32*)(0xFC0B000C+((x)*0x4000)))
3854 #define MCF_USB_HWTXBUF(x) (*(vuint32*)(0xFC0B0010+((x)*0x4000)))
3855 #define MCF_USB_HWRXBUF(x) (*(vuint32*)(0xFC0B0014+((x)*0x4000)))
3856 #define MCF_USB_CAPLENGTH(x) (*(vuint8 *)(0xFC0B0100+((x)*0x4000)))
3857 #define MCF_USB_HCIVERSION(x) (*(vuint16*)(0xFC0B0102+((x)*0x4000)))
3858 #define MCF_USB_HCSPARAMS(x) (*(vuint32*)(0xFC0B0104+((x)*0x4000)))
3859 #define MCF_USB_HCCPARAMS(x) (*(vuint32*)(0xFC0B0108+((x)*0x4000)))
3860 #define MCF_USB_DCIVERSION(x) (*(vuint16*)(0xFC0B0120+((x)*0x4000)))
3861 #define MCF_USB_DCCPARAMS(x) (*(vuint32*)(0xFC0B0124+((x)*0x4000)))
3862 #define MCF_USB_USBCMD(x) (*(vuint32*)(0xFC0B0140+((x)*0x4000)))
3863 #define MCF_USB_USBSTS(x) (*(vuint32*)(0xFC0B0144+((x)*0x4000)))
3864 #define MCF_USB_USBINTR(x) (*(vuint32*)(0xFC0B0148+((x)*0x4000)))
3865 #define MCF_USB_FRINDEX(x) (*(vuint32*)(0xFC0B014C+((x)*0x4000)))
3866 #define MCF_USB_PERIODICLISTBASE(x) (*(vuint32*)(0xFC0B0154+((x)*0x4000)))
3867 #define MCF_USB_DEVICEADDR(x) (*(vuint32*)(0xFC0B0154+((x)*0x4000)))
3868 #define MCF_USB_ASYNCLISTADDR(x) (*(vuint32*)(0xFC0B0158+((x)*0x4000)))
3869 #define MCF_USB_EPLISTADDR(x) (*(vuint32*)(0xFC0B0158+((x)*0x4000)))
3870 #define MCF_USB_ASYNCTTSTS(x) (*(vuint32*)(0xFC0B015C+((x)*0x4000)))
3871 #define MCF_USB_BURSTSIZE(x) (*(vuint32*)(0xFC0B0160+((x)*0x4000)))
3872 #define MCF_USB_TXFILLTUNING(x) (*(vuint32*)(0xFC0B0164+((x)*0x4000)))
3873 #define MCF_USB_TXTTFILLTUNING(x) (*(vuint32*)(0xFC0B0168+((x)*0x4000)))
3874 #define MCF_USB_ULPI_VIEWPORT(x) (*(vuint32*)(0xFC0B0170+((x)*0x4000)))
3875 #define MCF_USB_CONFIGFLAG(x) (*(vuint32*)(0xFC0B0180+((x)*0x4000)))
3876 #define MCF_USB_PORTSC(x) (*(vuint32*)(0xFC0B0184+((x)*0x4000)))
3877 #define MCF_USB_OTGSC(x) (*(vuint32*)(0xFC0B01A4+((x)*0x4000)))
3878 #define MCF_USB_USBMODE(x) (*(vuint32*)(0xFC0B01A8+((x)*0x4000)))
3879 #define MCF_USB_EPSETUPSR(x) (*(vuint32*)(0xFC0B01AC+((x)*0x4000)))
3880 #define MCF_USB_EPPRIME(x) (*(vuint32*)(0xFC0B01B0+((x)*0x4000)))
3881 #define MCF_USB_EPFLUSH(x) (*(vuint32*)(0xFC0B01B4+((x)*0x4000)))
3882 #define MCF_USB_EPSR(x) (*(vuint32*)(0xFC0B01B8+((x)*0x4000)))
3883 #define MCF_USB_EPCOMPLETE(x) (*(vuint32*)(0xFC0B01BC+((x)*0x4000)))
3884 #define MCF_USB_EPCR0(x) (*(vuint32*)(0xFC0B01C0+((x)*0x4000)))
3885 #define MCF_USB_EPCR1(x) (*(vuint32*)(0xFC0B01C4+((x)*0x4000)))
3886 #define MCF_USB_EPCR2(x) (*(vuint32*)(0xFC0B01C8+((x)*0x4000)))
3887 #define MCF_USB_EPCR3(x) (*(vuint32*)(0xFC0B01CC+((x)*0x4000)))
3888 
3889 /* Bit definitions and macros for MCF_USB_ID */
3890 #define MCF_USB_ID_RESERVED (0x0000C000)
3891 #define MCF_USB_ID_ID(x) (((x)&0x0000003F)<<0|0x0000C000)
3892 #define MCF_USB_ID_NID(x) (((x)&0x0000003F)<<8|0x0000C000)
3893 #define MCF_USB_ID_REVISION(x) (((x)&0x000000FF)<<16|0x0000C000)
3894 
3895 /* Bit definitions and macros for MCF_USB_HWGENERAL */
3896 #define MCF_USB_HWGENERAL_RT (0x00000001)
3897 #define MCF_USB_HWGENERAL_CLKC(x) (((x)&0x00000003)<<1)
3898 #define MCF_USB_HWGENERAL_BWT (0x00000008)
3899 #define MCF_USB_HWGENERAL_PHYW(x) (((x)&0x00000003)<<4)
3900 #define MCF_USB_HWGENERAL_PHYM(x) (((x)&0x00000007)<<6)
3901 #define MCF_USB_HWGENERAL_SM(x) (((x)&0x00000003)<<9)
3902 
3903 /* Bit definitions and macros for MCF_USB_HWHOST */
3904 #define MCF_USB_HWHOST_HC (0x00000001)
3905 #define MCF_USB_HWHOST_NPORT(x) (((x)&0x00000007)<<1)
3906 #define MCF_USB_HWHOST_TTASY(x) (((x)&0x000000FF)<<16)
3907 #define MCF_USB_HWHOST_TTPER(x) (((x)&0x000000FF)<<24)
3908 
3909 /* Bit definitions and macros for MCF_USB_HWDEVICE */
3910 #define MCF_USB_HWDEVICE_DC (0x00000001)
3911 #define MCF_USB_HWDEVICE_DEVEP(x) (((x)&0x0000001F)<<1)
3912 
3913 /* Bit definitions and macros for MCF_USB_HWTXBUF */
3914 #define MCF_USB_HWTXBUF_TXBURST(x) (((x)&0x000000FF)<<0)
3915 #define MCF_USB_HWTXBUF_TXADD(x) (((x)&0x000000FF)<<8)
3916 #define MCF_USB_HWTXBUF_TXCHANADD(x) (((x)&0x000000FF)<<16)
3917 #define MCF_USB_HWTXBUF_TXLC (0x80000000)
3918 
3919 /* Bit definitions and macros for MCF_USB_HWRXBUF */
3920 #define MCF_USB_HWRXBUF_RXBURST(x) (((x)&0x000000FF)<<0)
3921 #define MCF_USB_HWRXBUF_RXADD(x) (((x)&0x000000FF)<<8)
3922 
3923 /* Bit definitions and macros for MCF_USB_CAPLENGTH */
3924 #define MCF_USB_CAPLENGTH_CAPLENGTH(x) (((x)&0xFF)<<0)
3925 
3926 /* Bit definitions and macros for MCF_USB_HCIVERSION */
3927 #define MCF_USB_HCIVERSION_HCIVERSION(x) (((x)&0xFFFF)<<0)
3928 
3929 /* Bit definitions and macros for MCF_USB_HCSPARAMS */
3930 #define MCF_USB_HCSPARAMS_N_PORTS(x) (((x)&0x0000000F)<<0)
3931 #define MCF_USB_HCSPARAMS_PPC (0x00000010)
3932 #define MCF_USB_HCSPARAMS_N_PCC(x) (((x)&0x0000000F)<<8)
3933 #define MCF_USB_HCSPARAMS_N_CC(x) (((x)&0x0000000F)<<12)
3934 #define MCF_USB_HCSPARAMS_PI (0x00010000)
3935 #define MCF_USB_HCSPARAMS_N_PTT(x) (((x)&0x0000000F)<<20)
3936 #define MCF_USB_HCSPARAMS_N_TT(x) (((x)&0x0000000F)<<24)
3937 
3938 /* Bit definitions and macros for MCF_USB_HCCPARAMS */
3939 #define MCF_USB_HCCPARAMS_ADC (0x00000001)
3940 #define MCF_USB_HCCPARAMS_PFL (0x00000002)
3941 #define MCF_USB_HCCPARAMS_ASP (0x00000004)
3942 #define MCF_USB_HCCPARAMS_IST(x) (((x)&0x0000000F)<<4)
3943 #define MCF_USB_HCCPARAMS_EECP(x) (((x)&0x000000FF)<<8)
3944 
3945 /* Bit definitions and macros for MCF_USB_DCIVERSION */
3946 #define MCF_USB_DCIVERSION_DCIVERSION(x) (((x)&0xFFFF)<<0)
3947 
3948 /* Bit definitions and macros for MCF_USB_DCCPARAMS */
3949 #define MCF_USB_DCCPARAMS_DEN(x) (((x)&0x0000001F)<<0)
3950 #define MCF_USB_DCCPARAMS_DC (0x00000080)
3951 #define MCF_USB_DCCPARAMS_HC (0x00000100)
3952 
3953 /* Bit definitions and macros for MCF_USB_USBCMD */
3954 #define MCF_USB_USBCMD_RS (0x00000001)
3955 #define MCF_USB_USBCMD_RST (0x00000002)
3956 #define MCF_USB_USBCMD_FS0 (0x00000004)
3957 #define MCF_USB_USBCMD_FS1 (0x00000008)
3958 #define MCF_USB_USBCMD_PSE (0x00000010)
3959 #define MCF_USB_USBCMD_ASE (0x00000020)
3960 #define MCF_USB_USBCMD_IAA (0x00000040)
3961 #define MCF_USB_USBCMD_LR (0x00000080)
3962 #define MCF_USB_USBCMD_ASP(x) (((x)&0x00000003)<<8)
3963 #define MCF_USB_USBCMD_ASPE (0x00000800)
3964 #define MCF_USB_USBCMD_SUTW (0x00002000)
3965 #define MCF_USB_USBCMD_ATDTW (0x00004000)
3966 #define MCF_USB_USBCMD_FS2 (0x00008000)
3967 #define MCF_USB_USBCMD_ITC(x) (((x)&0x000000FF)<<16)
3968 #define MCF_USB_USBCMD_ITC_IMM (0x00000000)
3969 #define MCF_USB_USBCMD_ITC_1 (0x00010000)
3970 #define MCF_USB_USBCMD_ITC_2 (0x00020000)
3971 #define MCF_USB_USBCMD_ITC_4 (0x00040000)
3972 #define MCF_USB_USBCMD_ITC_8 (0x00080000)
3973 #define MCF_USB_USBCMD_ITC_16 (0x00100000)
3974 #define MCF_USB_USBCMD_ITC_32 (0x00200000)
3975 #define MCF_USB_USBCMD_ITC_40 (0x00400000)
3976 #define MCF_USB_USBCMD_FS_1024 (0x00000000)
3977 #define MCF_USB_USBCMD_FS_512 (0x00000004)
3978 #define MCF_USB_USBCMD_FS_256 (0x00000008)
3979 #define MCF_USB_USBCMD_FS_128 (0x0000000C)
3980 #define MCF_USB_USBCMD_FS_64 (0x00008000)
3981 #define MCF_USB_USBCMD_FS_32 (0x00008004)
3982 #define MCF_USB_USBCMD_FS_16 (0x00008008)
3983 #define MCF_USB_USBCMD_FS_8 (0x0000800C)
3984 
3985 /* Bit definitions and macros for MCF_USB_USBSTS */
3986 #define MCF_USB_USBSTS_UI (0x00000001)
3987 #define MCF_USB_USBSTS_UEI (0x00000002)
3988 #define MCF_USB_USBSTS_PCI (0x00000004)
3989 #define MCF_USB_USBSTS_FRI (0x00000008)
3990 #define MCF_USB_USBSTS_SEI (0x00000010)
3991 #define MCF_USB_USBSTS_AAI (0x00000020)
3992 #define MCF_USB_USBSTS_URI (0x00000040)
3993 #define MCF_USB_USBSTS_SRI (0x00000080)
3994 #define MCF_USB_USBSTS_SLI (0x00000100)
3995 #define MCF_USB_USBSTS_HCH (0x00001000)
3996 #define MCF_USB_USBSTS_RCL (0x00002000)
3997 #define MCF_USB_USBSTS_PS (0x00004000)
3998 #define MCF_USB_USBSTS_AS (0x00008000)
3999 
4000 /* Bit definitions and macros for MCF_USB_USBINTR */
4001 #define MCF_USB_USBINTR_UE (0x00000001)
4002 #define MCF_USB_USBINTR_UEE (0x00000002)
4003 #define MCF_USB_USBINTR_PCE (0x00000004)
4004 #define MCF_USB_USBINTR_FRE (0x00000008)
4005 #define MCF_USB_USBINTR_SEE (0x00000010)
4006 #define MCF_USB_USBINTR_AAE (0x00000020)
4007 #define MCF_USB_USBINTR_URE (0x00000040)
4008 #define MCF_USB_USBINTR_SRE (0x00000080)
4009 #define MCF_USB_USBINTR_SLE (0x00000100)
4010 
4011 /* Bit definitions and macros for MCF_USB_FRINDEX */
4012 #define MCF_USB_FRINDEX_FRINDEX(x) (((x)&0x00003FFF)<<0)
4013 
4014 /* Bit definitions and macros for MCF_USB_PERIODICLISTBASE */
4015 #define MCF_USB_PERIODICLISTBASE_PERBASE(x) (((x)&0x000FFFFF)<<12)
4016 
4017 /* Bit definitions and macros for MCF_USB_DEVICEADDR */
4018 #define MCF_USB_DEVICEADDR_USBADR(x) (((x)&0x0000007F)<<25)
4019 
4020 /* Bit definitions and macros for MCF_USB_ASYNCLISTADDR */
4021 #define MCF_USB_ASYNCLISTADDR_ASYBASE(x) (((x)&0x07FFFFFF)<<5)
4022 
4023 /* Bit definitions and macros for MCF_USB_EPLISTADDR */
4024 #define MCF_USB_EPLISTADDR_EPBASE(x) (((x)&0x001FFFFF)<<11)
4025 
4026 /* Bit definitions and macros for MCF_USB_ASYNCTTSTS */
4027 #define MCF_USB_ASYNCTTSTS_TTAS (0x00000001)
4028 #define MCF_USB_ASYNCTTSTS_TTAC (0x00000002)
4029 
4030 /* Bit definitions and macros for MCF_USB_BURSTSIZE */
4031 #define MCF_USB_BURSTSIZE_RXPBURST(x) (((x)&0x000000FF)<<0)
4032 #define MCF_USB_BURSTSIZE_TXPBURST(x) (((x)&0x000000FF)<<8)
4033 
4034 /* Bit definitions and macros for MCF_USB_TXFILLTUNING */
4035 #define MCF_USB_TXFILLTUNING_TXSCHOH(x) (((x)&0x000000FF)<<0)
4036 #define MCF_USB_TXFILLTUNING_TXSCHHEALTH(x) (((x)&0x0000001F)<<8)
4037 #define MCF_USB_TXFILLTUNING_TXFIFOTHRES(x) (((x)&0x0000003F)<<16)
4038 
4039 /* Bit definitions and macros for MCF_USB_TXTTFILLTUNING */
4040 #define MCF_USB_TXTTFILLTUNING_TXTTSCHOH(x) (((x)&0x0000001F)<<0)
4041 #define MCF_USB_TXTTFILLTUNING_TXTTSCHHEALTH(x) (((x)&0x0000001F)<<8)
4042 
4043 /* Bit definitions and macros for MCF_USB_CONFIGFLAG */
4044 #define MCF_USB_CONFIGFLAG_CONFIGFLAG(x) (((x)&0xFFFFFFFF)<<0)
4045 
4046 /* Bit definitions and macros for MCF_USB_PORTSC */
4047 #define MCF_USB_PORTSC_CCS (0x00000001)
4048 #define MCF_USB_PORTSC_CSC (0x00000002)
4049 #define MCF_USB_PORTSC_PE (0x00000004)
4050 #define MCF_USB_PORTSC_PEC (0x00000008)
4051 #define MCF_USB_PORTSC_OCA (0x00000010)
4052 #define MCF_USB_PORTSC_OCC (0x00000020)
4053 #define MCF_USB_PORTSC_FPR (0x00000040)
4054 #define MCF_USB_PORTSC_SUSP (0x00000080)
4055 #define MCF_USB_PORTSC_PR (0x00000100)
4056 #define MCF_USB_PORTSC_LS(x) (((x)&0x00000003)<<10)
4057 #define MCF_USB_PORTSC_PP (0x00001000)
4058 #define MCF_USB_PORTSC_PO (0x00002000)
4059 #define MCF_USB_PORTSC_PIC(x) (((x)&0x00000003)<<14)
4060 #define MCF_USB_PORTSC_PTC(x) (((x)&0x0000000F)<<16)
4061 #define MCF_USB_PORTSC_WLCN (0x00100000)
4062 #define MCF_USB_PORTSC_WKDS (0x00200000)
4063 #define MCF_USB_PORTSC_WKOC (0x00400000)
4064 #define MCF_USB_PORTSC_PHCD (0x00800000)
4065 #define MCF_USB_PORTSC_PFSC (0x01000000)
4066 #define MCF_USB_PORTSC_PSPD(x) (((x)&0x00000003)<<26)
4067 #define MCF_USB_PORTSC_PTS(x) (((x)&0x00000003)<<30)
4068 #define MCF_USB_PORTSC_PTS_ULPI (0x80000000)
4069 #define MCF_USB_PORTSC_PTS_FS_LS (0xC0000000)
4070 #define MCF_USB_PORTSC_PSPD_FULL (0x00000000)
4071 #define MCF_USB_PORTSC_PSPD_LOW (0x04000000)
4072 #define MCF_USB_PORTSC_PSPD_HIGH (0x08000000)
4073 #define MCF_USB_PORTSC_PTC_DISBALE (0x00000000)
4074 #define MCF_USB_PORTSC_PTC_JSTATE (0x00010000)
4075 #define MCF_USB_PORTSC_PTC_KSTATE (0x00020000)
4076 #define MCF_USB_PORTSC_PTC_SEQ_NAK (0x00030000)
4077 #define MCF_USB_PORTSC_PTC_PACKET (0x00040000)
4078 #define MCF_USB_PORTSC_PTC_FORCE_ENABLE (0x00050000)
4079 #define MCF_USB_PORTSC_PIC_OFF (0x00000000)
4080 #define MCF_USB_PORTSC_PIC_AMBER (0x00004000)
4081 #define MCF_USB_PORTSC_PIC_GREEN (0x00008000)
4082 #define MCF_USB_PORTSC_LS_SE0 (0x00000000)
4083 #define MCF_USB_PORTSC_LS_JSTATE (0x00000400)
4084 #define MCF_USB_PORTSC_LS_KSTATE (0x00000800)
4085 
4086 /* Bit definitions and macros for MCF_USB_OTGSC */
4087 #define MCF_USB_OTGSC_VD (0x00000001)
4088 #define MCF_USB_OTGSC_VC (0x00000002)
4089 #define MCF_USB_OTGSC_OT (0x00000008)
4090 #define MCF_USB_OTGSC_DP (0x00000010)
4091 #define MCF_USB_OTGSC_ID (0x00000100)
4092 #define MCF_USB_OTGSC_AVV (0x00000200)
4093 #define MCF_USB_OTGSC_ASV (0x00000400)
4094 #define MCF_USB_OTGSC_BSV (0x00000800)
4095 #define MCF_USB_OTGSC_BSE (0x00001000)
4096 #define MCF_USB_OTGSC_1MST (0x00002000)
4097 #define MCF_USB_OTGSC_DPS (0x00004000)
4098 #define MCF_USB_OTGSC_IDIS (0x00010000)
4099 #define MCF_USB_OTGSC_AVVIS (0x00020000)
4100 #define MCF_USB_OTGSC_ASVIS (0x00040000)
4101 #define MCF_USB_OTGSC_BSVIS (0x00080000)
4102 #define MCF_USB_OTGSC_BSEIS (0x00100000)
4103 #define MCF_USB_OTGSC_1MSS (0x00200000)
4104 #define MCF_USB_OTGSC_DPIS (0x00400000)
4105 #define MCF_USB_OTGSC_IDIE (0x01000000)
4106 #define MCF_USB_OTGSC_AVVIE (0x02000000)
4107 #define MCF_USB_OTGSC_ASVIE (0x04000000)
4108 #define MCF_USB_OTGSC_BSVIE (0x08000000)
4109 #define MCF_USB_OTGSC_BSEIE (0x10000000)
4110 #define MCF_USB_OTGSC_1MSE (0x20000000)
4111 #define MCF_USB_OTGSC_DPIE (0x40000000)
4112 #define MCF_USB_OTGSC_CLEAR (0x007F0000)
4113 #define MCF_USB_OTGSC_ENABLE_ALL (0x7F000000)
4114 
4115 /* Bit definitions and macros for MCF_USB_USBMODE */
4116 #define MCF_USB_USBMODE_CM(x) (((x)&0x00000003)<<0)
4117 #define MCF_USB_USBMODE_ES (0x00000004)
4118 #define MCF_USB_USBMODE_SLOM (0x00000008)
4119 #define MCF_USB_USBMODE_SDIS (0x00000010)
4120 #define MCF_USB_USBMODE_CM_IDLE (0x00000000)
4121 #define MCF_USB_USBMODE_CM_DEVICE (0x00000002)
4122 #define MCF_USB_USBMODE_CM_HOST (0x00000003)
4123 
4124 /* Bit definitions and macros for MCF_USB_EPSETUPSR */
4125 #define MCF_USB_EPSETUPSR_EPSETUPSTAT(x) (((x)&0x0000003F)<<0)
4126 
4127 /* Bit definitions and macros for MCF_USB_EPPRIME */
4128 #define MCF_USB_EPPRIME_PERB(x) (((x)&0x0000003F)<<0)
4129 #define MCF_USB_EPPRIME_PETB(x) (((x)&0x0000003F)<<16)
4130 #define MCF_USB_EPPRIME_PETB0 (0x00010000)
4131 #define MCF_USB_EPPRIME_PETB1 (0x00020000)
4132 #define MCF_USB_EPPRIME_PETB2 (0x00040000)
4133 #define MCF_USB_EPPRIME_PETB3 (0x00080000)
4134 #define MCF_USB_EPPRIME_PETB4 (0x00100000)
4135 #define MCF_USB_EPPRIME_PETB5 (0x00200000)
4136 #define MCF_USB_EPPRIME_PERB0 (0x00000001)
4137 #define MCF_USB_EPPRIME_PERB1 (0x00000002)
4138 #define MCF_USB_EPPRIME_PERB2 (0x00000004)
4139 #define MCF_USB_EPPRIME_PERB3 (0x00000008)
4140 #define MCF_USB_EPPRIME_PERB4 (0x00000010)
4141 #define MCF_USB_EPPRIME_PERB5 (0x00000020)
4142 
4143 /* Bit definitions and macros for MCF_USB_EPFLUSH */
4144 #define MCF_USB_EPFLUSH_FERB(x) (((x)&0x0000003F)<<0)
4145 #define MCF_USB_EPFLUSH_FETB(x) (((x)&0x0000003F)<<16)
4146 #define MCF_USB_EPFLUSH_FETB0 (0x00010000)
4147 #define MCF_USB_EPFLUSH_FETB1 (0x00020000)
4148 #define MCF_USB_EPFLUSH_FETB2 (0x00040000)
4149 #define MCF_USB_EPFLUSH_FETB3 (0x00080000)
4150 #define MCF_USB_EPFLUSH_FETB4 (0x00100000)
4151 #define MCF_USB_EPFLUSH_FETB5 (0x00200000)
4152 #define MCF_USB_EPFLUSH_FERB0 (0x00000001)
4153 #define MCF_USB_EPFLUSH_FERB1 (0x00000002)
4154 #define MCF_USB_EPFLUSH_FERB2 (0x00000004)
4155 #define MCF_USB_EPFLUSH_FERB3 (0x00000008)
4156 #define MCF_USB_EPFLUSH_FERB4 (0x00000010)
4157 #define MCF_USB_EPFLUSH_FERB5 (0x00000020)
4158 
4159 /* Bit definitions and macros for MCF_USB_EPSR */
4160 #define MCF_USB_EPSR_ERBR(x) (((x)&0x0000003F)<<0)
4161 #define MCF_USB_EPSR_ETBR(x) (((x)&0x0000003F)<<16)
4162 #define MCF_USB_EPSR_ETBR0 (0x00010000)
4163 #define MCF_USB_EPSR_ETBR1 (0x00020000)
4164 #define MCF_USB_EPSR_ETBR2 (0x00040000)
4165 #define MCF_USB_EPSR_ETBR3 (0x00080000)
4166 #define MCF_USB_EPSR_ETBR4 (0x00100000)
4167 #define MCF_USB_EPSR_ETBR5 (0x00200000)
4168 #define MCF_USB_EPSR_ERBR0 (0x00000001)
4169 #define MCF_USB_EPSR_ERBR1 (0x00000002)
4170 #define MCF_USB_EPSR_ERBR2 (0x00000004)
4171 #define MCF_USB_EPSR_ERBR3 (0x00000008)
4172 #define MCF_USB_EPSR_ERBR4 (0x00000010)
4173 #define MCF_USB_EPSR_ERBR5 (0x00000020)
4174 
4175 /* Bit definitions and macros for MCF_USB_EPCOMPLETE */
4176 #define MCF_USB_EPCOMPLETE_ERCE(x) (((x)&0x0000003F)<<0)
4177 #define MCF_USB_EPCOMPLETE_ETCE(x) (((x)&0x0000003F)<<16)
4178 #define MCF_USB_EPCOMPLETE_ETCE0 (0x00010000)
4179 #define MCF_USB_EPCOMPLETE_ETCE1 (0x00020000)
4180 #define MCF_USB_EPCOMPLETE_ETCE2 (0x00040000)
4181 #define MCF_USB_EPCOMPLETE_ETCE3 (0x00080000)
4182 #define MCF_USB_EPCOMPLETE_ETCE4 (0x00100000)
4183 #define MCF_USB_EPCOMPLETE_ETCE5 (0x00200000)
4184 #define MCF_USB_EPCOMPLETE_ERCE0 (0x00000001)
4185 #define MCF_USB_EPCOMPLETE_ERCE1 (0x00000002)
4186 #define MCF_USB_EPCOMPLETE_ERCE2 (0x00000004)
4187 #define MCF_USB_EPCOMPLETE_ERCE3 (0x00000008)
4188 #define MCF_USB_EPCOMPLETE_ERCE4 (0x00000010)
4189 #define MCF_USB_EPCOMPLETE_ERCE5 (0x00000020)
4190 
4191 /* Bit definitions and macros for MCF_USB_EPCR0 */
4192 #define MCF_USB_EPCR0_RXS (0x00000001)
4193 #define MCF_USB_EPCR0_RXT(x) (((x)&0x00000003)<<2)
4194 #define MCF_USB_EPCR0_RXE (0x00000080)
4195 #define MCF_USB_EPCR0_TXS (0x00010000)
4196 #define MCF_USB_EPCR0_TXT(x) (((x)&0x00000003)<<18)
4197 #define MCF_USB_EPCR0_TXE (0x00800000)
4198 
4199 /* Bit definitions and macros for MCF_USB_EPCR */
4200 #define MCF_USB_EPCR_RXS (0x00000001)
4201 #define MCF_USB_EPCR_RXD (0x00000002)
4202 #define MCF_USB_EPCR_RXT(x) (((x)&0x00000003)<<2)
4203 #define MCF_USB_EPCR_RXI (0x00000020)
4204 #define MCF_USB_EPCR_RXR (0x00000040)
4205 #define MCF_USB_EPCR_RXE (0x00000080)
4206 #define MCF_USB_EPCR_TXS (0x00010000)
4207 #define MCF_USB_EPCR_TXD (0x00020000)
4208 #define MCF_USB_EPCR_TXT(x) (((x)&0x00000003)<<18)
4209 #define MCF_USB_EPCR_TXI (0x00200000)
4210 #define MCF_USB_EPCR_TXR (0x00400000)
4211 #define MCF_USB_EPCR_TXE (0x00800000)
4212 #define MCF_USB_EPCR_TXT_CONTROL (0x00000000)
4213 #define MCF_USB_EPCR_TXT_ISO (0x00040000)
4214 #define MCF_USB_EPCR_TXT_BULK (0x00080000)
4215 #define MCF_USB_EPCR_TXT_INT (0x000C0000)
4216 #define MCF_USB_EPCR_RXT_CONTROL (0x00000000)
4217 #define MCF_USB_EPCR_RXT_ISO (0x00000004)
4218 #define MCF_USB_EPCR_RXT_BULK (0x00000008)
4219 #define MCF_USB_EPCR_RXT_INT (0x0000000C)
4220 
4221 /*********************************************************************
4222 *
4223 * SDRAM Controller (SDRAMC)
4224 *
4225 *********************************************************************/
4226 
4227 /* Register read/write macros */
4228 #define MCF_SDRAMC_SDMR (*(vuint32*)(0xFC0B8000))
4229 #define MCF_SDRAMC_SDCR (*(vuint32*)(0xFC0B8004))
4230 #define MCF_SDRAMC_SDCFG1 (*(vuint32*)(0xFC0B8008))
4231 #define MCF_SDRAMC_SDCFG2 (*(vuint32*)(0xFC0B800C))
4232 #define MCF_SDRAMC_SDDS (*(vuint32*)(0xFC0B8100))
4233 #define MCF_SDRAMC_SDCS0 (*(vuint32*)(0xFC0B8110))
4234 #define MCF_SDRAMC_SDCS1 (*(vuint32*)(0xFC0B8114))
4235 #define MCF_SDRAMC_SDCS2 (*(vuint32*)(0xFC0B8118))
4236 #define MCF_SDRAMC_SDCS3 (*(vuint32*)(0xFC0B811C))
4237 #define MCF_SDRAMC_SDCS(x) (*(vuint32*)(0xFC0B8110+((x)*0x004)))
4238 
4239 /* Bit definitions and macros for MCF_SDRAMC_SDMR */
4240 #define MCF_SDRAMC_SDMR_CMD (0x00010000)
4241 #define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
4242 #define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30)
4243 #define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000)
4244 #define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
4245 
4246 /* Bit definitions and macros for MCF_SDRAMC_SDCR */
4247 #define MCF_SDRAMC_SDCR_IPALL (0x00000002)
4248 #define MCF_SDRAMC_SDCR_IREF (0x00000004)
4249 #define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8)
4250 #define MCF_SDRAMC_SDCR_PS(x) (((x)&0x00000003)<<12)
4251 #define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
4252 #define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
4253 #define MCF_SDRAMC_SDCR_REF (0x10000000)
4254 #define MCF_SDRAMC_SDCR_DDR (0x20000000)
4255 #define MCF_SDRAMC_SDCR_CKE (0x40000000)
4256 #define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
4257 #define MCF_SDRAMC_SDCR_PS_16 (0x00002000)
4258 #define MCF_SDRAMC_SDCR_PS_32 (0x00000000)
4259 
4260 /* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
4261 #define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
4262 #define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
4263 #define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
4264 #define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
4265 #define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
4266 #define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
4267 #define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
4268 
4269 /* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
4270 #define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
4271 #define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
4272 #define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
4273 #define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
4274 
4275 /* Bit definitions and macros for MCF_SDRAMC_SDDS */
4276 #define MCF_SDRAMC_SDDS_SB_D(x) (((x)&0x00000003)<<0)
4277 #define MCF_SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2)
4278 #define MCF_SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4)
4279 #define MCF_SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6)
4280 #define MCF_SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8)
4281 
4282 /* Bit definitions and macros for MCF_SDRAMC_SDCS */
4283 #define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)<<0)
4284 #define MCF_SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20)
4285 #define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
4286 #define MCF_SDRAMC_SDCS_CSSZ_DIABLE (0x00000000)
4287 #define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
4288 #define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
4289 #define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
4290 #define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
4291 #define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
4292 #define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
4293 #define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
4294 #define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
4295 #define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
4296 #define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
4297 #define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
4298 #define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
4299 #define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
4300 
4301 /*********************************************************************
4302 *
4303 * Synchronous Serial Interface (SSI)
4304 *
4305 *********************************************************************/
4306 
4307 /* Register read/write macros */
4308 #define MCF_SSI_TX0 (*(vuint32*)(0xFC0BC000))
4309 #define MCF_SSI_TX1 (*(vuint32*)(0xFC0BC004))
4310 #define MCF_SSI_RX0 (*(vuint32*)(0xFC0BC008))
4311 #define MCF_SSI_RX1 (*(vuint32*)(0xFC0BC00C))
4312 #define MCF_SSI_CR (*(vuint32*)(0xFC0BC010))
4313 #define MCF_SSI_ISR (*(vuint32*)(0xFC0BC014))
4314 #define MCF_SSI_IER (*(vuint32*)(0xFC0BC018))
4315 #define MCF_SSI_TCR (*(vuint32*)(0xFC0BC01C))
4316 #define MCF_SSI_RCR (*(vuint32*)(0xFC0BC020))
4317 #define MCF_SSI_CCR (*(vuint32*)(0xFC0BC024))
4318 #define MCF_SSI_FCSR (*(vuint32*)(0xFC0BC02C))
4319 #define MCF_SSI_ACR (*(vuint32*)(0xFC0BC038))
4320 #define MCF_SSI_ACADD (*(vuint32*)(0xFC0BC03C))
4321 #define MCF_SSI_ACDAT (*(vuint32*)(0xFC0BC040))
4322 #define MCF_SSI_ATAG (*(vuint32*)(0xFC0BC044))
4323 #define MCF_SSI_TMASK (*(vuint32*)(0xFC0BC048))
4324 #define MCF_SSI_RMASK (*(vuint32*)(0xFC0BC04C))
4325 
4326 /* Bit definitions and macros for MCF_SSI_TX */
4327 #define MCF_SSI_TX_SSI_TX(x) (((x)&0xFFFFFFFF)<<0)
4328 
4329 /* Bit definitions and macros for MCF_SSI_RX */
4330 #define MCF_SSI_RX_SSI_RX(x) (((x)&0xFFFFFFFF)<<0)
4331 
4332 /* Bit definitions and macros for MCF_SSI_CR */
4333 #define MCF_SSI_CR_SSI_EN (0x00000001)
4334 #define MCF_SSI_CR_TE (0x00000002)
4335 #define MCF_SSI_CR_RE (0x00000004)
4336 #define MCF_SSI_CR_NET (0x00000008)
4337 #define MCF_SSI_CR_SYN (0x00000010)
4338 #define MCF_SSI_CR_I2S(x) (((x)&0x00000003)<<5)
4339 #define MCF_SSI_CR_MCE (0x00000080)
4340 #define MCF_SSI_CR_TCH (0x00000100)
4341 #define MCF_SSI_CR_CIS (0x00000200)
4342 #define MCF_SSI_CR_I2S_NORMAL (0x00000000)
4343 #define MCF_SSI_CR_I2S_MASTER (0x00000020)
4344 #define MCF_SSI_CR_I2S_SLAVE (0x00000040)
4345 
4346 /* Bit definitions and macros for MCF_SSI_ISR */
4347 #define MCF_SSI_ISR_TFE0 (0x00000001)
4348 #define MCF_SSI_ISR_TFE1 (0x00000002)
4349 #define MCF_SSI_ISR_RFF0 (0x00000004)
4350 #define MCF_SSI_ISR_RFF1 (0x00000008)
4351 #define MCF_SSI_ISR_RLS (0x00000010)
4352 #define MCF_SSI_ISR_TLS (0x00000020)
4353 #define MCF_SSI_ISR_RFS (0x00000040)
4354 #define MCF_SSI_ISR_TFS (0x00000080)
4355 #define MCF_SSI_ISR_TUE0 (0x00000100)
4356 #define MCF_SSI_ISR_TUE1 (0x00000200)
4357 #define MCF_SSI_ISR_ROE0 (0x00000400)
4358 #define MCF_SSI_ISR_ROE1 (0x00000800)
4359 #define MCF_SSI_ISR_TDE0 (0x00001000)
4360 #define MCF_SSI_ISR_TDE1 (0x00002000)
4361 #define MCF_SSI_ISR_RDR0 (0x00004000)
4362 #define MCF_SSI_ISR_RDR1 (0x00008000)
4363 #define MCF_SSI_ISR_RXT (0x00010000)
4364 #define MCF_SSI_ISR_CMDDU (0x00020000)
4365 #define MCF_SSI_ISR_CMDAU (0x00040000)
4366 
4367 /* Bit definitions and macros for MCF_SSI_IER */
4368 #define MCF_SSI_IER_TFE0 (0x00000001)
4369 #define MCF_SSI_IER_TFE1 (0x00000002)
4370 #define MCF_SSI_IER_RFF0 (0x00000004)
4371 #define MCF_SSI_IER_RFF1 (0x00000008)
4372 #define MCF_SSI_IER_RLS (0x00000010)
4373 #define MCF_SSI_IER_TLS (0x00000020)
4374 #define MCF_SSI_IER_RFS (0x00000040)
4375 #define MCF_SSI_IER_TFS (0x00000080)
4376 #define MCF_SSI_IER_TUE0 (0x00000100)
4377 #define MCF_SSI_IER_TUE1 (0x00000200)
4378 #define MCF_SSI_IER_ROE0 (0x00000400)
4379 #define MCF_SSI_IER_ROE1 (0x00000800)
4380 #define MCF_SSI_IER_TDE0 (0x00001000)
4381 #define MCF_SSI_IER_TDE1 (0x00002000)
4382 #define MCF_SSI_IER_RDR0 (0x00004000)
4383 #define MCF_SSI_IER_RDR1 (0x00008000)
4384 #define MCF_SSI_IER_RXT (0x00010000)
4385 #define MCF_SSI_IER_CMDU (0x00020000)
4386 #define MCF_SSI_IER_CMDAU (0x00040000)
4387 #define MCF_SSI_IER_TIE (0x00080000)
4388 #define MCF_SSI_IER_TDMAE (0x00100000)
4389 #define MCF_SSI_IER_RIE (0x00200000)
4390 #define MCF_SSI_IER_RDMAE (0x00400000)
4391 
4392 /* Bit definitions and macros for MCF_SSI_TCR */
4393 #define MCF_SSI_TCR_TEFS (0x00000001)
4394 #define MCF_SSI_TCR_TFSL (0x00000002)
4395 #define MCF_SSI_TCR_TFSI (0x00000004)
4396 #define MCF_SSI_TCR_TSCKP (0x00000008)
4397 #define MCF_SSI_TCR_TSHFD (0x00000010)
4398 #define MCF_SSI_TCR_TXDIR (0x00000020)
4399 #define MCF_SSI_TCR_TFDIR (0x00000040)
4400 #define MCF_SSI_TCR_TFEN0 (0x00000080)
4401 #define MCF_SSI_TCR_TFEN1 (0x00000100)
4402 #define MCF_SSI_TCR_TXBIT0 (0x00000200)
4403 
4404 /* Bit definitions and macros for MCF_SSI_RCR */
4405 #define MCF_SSI_RCR_REFS (0x00000001)
4406 #define MCF_SSI_RCR_RFSL (0x00000002)
4407 #define MCF_SSI_RCR_RFSI (0x00000004)
4408 #define MCF_SSI_RCR_RSCKP (0x00000008)
4409 #define MCF_SSI_RCR_RSHFD (0x00000010)
4410 #define MCF_SSI_RCR_RFEN0 (0x00000080)
4411 #define MCF_SSI_RCR_RFEN1 (0x00000100)
4412 #define MCF_SSI_RCR_RXBIT0 (0x00000200)
4413 #define MCF_SSI_RCR_RXEXT (0x00000400)
4414 
4415 /* Bit definitions and macros for MCF_SSI_CCR */
4416 #define MCF_SSI_CCR_PM(x) (((x)&0x000000FF)<<0)
4417 #define MCF_SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
4418 #define MCF_SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
4419 #define MCF_SSI_CCR_PSR (0x00020000)
4420 #define MCF_SSI_CCR_DIV2 (0x00040000)
4421 
4422 /* Bit definitions and macros for MCF_SSI_FCSR */
4423 #define MCF_SSI_FCSR_TFWM0(x) (((x)&0x0000000F)<<0)
4424 #define MCF_SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
4425 #define MCF_SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
4426 #define MCF_SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
4427 #define MCF_SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
4428 #define MCF_SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
4429 #define MCF_SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
4430 #define MCF_SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
4431 
4432 /* Bit definitions and macros for MCF_SSI_ACR */
4433 #define MCF_SSI_ACR_AC97EN (0x00000001)
4434 #define MCF_SSI_ACR_FV (0x00000002)
4435 #define MCF_SSI_ACR_TIF (0x00000004)
4436 #define MCF_SSI_ACR_RD (0x00000008)
4437 #define MCF_SSI_ACR_WR (0x00000010)
4438 #define MCF_SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
4439 
4440 /* Bit definitions and macros for MCF_SSI_ACADD */
4441 #define MCF_SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF)<<0)
4442 
4443 /* Bit definitions and macros for MCF_SSI_ACDAT */
4444 #define MCF_SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF)<<0)
4445 
4446 /* Bit definitions and macros for MCF_SSI_ATAG */
4447 #define MCF_SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF)<<0)
4448 
4449 /* Bit definitions and macros for MCF_SSI_TMASK */
4450 #define MCF_SSI_TMASK_SSI_TMASK(x) (((x)&0xFFFFFFFF)<<0)
4451 
4452 /* Bit definitions and macros for MCF_SSI_RMASK */
4453 #define MCF_SSI_RMASK_SSI_RMASK(x) (((x)&0xFFFFFFFF)<<0)
4454 
4455 /*********************************************************************
4456 *
4457 * Phase Locked Loop (PLL)
4458 *
4459 *********************************************************************/
4460 
4461 /* Register read/write macros */
4462 #define MCF_PLL_PODR (*(vuint8 *)(0xFC0C0000))
4463 #define MCF_PLL_PLLCR (*(vuint8 *)(0xFC0C0004))
4464 #define MCF_PLL_PMDR (*(vuint8 *)(0xFC0C0008))
4465 #define MCF_PLL_PFDR (*(vuint8 *)(0xFC0C000C))
4466 
4467 /* Bit definitions and macros for MCF_PLL_PODR */
4468 #define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0)
4469 #define MCF_PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4)
4470 
4471 /* Bit definitions and macros for MCF_PLL_PLLCR */
4472 #define MCF_PLL_PLLCR_DITHDEV(x) (((x)&0x07)<<0)
4473 #define MCF_PLL_PLLCR_DITHEN (0x80)
4474 
4475 /* Bit definitions and macros for MCF_PLL_PMDR */
4476 #define MCF_PLL_PMDR_MODDIV(x) (((x)&0xFF)<<0)
4477 
4478 /* Bit definitions and macros for MCF_PLL_PFDR */
4479 #define MCF_PLL_PFDR_MFD(x) (((x)&0xFF)<<0)
4480 
4481 /********************************************************************/
4482 
4483 #endif /* __MCF532X_H__ */
Generated by   doxygen 1.8.15