RTEMS  5.1
mcf5235.h
1 /*
2  *******************************************
3  * Definitions from Motorola/FreeScale *
4  *******************************************
5  */
6 
7 /*
8  * File: mcf5235.h
9  * Purpose: MCF5235 definitions
10  *
11  * Notes:
12  */
13 
14 #ifndef _CPU_MCF5235_H
15 #define _CPU_MCF5235_H
16 
17 #include <stdint.h>
18 
19 /********************************************************************/
20 
21 /*
22  * File: mcf5xxx.h
23  * Purpose: Definitions common to all ColdFire processors
24  *
25  * Notes:
26  */
27 
28 #ifndef _CPU_MCF5XXX_H
29 #define _CPU_MCF5XXX_H
30 
31 /***********************************************************************/
32 /*
33  * The basic data types
34  */
35 
36 typedef unsigned char uint8; /* 8 bits */
37 typedef unsigned short int uint16; /* 16 bits */
38 typedef unsigned long int uint32; /* 32 bits */
39 
40 typedef signed char int8; /* 8 bits */
41 typedef signed short int int16; /* 16 bits */
42 typedef signed long int int32; /* 32 bits */
43 
44 typedef volatile uint8 vuint8; /* 8 bits */
45 typedef volatile uint16 vuint16; /* 16 bits */
46 typedef volatile uint32 vuint32; /* 32 bits */
47 
48 /***********************************************************************/
49 /*
50  * Common M68K & ColdFire definitions
51  *
52  ***********************************************************************/
53 
54 #define ADDRESS uint32
55 #define INSTRUCTION uint16
56 #define ILLEGAL 0x4AFC
57 #define CPU_WORD_SIZE 16
58 
59 #define MCF5XXX_SR_T (0x8000)
60 #define MCF5XXX_SR_S (0x2000)
61 #define MCF5XXX_SR_M (0x1000)
62 #define MCF5XXX_SR_IPL (0x0700)
63 #define MCF5XXX_SR_IPL_0 (0x0000)
64 #define MCF5XXX_SR_IPL_1 (0x0100)
65 #define MCF5XXX_SR_IPL_2 (0x0200)
66 #define MCF5XXX_SR_IPL_3 (0x0300)
67 #define MCF5XXX_SR_IPL_4 (0x0400)
68 #define MCF5XXX_SR_IPL_5 (0x0500)
69 #define MCF5XXX_SR_IPL_6 (0x0600)
70 #define MCF5XXX_SR_IPL_7 (0x0700)
71 #define MCF5XXX_SR_X (0x0010)
72 #define MCF5XXX_SR_N (0x0008)
73 #define MCF5XXX_SR_Z (0x0004)
74 #define MCF5XXX_SR_V (0x0002)
75 #define MCF5XXX_SR_C (0x0001)
76 
77 #define MCF5XXX_CACR_CENB (0x80000000)
78 #define MCF5XXX_CACR_CPDI (0x10000000)
79 #define MCF5XXX_CACR_CPD (0x10000000)
80 #define MCF5XXX_CACR_CFRZ (0x08000000)
81 #define MCF5XXX_CACR_CINV (0x01000000)
82 #define MCF5XXX_CACR_DIDI (0x00800000)
83 #define MCF5XXX_CACR_DISD (0x00400000)
84 #define MCF5XXX_CACR_INVI (0x00200000)
85 #define MCF5XXX_CACR_INVD (0x00100000)
86 #define MCF5XXX_CACR_CEIB (0x00000400)
87 #define MCF5XXX_CACR_DCM_WR (0x00000000)
88 #define MCF5XXX_CACR_DCM_CB (0x00000100)
89 #define MCF5XXX_CACR_DCM_IP (0x00000200)
90 #define MCF5XXX_CACR_DCM (0x00000200)
91 #define MCF5XXX_CACR_DCM_II (0x00000300)
92 #define MCF5XXX_CACR_DBWE (0x00000100)
93 #define MCF5XXX_CACR_DWP (0x00000020)
94 #define MCF5XXX_CACR_EUST (0x00000010)
95 #define MCF5XXX_CACR_CLNF_00 (0x00000000)
96 #define MCF5XXX_CACR_CLNF_01 (0x00000002)
97 #define MCF5XXX_CACR_CLNF_10 (0x00000004)
98 #define MCF5XXX_CACR_CLNF_11 (0x00000006)
99 
100 #define MCF5XXX_ACR_AB(a) ((a)&0xFF000000)
101 #define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8)
102 #define MCF5XXX_ACR_EN (0x00008000)
103 #define MCF5XXX_ACR_SM_USER (0x00000000)
104 #define MCF5XXX_ACR_SM_SUPER (0x00002000)
105 #define MCF5XXX_ACR_SM_IGNORE (0x00006000)
106 #define MCF5XXX_ACR_ENIB (0x00000080)
107 #define MCF5XXX_ACR_CM (0x00000040)
108 #define MCF5XXX_ACR_DCM_WR (0x00000000)
109 #define MCF5XXX_ACR_DCM_CB (0x00000020)
110 #define MCF5XXX_ACR_DCM_IP (0x00000040)
111 #define MCF5XXX_ACR_DCM_II (0x00000060)
112 #define MCF5XXX_ACR_CM (0x00000040)
113 #define MCF5XXX_ACR_BWE (0x00000020)
114 #define MCF5XXX_ACR_WP (0x00000004)
115 
116 #define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000)
117 #define MCF5XXX_RAMBAR_PRI_00 (0x00000000)
118 #define MCF5XXX_RAMBAR_PRI_01 (0x00004000)
119 #define MCF5XXX_RAMBAR_PRI_10 (0x00008000)
120 #define MCF5XXX_RAMBAR_PRI_11 (0x0000C000)
121 #define MCF5XXX_RAMBAR_WP (0x00000100)
122 #define MCF5XXX_RAMBAR_CI (0x00000020)
123 #define MCF5XXX_RAMBAR_SC (0x00000010)
124 #define MCF5XXX_RAMBAR_SD (0x00000008)
125 #define MCF5XXX_RAMBAR_UC (0x00000004)
126 #define MCF5XXX_RAMBAR_UD (0x00000002)
127 #define MCF5XXX_RAMBAR_V (0x00000001)
128 
129 /***********************************************************************/
130 /*
131  * The ColdFire family of processors has a simplified exception stack
132  * frame that looks like the following:
133  *
134  * 3322222222221111 111111
135  * 1098765432109876 5432109876543210
136  * 8 +----------------+----------------+
137  * | Program Counter |
138  * 4 +----------------+----------------+
139  * |FS/Fmt/Vector/FS| SR |
140  * SP --> 0 +----------------+----------------+
141  *
142  * The stack self-aligns to a 4-byte boundary at an exception, with
143  * the FS/Fmt/Vector/FS field indicating the size of the adjustment
144  * (SP += 0,1,2,3 bytes).
145  */
146 
147 #define MCF5XXX_RD_SF_FORMAT(PTR) \
148  ((*((uint16 *)(PTR)) >> 12) & 0x00FF)
149 
150 #define MCF5XXX_RD_SF_VECTOR(PTR) \
151  ((*((uint16 *)(PTR)) >> 2) & 0x00FF)
152 
153 #define MCF5XXX_RD_SF_FS(PTR) \
154  ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )
155 
156 #define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1)
157 #define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1)
158 
159 /********************************************************************/
160 /*
161  * Functions provided by mcf5xxx.s
162  */
163 
164 int asm_set_ipl (uint32);
165 void mcf5xxx_wr_cacr (uint32);
166 void mcf5xxx_wr_acr0 (uint32);
167 void mcf5xxx_wr_acr1 (uint32);
168 void mcf5xxx_wr_acr2 (uint32);
169 void mcf5xxx_wr_acr3 (uint32);
170 void mcf5xxx_wr_other_a7 (uint32);
171 void mcf5xxx_wr_other_sp (uint32);
172 void mcf5xxx_wr_vbr (uint32);
173 void mcf5xxx_wr_macsr (uint32);
174 void mcf5xxx_wr_mask (uint32);
175 void mcf5xxx_wr_acc0 (uint32);
176 void mcf5xxx_wr_accext01 (uint32);
177 void mcf5xxx_wr_accext23 (uint32);
178 void mcf5xxx_wr_acc1 (uint32);
179 void mcf5xxx_wr_acc2 (uint32);
180 void mcf5xxx_wr_acc3 (uint32);
181 void mcf5xxx_wr_sr (uint32);
182 void mcf5xxx_wr_rambar0 (uint32);
183 void mcf5xxx_wr_rambar1 (uint32);
184 void mcf5xxx_wr_mbar (uint32);
185 void mcf5xxx_wr_mbar0 (uint32);
186 void mcf5xxx_wr_mbar1 (uint32);
187 
188 /********************************************************************/
189 
190 #endif /* _CPU_MCF5XXX_H */
191 
192 
193 /********************************************************************/
194 /*
195  * Memory map definitions from linker command files
196  */
197 extern char __IPSBAR[];
198 
199 /*********************************************************************
200 *
201 * Watchdog Timer Modules (WTM)
202 *
203 *********************************************************************/
204 
205 /* Register read/write macros */
206 #define MCF5235_WCR (*(vuint16*)((uintptr_t)__IPSBAR + (0x140000)))
207 #define MCF5235_WMR (*(vuint16*)((uintptr_t)__IPSBAR + (0x140002)))
208 #define MCF5235_WCNTR (*(vuint16*)((uintptr_t)__IPSBAR + (0x140004)))
209 #define MCF5235_WSR (*(vuint16*)((uintptr_t)__IPSBAR + (0x140006)))
210 
211 /* Bit definitions and macros for MCF5235_WTM_WCR */
212 #define MCF5235_WCR_EN (0x0001)
213 #define MCF5235_WCR_HALTED (0x0002)
214 #define MCF5235_WCR_DOZE (0x0004)
215 #define MCF5235_WCR_WAIT (0x0008)
216 
217 /* Bit definitions and macros for MCF5235_WTM_WMR */
218 #define MCF5235_WMR_WM0 (0x0001)
219 #define MCF5235_WMR_WM1 (0x0002)
220 #define MCF5235_WMR_WM2 (0x0004)
221 #define MCF5235_WMR_WM3 (0x0008)
222 #define MCF5235_WMR_WM4 (0x0010)
223 #define MCF5235_WMR_WM5 (0x0020)
224 #define MCF5235_WMR_WM6 (0x0040)
225 #define MCF5235_WMR_WM7 (0x0080)
226 #define MCF5235_WMR_WM8 (0x0100)
227 #define MCF5235_WMR_WM9 (0x0200)
228 #define MCF5235_WMR_WM10 (0x0400)
229 #define MCF5235_WMR_WM11 (0x0800)
230 #define MCF5235_WMR_WM12 (0x1000)
231 #define MCF5235_WMR_WM13 (0x2000)
232 #define MCF5235_WMR_WM14 (0x4000)
233 #define MCF5235_WMR_WM15 (0x8000)
234 
235 /* Bit definitions and macros for MCF5235_WTM_WCNTR */
236 #define MCF5235_WCNTR_WC0 (0x0001)
237 #define MCF5235_WCNTR_WC1 (0x0002)
238 #define MCF5235_WCNTR_WC2 (0x0004)
239 #define MCF5235_WCNTR_WC3 (0x0008)
240 #define MCF5235_WCNTR_WC4 (0x0010)
241 #define MCF5235_WCNTR_WC5 (0x0020)
242 #define MCF5235_WCNTR_WC6 (0x0040)
243 #define MCF5235_WCNTR_WC7 (0x0080)
244 #define MCF5235_WCNTR_WC8 (0x0100)
245 #define MCF5235_WCNTR_WC9 (0x0200)
246 #define MCF5235_WCNTR_WC10 (0x0400)
247 #define MCF5235_WCNTR_WC11 (0x0800)
248 #define MCF5235_WCNTR_WC12 (0x1000)
249 #define MCF5235_WCNTR_WC13 (0x2000)
250 #define MCF5235_WCNTR_WC14 (0x4000)
251 #define MCF5235_WCNTR_WC15 (0x8000)
252 #define MCF5235_WSR_WS0 (0x0001)
253 #define MCF5235_WSR_WS1 (0x0002)
254 #define MCF5235_WSR_WS2 (0x0004)
255 #define MCF5235_WSR_WS3 (0x0008)
256 #define MCF5235_WSR_WS4 (0x0010)
257 #define MCF5235_WSR_WS5 (0x0020)
258 #define MCF5235_WSR_WS6 (0x0040)
259 #define MCF5235_WSR_WS7 (0x0080)
260 #define MCF5235_WSR_WS8 (0x0100)
261 #define MCF5235_WSR_WS9 (0x0200)
262 #define MCF5235_WSR_WS10 (0x0400)
263 #define MCF5235_WSR_WS11 (0x0800)
264 #define MCF5235_WSR_WS12 (0x1000)
265 #define MCF5235_WSR_WS13 (0x2000)
266 #define MCF5235_WSR_WS14 (0x4000)
267 #define MCF5235_WSR_WS15 (0x8000)
268 
269 /********************************************************************/
270 
271 /*********************************************************************
272 *
273 * Universal Asynchronous Receiver Transmitter (UART)
274 *
275 *********************************************************************/
276 
277 /* Register read/write macros */
278 #define MCF5235_UART_UMR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000200)))
279 #define MCF5235_UART_USR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000204)))
280 #define MCF5235_UART_UCSR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000204)))
281 #define MCF5235_UART_UCR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000208)))
282 #define MCF5235_UART_URB0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00020C)))
283 #define MCF5235_UART_UTB0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00020C)))
284 #define MCF5235_UART_UIPCR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000210)))
285 #define MCF5235_UART_UACR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000210)))
286 #define MCF5235_UART_UISR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000214)))
287 #define MCF5235_UART_UIMR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000214)))
288 #define MCF5235_UART_UBG10 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000218)))
289 #define MCF5235_UART_UBG20 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00021C)))
290 #define MCF5235_UART_UIP0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000234)))
291 #define MCF5235_UART_UOP10 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000238)))
292 #define MCF5235_UART_UOP00 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00023C)))
293 #define MCF5235_UART_UMR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000240)))
294 #define MCF5235_UART_USR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000244)))
295 #define MCF5235_UART_UCSR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000244)))
296 #define MCF5235_UART_UCR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000248)))
297 #define MCF5235_UART_URB1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00024C)))
298 #define MCF5235_UART_UTB1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00024C)))
299 #define MCF5235_UART_UIPCR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000250)))
300 #define MCF5235_UART_UACR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000250)))
301 #define MCF5235_UART_UISR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000254)))
302 #define MCF5235_UART_UIMR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000254)))
303 #define MCF5235_UART_UBG11 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000258)))
304 #define MCF5235_UART_UBG21 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00025C)))
305 #define MCF5235_UART_UIP1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000274)))
306 #define MCF5235_UART_UOP11 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000278)))
307 #define MCF5235_UART_UOP01 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00027C)))
308 #define MCF5235_UART_UMR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000280)))
309 #define MCF5235_UART_USR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000284)))
310 #define MCF5235_UART_UCSR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000284)))
311 #define MCF5235_UART_UCR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000288)))
312 #define MCF5235_UART_URB2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00028C)))
313 #define MCF5235_UART_UTB2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00028C)))
314 #define MCF5235_UART_UIPCR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000290)))
315 #define MCF5235_UART_UACR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000290)))
316 #define MCF5235_UART_UISR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000294)))
317 #define MCF5235_UART_UIMR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000294)))
318 #define MCF5235_UART_UBG12 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000298)))
319 #define MCF5235_UART_UBG22 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00029C)))
320 #define MCF5235_UART_UIP2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0002B4)))
321 #define MCF5235_UART_UOP12 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0002B8)))
322 #define MCF5235_UART_UOP02 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0002BC)))
323 #define MCF5235_UART_UMR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000200+((x)*0x040))))
324 #define MCF5235_UART_USR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000204+((x)*0x040))))
325 #define MCF5235_UART_UCSR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000204+((x)*0x040))))
326 #define MCF5235_UART_UCR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000208+((x)*0x040))))
327 #define MCF5235_UART_URB(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00020C+((x)*0x040))))
328 #define MCF5235_UART_UTB(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00020C+((x)*0x040))))
329 #define MCF5235_UART_UIPCR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000210+((x)*0x040))))
330 #define MCF5235_UART_UACR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000210+((x)*0x040))))
331 #define MCF5235_UART_UISR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000214+((x)*0x040))))
332 #define MCF5235_UART_UIMR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000214+((x)*0x040))))
333 #define MCF5235_UART_UBG1(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000218+((x)*0x040))))
334 #define MCF5235_UART_UBG2(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00021C+((x)*0x040))))
335 #define MCF5235_UART_UIP(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000234+((x)*0x040))))
336 #define MCF5235_UART_UOP1(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000238+((x)*0x040))))
337 #define MCF5235_UART_UOP0(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00023C+((x)*0x040))))
338 
339 /* Bit definitions and macros for MCF5235_UART_UMR */
340 #define MCF5235_UART_UMR_BC(x) (((x)&0x03)<<0)
341 #define MCF5235_UART_UMR_PT (0x04)
342 #define MCF5235_UART_UMR_PM(x) (((x)&0x03)<<3)
343 #define MCF5235_UART_UMR_ERR (0x20)
344 #define MCF5235_UART_UMR_RXIRQ (0x40)
345 #define MCF5235_UART_UMR_RXRTS (0x80)
346 #define MCF5235_UART_UMR_SB(x) (((x)&0x0F)<<0)
347 #define MCF5235_UART_UMR_TXCTS (0x10)
348 #define MCF5235_UART_UMR_TXRTS (0x20)
349 #define MCF5235_UART_UMR_CM(x) (((x)&0x03)<<6)
350 #define MCF5235_UART_UMR_PM_MULTI_ADDR (0x1C)
351 #define MCF5235_UART_UMR_PM_MULTI_DATA (0x18)
352 #define MCF5235_UART_UMR_PM_NONE (0x10)
353 #define MCF5235_UART_UMR_PM_FORCE_HI (0x0C)
354 #define MCF5235_UART_UMR_PM_FORCE_LO (0x08)
355 #define MCF5235_UART_UMR_PM_ODD (0x04)
356 #define MCF5235_UART_UMR_PM_EVEN (0x00)
357 #define MCF5235_UART_UMR_BC_5 (0x00)
358 #define MCF5235_UART_UMR_BC_6 (0x01)
359 #define MCF5235_UART_UMR_BC_7 (0x02)
360 #define MCF5235_UART_UMR_BC_8 (0x03)
361 #define MCF5235_UART_UMR_CM_NORMAL (0x00)
362 #define MCF5235_UART_UMR_CM_ECHO (0x40)
363 #define MCF5235_UART_UMR_CM_LOCAL_LOOP (0x80)
364 #define MCF5235_UART_UMR_CM_REMOTE_LOOP (0xC0)
365 #define MCF5235_UART_UMR_STOP_BITS_1 (0x07)
366 #define MCF5235_UART_UMR_STOP_BITS_15 (0x08)
367 #define MCF5235_UART_UMR_STOP_BITS_2 (0x0F)
368 #define MCF5235_UART_USR_RXRDY (0x01)
369 #define MCF5235_UART_USR_FFULL (0x02)
370 #define MCF5235_UART_USR_TXRDY (0x04)
371 #define MCF5235_UART_USR_TXEMP (0x08)
372 #define MCF5235_UART_USR_OE (0x10)
373 #define MCF5235_UART_USR_PE (0x20)
374 #define MCF5235_UART_USR_FE (0x40)
375 #define MCF5235_UART_USR_RB (0x80)
376 #define MCF5235_UART_UCSR_TCS(x) (((x)&0x0F)<<0)
377 #define MCF5235_UART_UCSR_RCS(x) (((x)&0x0F)<<4)
378 #define MCF5235_UART_UCSR_RCS_SYS_CLK (0xD0)
379 #define MCF5235_UART_UCSR_RCS_CTM16 (0xE0)
380 #define MCF5235_UART_UCSR_RCS_CTM (0xF0)
381 #define MCF5235_UART_UCSR_TCS_SYS_CLK (0x0D)
382 #define MCF5235_UART_UCSR_TCS_CTM16 (0x0E)
383 #define MCF5235_UART_UCSR_TCS_CTM (0x0F)
384 #define MCF5235_UART_UCR_RXC(x) (((x)&0x03)<<0)
385 #define MCF5235_UART_UCR_TXC(x) (((x)&0x03)<<2)
386 #define MCF5235_UART_UCR_MISC(x) (((x)&0x07)<<4)
387 #define MCF5235_UART_UCR_NONE (0x00)
388 #define MCF5235_UART_UCR_STOP_BREAK (0x70)
389 #define MCF5235_UART_UCR_START_BREAK (0x60)
390 #define MCF5235_UART_UCR_BKCHGINT (0x50)
391 #define MCF5235_UART_UCR_RESET_ERROR (0x40)
392 #define MCF5235_UART_UCR_RESET_TX (0x30)
393 #define MCF5235_UART_UCR_RESET_RX (0x20)
394 #define MCF5235_UART_UCR_RESET_MR (0x10)
395 #define MCF5235_UART_UCR_TX_DISABLED (0x08)
396 #define MCF5235_UART_UCR_TX_ENABLED (0x04)
397 #define MCF5235_UART_UCR_RX_DISABLED (0x02)
398 #define MCF5235_UART_UCR_RX_ENABLED (0x01)
399 #define MCF5235_UART_UIPCR_CTS (0x01)
400 #define MCF5235_UART_UIPCR_COS (0x10)
401 #define MCF5235_UART_UACR_IEC (0x01)
402 #define MCF5235_UART_UISR_TXRDY (0x01)
403 #define MCF5235_UART_UISR_RXRDY (0x02)
404 #define MCF5235_UART_UISR_DB (0x04)
405 #define MCF5235_UART_UISR_RXFTO (0x08)
406 #define MCF5235_UART_UISR_TXFIFO (0x10)
407 #define MCF5235_UART_UISR_RXFIFO (0x20)
408 #define MCF5235_UART_UISR_COS (0x80)
409 #define MCF5235_UART_UIMR_TXRDY (0x01)
410 #define MCF5235_UART_UIMR_FFULL (0x02)
411 #define MCF5235_UART_UIMR_DB (0x04)
412 #define MCF5235_UART_UIMR_COS (0x80)
413 #define MCF5235_UART_UIP_CTS (0x01)
414 #define MCF5235_UART_UOP1_RTS (0x01)
415 #define MCF5235_UART_UOP0_RTS (0x01)
416 
417 
418 /*********************************************************************
419 *
420 * SDRAM Controller (SDRAMC)
421 *
422 *********************************************************************/
423 
424 /* Register read/write macros */
425 #define MCF5235_SDRAMC_DCR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000040)))
426 #define MCF5235_SDRAMC_DACR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000048)))
427 #define MCF5235_SDRAMC_DMR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00004C)))
428 #define MCF5235_SDRAMC_DACR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000050)))
429 #define MCF5235_SDRAMC_DMR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000054)))
430 
431 /* Bit definitions and macros for MCF5235_SDRAMC_DCR */
432 #define MCF5235_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0)
433 #define MCF5235_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9)
434 #define MCF5235_SDRAMC_DCR_IS (0x0800)
435 #define MCF5235_SDRAMC_DCR_COC (0x1000)
436 #define MCF5235_SDRAMC_DCR_NAM (0x2000)
437 #define MCF5235_SDRAMC_DACR0_IP (0x00000008)
438 #define MCF5235_SDRAMC_DACR0_PS(x) (((x)&0x00000003)<<4)
439 #define MCF5235_SDRAMC_DACR0_MRS (0x00000040)
440 #define MCF5235_SDRAMC_DACR0_CBM(x) (((x)&0x00000007)<<8)
441 #define MCF5235_SDRAMC_DACR0_CASL(x) (((x)&0x00000003)<<12)
442 #define MCF5235_SDRAMC_DACR0_RE (0x00008000)
443 #define MCF5235_SDRAMC_DACR0_BA(x) (((x)&0x00003FFF)<<18)
444 #define MCF5235_SDRAMC_DMR0_V (0x00000001)
445 #define MCF5235_SDRAMC_DMR0_WP (0x00000100)
446 #define MCF5235_SDRAMC_DMR0_BAM(x) (((x)&0x00003FFF)<<18)
447 #define MCF5235_SDRAMC_DACR1_IP (0x00000008)
448 #define MCF5235_SDRAMC_DACR1_PS(x) (((x)&0x00000003)<<4)
449 #define MCF5235_SDRAMC_DACR1_MRS (0x00000040)
450 #define MCF5235_SDRAMC_DACR1_CBM(x) (((x)&0x00000007)<<8)
451 #define MCF5235_SDRAMC_DACR1_CASL(x) (((x)&0x00000003)<<12)
452 #define MCF5235_SDRAMC_DACR1_RE (0x00008000)
453 #define MCF5235_SDRAMC_DACR1_BA(x) (((x)&0x00003FFF)<<18)
454 #define MCF5235_SDRAMC_DMR1_V (0x00000001)
455 #define MCF5235_SDRAMC_DMR1_WP (0x00000100)
456 #define MCF5235_SDRAMC_DMR1_BAM(x) (((x)&0x00003FFF)<<18)
457 #define MCF5235_SDRAMC_DMR_BAM_4G (0xFFFC0000)
458 #define MCF5235_SDRAMC_DMR_BAM_2G (0x7FFC0000)
459 #define MCF5235_SDRAMC_DMR_BAM_1G (0x3FFC0000)
460 #define MCF5235_SDRAMC_DMR_BAM_1024M (0x3FFC0000)
461 #define MCF5235_SDRAMC_DMR_BAM_512M (0x1FFC0000)
462 #define MCF5235_SDRAMC_DMR_BAM_256M (0x0FFC0000)
463 #define MCF5235_SDRAMC_DMR_BAM_128M (0x07FC0000)
464 #define MCF5235_SDRAMC_DMR_BAM_64M (0x03FC0000)
465 #define MCF5235_SDRAMC_DMR_BAM_32M (0x01FC0000)
466 #define MCF5235_SDRAMC_DMR_BAM_16M (0x00FC0000)
467 #define MCF5235_SDRAMC_DMR_BAM_8M (0x007C0000)
468 #define MCF5235_SDRAMC_DMR_BAM_4M (0x003C0000)
469 #define MCF5235_SDRAMC_DMR_BAM_2M (0x001C0000)
470 #define MCF5235_SDRAMC_DMR_BAM_1M (0x000C0000)
471 #define MCF5235_SDRAMC_DMR_BAM_1024K (0x000C0000)
472 #define MCF5235_SDRAMC_DMR_BAM_512K (0x00040000)
473 #define MCF5235_SDRAMC_DMR_BAM_256K (0x00000000)
474 #define MCF5235_SDRAMC_DMR_WP (0x00000100)
475 #define MCF5235_SDRAMC_DMR_CI (0x00000040)
476 #define MCF5235_SDRAMC_DMR_AM (0x00000020)
477 #define MCF5235_SDRAMC_DMR_SC (0x00000010)
478 #define MCF5235_SDRAMC_DMR_SD (0x00000008)
479 #define MCF5235_SDRAMC_DMR_UC (0x00000004)
480 #define MCF5235_SDRAMC_DMR_UD (0x00000002)
481 #define MCF5235_SDRAMC_DMR_V (0x00000001)
482 
483 /*********************************************************************
484 *
485 * DMA Timers (TIMER)
486 *
487 *********************************************************************/
488 
489 /* Register read/write macros */
490 #define MCF5235_TIMER_DTMR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000400)))
491 #define MCF5235_TIMER_DTXMR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000402)))
492 #define MCF5235_TIMER_DTER0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000403)))
493 #define MCF5235_TIMER_DTRR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000404)))
494 #define MCF5235_TIMER_DTCR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000408)))
495 #define MCF5235_TIMER_DTCN0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00040C)))
496 #define MCF5235_TIMER_DTMR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000440)))
497 #define MCF5235_TIMER_DTXMR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000442)))
498 #define MCF5235_TIMER_DTER1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000443)))
499 #define MCF5235_TIMER_DTRR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000444)))
500 #define MCF5235_TIMER_DTCR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000448)))
501 #define MCF5235_TIMER_DTCN1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00044C)))
502 #define MCF5235_TIMER_DTMR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000480)))
503 #define MCF5235_TIMER_DTXMR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000482)))
504 #define MCF5235_TIMER_DTER2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000483)))
505 #define MCF5235_TIMER_DTRR2 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000484)))
506 #define MCF5235_TIMER_DTCR2 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000488)))
507 #define MCF5235_TIMER_DTCN2 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00048C)))
508 #define MCF5235_TIMER3_DTMR (*(vuint16*)((uintptr_t)__IPSBAR + (0x0004C0)))
509 #define MCF5235_TIMER_DTXMR3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0004C2)))
510 #define MCF5235_TIMER_DTER3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0004C3)))
511 #define MCF5235_TIMER_DTRR3 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0004C4)))
512 #define MCF5235_TIMER_DTCR3 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0004C8)))
513 #define MCF5235_TIMER3_DTCN (*(vuint32*)((uintptr_t)__IPSBAR + (0x0004CC)))
514 #define MCF5235_TIMER_DTMR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x000400+((x)*0x040))))
515 #define MCF5235_TIMER_DTXMR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000402+((x)*0x040))))
516 #define MCF5235_TIMER_DTER(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000403+((x)*0x040))))
517 #define MCF5235_TIMER_DTRR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x000404+((x)*0x040))))
518 #define MCF5235_TIMER_DTCR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x000408+((x)*0x040))))
519 #define MCF5235_TIMER_DTCN(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x00040C+((x)*0x040))))
520 
521 /* Bit definitions and macros for MCF5235_TIMER_DTMR */
522 #define MCF5235_TIMER_DTMR_RST (0x0001)
523 #define MCF5235_TIMER_DTMR_CLK(x) (((x)&0x0003)<<1)
524 #define MCF5235_TIMER_DTMR_FRR (0x0008)
525 #define MCF5235_TIMER_DTMR_ORRI (0x0010)
526 #define MCF5235_TIMER_DTMR_OM (0x0020)
527 #define MCF5235_TIMER_DTMR_CE(x) (((x)&0x0003)<<6)
528 #define MCF5235_TIMER_DTMR_PS(x) (((x)&0x00FF)<<8)
529 #define MCF5235_TIMER_DTMR_CE_ANY (0x00C0)
530 #define MCF5235_TIMER_DTMR_CE_FALL (0x0080)
531 #define MCF5235_TIMER_DTMR_CE_RISE (0x0040)
532 #define MCF5235_TIMER_DTMR_CE_NONE (0x0000)
533 #define MCF5235_TIMER_DTMR_CLK_DTIN (0x0006)
534 #define MCF5235_TIMER_DTMR_CLK_DIV16 (0x0004)
535 #define MCF5235_TIMER_DTMR_CLK_DIV1 (0x0002)
536 #define MCF5235_TIMER_DTMR_CLK_STOP (0x0000)
537 #define MCF5235_TIMER_DTXMR_MODE16 (0x01)
538 #define MCF5235_TIMER_DTXMR_DMAEN (0x80)
539 #define MCF5235_TIMER_DTER_CAP (0x01)
540 #define MCF5235_TIMER_DTER_REF (0x02)
541 
542 /*********************************************************************
543 *
544 * System SRAM (SRAM)
545 *
546 *********************************************************************/
547 
548 /* Register read/write macros */
549 #define MCF5235_SRAM_RAMBAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x20000000)))
550 
551 /* Bit definitions and macros for MCF5235_SRAM_RAMBAR */
552 #define MCF5235_SRAM_RAMBAR_V (0x00000001)
553 #define MCF5235_SRAM_RAMBAR_UD (0x00000002)
554 #define MCF5235_SRAM_RAMBAR_UC (0x00000004)
555 #define MCF5235_SRAM_RAMBAR_SD (0x00000008)
556 #define MCF5235_SRAM_RAMBAR_SC (0x00000010)
557 #define MCF5235_SRAM_RAMBAR_CI (0x00000020)
558 #define MCF5235_SRAM_RAMBAR_WP (0x00000100)
559 #define MCF5235_SRAM_RAMBAR_SPV (0x00000200)
560 #define MCF5235_SRAM_RAMBAR_PRI2 (0x00000400)
561 #define MCF5235_SRAM_RAMBAR_PRI1 (0x00000800)
562 #define MCF5235_SRAM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16)
563 
564 /*********************************************************************
565 *
566 * System Control Module (SCM)
567 *
568 *********************************************************************/
569 
570 /* Register read/write macros */
571 #define MCF5235_SCM_IPSBAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x000000)))
572 #define MCF5235_SCM_RAMBAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x000008)))
573 #define MCF5235_SCM_CRSR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000010)))
574 #define MCF5235_SCM_CWCR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000011)))
575 #define MCF5235_SCM_LPICR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000012)))
576 #define MCF5235_SCM_CWSR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000013)))
577 #define MCF5235_SCM_DMAREQC (*(vuint32*)((uintptr_t)__IPSBAR + (0x000014)))
578 #define MCF5235_SCM_MPARK (*(vuint32*)((uintptr_t)__IPSBAR + (0x00001C)))
579 #define MCF5235_SCM_MPR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000020)))
580 #define MCF5235_SCM_PACR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000024)))
581 #define MCF5235_SCM_PACR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000025)))
582 #define MCF5235_SCM_PACR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000026)))
583 #define MCF5235_SCM_PACR3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000027)))
584 #define MCF5235_SCM_PACR4 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000028)))
585 #define MCF5235_SCM_PACR5 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00002A)))
586 #define MCF5235_SCM_PACR6 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00002B)))
587 #define MCF5235_SCM_PACR7 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00002C)))
588 #define MCF5235_SCM_PACR8 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00002E)))
589 #define MCF5235_SCM_GPACR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000030)))
590 
591 /* Bit definitions */
592 #define MCF5235_SCM_IPSBAR_V (0x00000001)
593 #define MCF5235_SCM_IPSBAR_BA(x) (((x)&0x00000003)<<30)
594 #define MCF5235_SCM_RAMBAR_BDE (0x00000200)
595 #define MCF5235_SCM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16)
596 #define MCF5235_SCM_CRSR_CWDR (0x20)
597 #define MCF5235_SCM_CRSR_EXT (0x80)
598 #define MCF5235_SCM_CWCR_CWTIC (0x01)
599 #define MCF5235_SCM_CWCR_CWTAVAL (0x02)
600 #define MCF5235_SCM_CWCR_CWTA (0x04)
601 #define MCF5235_SCM_CWCR_CWT(x) (((x)&0x07)<<3)
602 #define MCF5235_SCM_CWCR_CWRI (0x40)
603 #define MCF5235_SCM_CWCR_CWE (0x80)
604 #define MCF5235_SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4)
605 #define MCF5235_SCM_LPICR_ENBSTOP (0x80)
606 #define MCF5235_SCM_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0)
607 #define MCF5235_SCM_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4)
608 #define MCF5235_SCM_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8)
609 #define MCF5235_SCM_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12)
610 #define MCF5235_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8)
611 #define MCF5235_SCM_MPARK_PRKLAST (0x00001000)
612 #define MCF5235_SCM_MPARK_TIMEOUT (0x00002000)
613 #define MCF5235_SCM_MPARK_FIXED (0x00004000)
614 #define MCF5235_SCM_MPARK_M1_PRTY(x) (((x)&0x00000003)<<16)
615 #define MCF5235_SCM_MPARK_M0_PRTY(x) (((x)&0x00000003)<<18)
616 #define MCF5235_SCM_MPARK_M2_PRTY(x) (((x)&0x00000003)<<20)
617 #define MCF5235_SCM_MPARK_M3_PRTY(x) (((x)&0x00000003)<<22)
618 #define MCF5235_SCM_MPARK_BCR24BIT (0x01000000)
619 #define MCF5235_SCM_MPARK_M2_P_EN (0x02000000)
620 #define MCF5235_SCM_MPR_MPR(x) (((x)&0x0F)<<0)
621 #define MCF5235_SCM_PACR0_ACCESS_CTRL0(x) (((x)&0x07)<<0)
622 #define MCF5235_SCM_PACR0_LOCK0 (0x08)
623 #define MCF5235_SCM_PACR0_ACCESS_CTRL1(x) (((x)&0x07)<<4)
624 #define MCF5235_SCM_PACR0_LOCK1 (0x80)
625 #define MCF5235_SCM_PACR1_ACCESS_CTRL0(x) (((x)&0x07)<<0)
626 #define MCF5235_SCM_PACR1_LOCK0 (0x08)
627 #define MCF5235_SCM_PACR1_ACCESS_CTRL1(x) (((x)&0x07)<<4)
628 #define MCF5235_SCM_PACR1_LOCK1 (0x80)
629 #define MCF5235_SCM_PACR2_ACCESS_CTRL0(x) (((x)&0x07)<<0)
630 #define MCF5235_SCM_PACR2_LOCK0 (0x08)
631 #define MCF5235_SCM_PACR2_ACCESS_CTRL1(x) (((x)&0x07)<<4)
632 #define MCF5235_SCM_PACR2_LOCK1 (0x80)
633 #define MCF5235_SCM_PACR3_ACCESS_CTRL0(x) (((x)&0x07)<<0)
634 #define MCF5235_SCM_PACR3_LOCK0 (0x08)
635 #define MCF5235_SCM_PACR3_ACCESS_CTRL1(x) (((x)&0x07)<<4)
636 #define MCF5235_SCM_PACR3_LOCK1 (0x80)
637 #define MCF5235_SCM_PACR4_ACCESS_CTRL0(x) (((x)&0x07)<<0)
638 #define MCF5235_SCM_PACR4_LOCK0 (0x08)
639 #define MCF5235_SCM_PACR4_ACCESS_CTRL1(x) (((x)&0x07)<<4)
640 #define MCF5235_SCM_PACR4_LOCK1 (0x80)
641 #define MCF5235_SCM_PACR5_ACCESS_CTRL0(x) (((x)&0x07)<<0)
642 #define MCF5235_SCM_PACR5_LOCK0 (0x08)
643 #define MCF5235_SCM_PACR5_ACCESS_CTRL1(x) (((x)&0x07)<<4)
644 #define MCF5235_SCM_PACR5_LOCK1 (0x80)
645 #define MCF5235_SCM_PACR6_ACCESS_CTRL0(x) (((x)&0x07)<<0)
646 #define MCF5235_SCM_PACR6_LOCK0 (0x08)
647 #define MCF5235_SCM_PACR6_ACCESS_CTRL1(x) (((x)&0x07)<<4)
648 #define MCF5235_SCM_PACR6_LOCK1 (0x80)
649 #define MCF5235_SCM_PACR7_ACCESS_CTRL0(x) (((x)&0x07)<<0)
650 #define MCF5235_SCM_PACR7_LOCK0 (0x08)
651 #define MCF5235_SCM_PACR7_ACCESS_CTRL1(x) (((x)&0x07)<<4)
652 #define MCF5235_SCM_PACR7_LOCK1 (0x80)
653 #define MCF5235_SCM_PACR8_ACCESS_CTRL0(x) (((x)&0x07)<<0)
654 #define MCF5235_SCM_PACR8_LOCK0 (0x08)
655 #define MCF5235_SCM_PACR8_ACCESS_CTRL1(x) (((x)&0x07)<<4)
656 #define MCF5235_SCM_PACR8_LOCK1 (0x80)
657 #define MCF5235_SCM_GPACR0_ACCESS_CTRL(x) (((x)&0x0F)<<0)
658 #define MCF5235_SCM_GPACR0_LOCK (0x80)
659 
660 
661 /*********************************************************************
662 *
663 * FlexCAN Module (CAN)
664 *
665 *********************************************************************/
666 
667 /* Register read/write macros */
668 #define MCF5235_CAN_CANMCR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0000)))
669 #define MCF5235_CAN_CANCTRL0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0004)))
670 #define MCF5235_CAN_TIMER0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0008)))
671 #define MCF5235_CAN_RXGMASK0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0010)))
672 #define MCF5235_CAN_RX14MASK0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0014)))
673 #define MCF5235_CAN_RX15MASK0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0018)))
674 #define MCF5235_CAN_ERRCNT0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C001C)))
675 #define MCF5235_CAN_ERRSTAT0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0020)))
676 #define MCF5235_CAN_IMASK0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x1C002A)))
677 #define MCF5235_CAN_IFLAG0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x1C0032)))
678 #define MCF5235_CAN_CANMCR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0000)))
679 #define MCF5235_CAN_CANCTRL1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0004)))
680 #define MCF5235_CAN_TIMER1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0008)))
681 #define MCF5235_CAN_RXGMASK1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0010)))
682 #define MCF5235_CAN_RX14MASK1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0014)))
683 #define MCF5235_CAN_RX15MASK1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0018)))
684 #define MCF5235_CAN_ERRCNT1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F001C)))
685 #define MCF5235_CAN_ERRSTAT1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0020)))
686 #define MCF5235_CAN_IMASK1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x1F002A)))
687 #define MCF5235_CAN_IFLAG1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x1F0032)))
688 #define MCF5235_CAN_CANMCR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0000+((x)*0x30000))))
689 #define MCF5235_CAN_CANCTRL(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0004+((x)*0x30000))))
690 #define MCF5235_CAN_TIMER(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0008+((x)*0x30000))))
691 #define MCF5235_CAN_RXGMASK(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0010+((x)*0x30000))))
692 #define MCF5235_CAN_RX14MASK(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0014+((x)*0x30000))))
693 #define MCF5235_CAN_RX15MASK(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0018+((x)*0x30000))))
694 #define MCF5235_CAN_ERRCNT(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C001C+((x)*0x30000))))
695 #define MCF5235_CAN_ERRSTAT(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0020+((x)*0x30000))))
696 #define MCF5235_CAN_IMASK(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x1C002A+((x)*0x30000))))
697 #define MCF5235_CAN_IFLAG(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x1C0032+((x)*0x30000))))
698 
699 #define MCF5235_CAN_MBUF0_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0080+((x)*0x30000))))
700 #define MCF5235_CAN_MBUF0_TMSTP(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0082+((x)*0x30000))))
701 #define MCF5235_CAN_MBUF0_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0084+((x)*0x30000))))
702 #define MCF5235_CAN_MBUF0_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0088+((x)*0x30000))))
703 #define MCF5235_CAN_MBUF0_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0089+((x)*0x30000))))
704 #define MCF5235_CAN_MBUF0_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008A+((x)*0x30000))))
705 #define MCF5235_CAN_MBUF0_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008B+((x)*0x30000))))
706 #define MCF5235_CAN_MBUF0_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008C+((x)*0x30000))))
707 #define MCF5235_CAN_MBUF0_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008D+((x)*0x30000))))
708 #define MCF5235_CAN_MBUF0_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008E+((x)*0x30000))))
709 #define MCF5235_CAN_MBUF0_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008F+((x)*0x30000))))
710 #define MCF5235_CAN_MBUF1_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0090+((x)*0x30000))))
711 #define MCF5235_CAN_MBUF1_TMSTP(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0092+((x)*0x30000))))
712 #define MCF5235_CAN_MBUF1_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0094+((x)*0x30000))))
713 #define MCF5235_CAN_MBUF1_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0098+((x)*0x30000))))
714 #define MCF5235_CAN_MBUF1_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0099+((x)*0x30000))))
715 #define MCF5235_CAN_MBUF1_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009A+((x)*0x30000))))
716 #define MCF5235_CAN_MBUF1_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009B+((x)*0x30000))))
717 #define MCF5235_CAN_MBUF1_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009C+((x)*0x30000))))
718 #define MCF5235_CAN_MBUF1_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009D+((x)*0x30000))))
719 #define MCF5235_CAN_MBUF1_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009E+((x)*0x30000))))
720 #define MCF5235_CAN_MBUF1_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009F+((x)*0x30000))))
721 #define MCF5235_CAN_MBUF2_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A0+((x)*0x30000))))
722 #define MCF5235_CAN_MBUF2_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A4+((x)*0x30000))))
723 #define MCF5235_CAN_MBUF2_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A8+((x)*0x30000))))
724 #define MCF5235_CAN_MBUF2_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A9+((x)*0x30000))))
725 #define MCF5235_CAN_MBUF2_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AA+((x)*0x30000))))
726 #define MCF5235_CAN_MBUF2_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AB+((x)*0x30000))))
727 #define MCF5235_CAN_MBUF2_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AC+((x)*0x30000))))
728 #define MCF5235_CAN_MBUF2_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AD+((x)*0x30000))))
729 #define MCF5235_CAN_MBUF2_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AE+((x)*0x30000))))
730 #define MCF5235_CAN_MBUF2_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AF+((x)*0x30000))))
731 #define MCF5235_CAN_MBUF3_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00B0+((x)*0x30000))))
732 #define MCF5235_CAN_MBUF3_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00B4+((x)*0x30000))))
733 #define MCF5235_CAN_MBUF3_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00B8+((x)*0x30000))))
734 #define MCF5235_CAN_MBUF3_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00B9+((x)*0x30000))))
735 #define MCF5235_CAN_MBUF3_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BA+((x)*0x30000))))
736 #define MCF5235_CAN_MBUF3_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BB+((x)*0x30000))))
737 #define MCF5235_CAN_MBUF3_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BC+((x)*0x30000))))
738 #define MCF5235_CAN_MBUF3_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BD+((x)*0x30000))))
739 #define MCF5235_CAN_MBUF3_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BE+((x)*0x30000))))
740 #define MCF5235_CAN_MBUF3_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BF+((x)*0x30000))))
741 #define MCF5235_CAN_MBUF4_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00C0+((x)*0x30000))))
742 #define MCF5235_CAN_MBUF4_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00C4+((x)*0x30000))))
743 #define MCF5235_CAN_MBUF4_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00C8+((x)*0x30000))))
744 #define MCF5235_CAN_MBUF4_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00C9+((x)*0x30000))))
745 #define MCF5235_CAN_MBUF4_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CA+((x)*0x30000))))
746 #define MCF5235_CAN_MBUF4_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CB+((x)*0x30000))))
747 #define MCF5235_CAN_MBUF4_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CC+((x)*0x30000))))
748 #define MCF5235_CAN_MBUF4_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CD+((x)*0x30000))))
749 #define MCF5235_CAN_MBUF4_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CE+((x)*0x30000))))
750 #define MCF5235_CAN_MBUF4_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CF+((x)*0x30000))))
751 #define MCF5235_CAN_MBUF5_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00D0+((x)*0x30000))))
752 #define MCF5235_CAN_MBUF5_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00D4+((x)*0x30000))))
753 #define MCF5235_CAN_MBUF5_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00D8+((x)*0x30000))))
754 #define MCF5235_CAN_MBUF5_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00D9+((x)*0x30000))))
755 #define MCF5235_CAN_MBUF5_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DA+((x)*0x30000))))
756 #define MCF5235_CAN_MBUF5_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DB+((x)*0x30000))))
757 #define MCF5235_CAN_MBUF5_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DC+((x)*0x30000))))
758 #define MCF5235_CAN_MBUF5_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DD+((x)*0x30000))))
759 #define MCF5235_CAN_MBUF5_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DE+((x)*0x30000))))
760 #define MCF5235_CAN_MBUF5_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DF+((x)*0x30000))))
761 #define MCF5235_CAN_MBUF6_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00E0+((x)*0x30000))))
762 #define MCF5235_CAN_MBUF6_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00E4+((x)*0x30000))))
763 #define MCF5235_CAN_MBUF6_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00E8+((x)*0x30000))))
764 #define MCF5235_CAN_MBUF6_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00E9+((x)*0x30000))))
765 #define MCF5235_CAN_MBUF6_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EA+((x)*0x30000))))
766 #define MCF5235_CAN_MBUF6_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EB+((x)*0x30000))))
767 #define MCF5235_CAN_MBUF6_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EC+((x)*0x30000))))
768 #define MCF5235_CAN_MBUF6_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00ED+((x)*0x30000))))
769 #define MCF5235_CAN_MBUF6_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EE+((x)*0x30000))))
770 #define MCF5235_CAN_MBUF6_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EF+((x)*0x30000))))
771 #define MCF5235_CAN_MBUF7_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00F0+((x)*0x30000))))
772 #define MCF5235_CAN_MBUF7_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00F4+((x)*0x30000))))
773 #define MCF5235_CAN_MBUF7_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00F8+((x)*0x30000))))
774 #define MCF5235_CAN_MBUF7_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00F9+((x)*0x30000))))
775 #define MCF5235_CAN_MBUF7_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FA+((x)*0x30000))))
776 #define MCF5235_CAN_MBUF7_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FB+((x)*0x30000))))
777 #define MCF5235_CAN_MBUF7_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FC+((x)*0x30000))))
778 #define MCF5235_CAN_MBUF7_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FD+((x)*0x30000))))
779 #define MCF5235_CAN_MBUF7_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FE+((x)*0x30000))))
780 #define MCF5235_CAN_MBUF7_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FF+((x)*0x30000))))
781 #define MCF5235_CAN_MBUF8_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0100+((x)*0x30000))))
782 #define MCF5235_CAN_MBUF8_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0104+((x)*0x30000))))
783 #define MCF5235_CAN_MBUF8_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0108+((x)*0x30000))))
784 #define MCF5235_CAN_MBUF8_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0109+((x)*0x30000))))
785 #define MCF5235_CAN_MBUF8_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010A+((x)*0x30000))))
786 #define MCF5235_CAN_MBUF8_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010B+((x)*0x30000))))
787 #define MCF5235_CAN_MBUF8_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010C+((x)*0x30000))))
788 #define MCF5235_CAN_MBUF8_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010D+((x)*0x30000))))
789 #define MCF5235_CAN_MBUF8_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010E+((x)*0x30000))))
790 #define MCF5235_CAN_MBUF8_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010F+((x)*0x30000))))
791 #define MCF5235_CAN_MBUF9_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0100+((x)*0x30000))))
792 #define MCF5235_CAN_MBUF9_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0114+((x)*0x30000))))
793 #define MCF5235_CAN_MBUF9_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0118+((x)*0x30000))))
794 #define MCF5235_CAN_MBUF9_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0119+((x)*0x30000))))
795 #define MCF5235_CAN_MBUF9_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011A+((x)*0x30000))))
796 #define MCF5235_CAN_MBUF9_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011B+((x)*0x30000))))
797 #define MCF5235_CAN_MBUF9_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011C+((x)*0x30000))))
798 #define MCF5235_CAN_MBUF9_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011D+((x)*0x30000))))
799 #define MCF5235_CAN_MBUF9_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011E+((x)*0x30000))))
800 #define MCF5235_CAN_MBUF9_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011F+((x)*0x30000))))
801 #define MCF5235_CAN_MBUF10_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0120+((x)*0x30000))))
802 #define MCF5235_CAN_MBUF10_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0124+((x)*0x30000))))
803 #define MCF5235_CAN_MBUF10_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0128+((x)*0x30000))))
804 #define MCF5235_CAN_MBUF10_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0129+((x)*0x30000))))
805 #define MCF5235_CAN_MBUF10_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012A+((x)*0x30000))))
806 #define MCF5235_CAN_MBUF10_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012B+((x)*0x30000))))
807 #define MCF5235_CAN_MBUF10_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012C+((x)*0x30000))))
808 #define MCF5235_CAN_MBUF10_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012D+((x)*0x30000))))
809 #define MCF5235_CAN_MBUF10_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012E+((x)*0x30000))))
810 #define MCF5235_CAN_MBUF10_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012F+((x)*0x30000))))
811 #define MCF5235_CAN_MBUF11_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0130+((x)*0x30000))))
812 #define MCF5235_CAN_MBUF11_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0134+((x)*0x30000))))
813 #define MCF5235_CAN_MBUF11_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0138+((x)*0x30000))))
814 #define MCF5235_CAN_MBUF11_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0139+((x)*0x30000))))
815 #define MCF5235_CAN_MBUF11_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013A+((x)*0x30000))))
816 #define MCF5235_CAN_MBUF11_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013B+((x)*0x30000))))
817 #define MCF5235_CAN_MBUF11_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013C+((x)*0x30000))))
818 #define MCF5235_CAN_MBUF11_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013D+((x)*0x30000))))
819 #define MCF5235_CAN_MBUF11_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013E+((x)*0x30000))))
820 #define MCF5235_CAN_MBUF11_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013F+((x)*0x30000))))
821 #define MCF5235_CAN_MBUF12_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0140+((x)*0x30000))))
822 #define MCF5235_CAN_MBUF12_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0144+((x)*0x30000))))
823 #define MCF5235_CAN_MBUF12_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0148+((x)*0x30000))))
824 #define MCF5235_CAN_MBUF12_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0149+((x)*0x30000))))
825 #define MCF5235_CAN_MBUF12_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014A+((x)*0x30000))))
826 #define MCF5235_CAN_MBUF12_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014B+((x)*0x30000))))
827 #define MCF5235_CAN_MBUF12_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014C+((x)*0x30000))))
828 #define MCF5235_CAN_MBUF12_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014D+((x)*0x30000))))
829 #define MCF5235_CAN_MBUF12_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014E+((x)*0x30000))))
830 #define MCF5235_CAN_MBUF12_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014F+((x)*0x30000))))
831 #define MCF5235_CAN_MBUF13_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0150+((x)*0x30000))))
832 #define MCF5235_CAN_MBUF13_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0154+((x)*0x30000))))
833 #define MCF5235_CAN_MBUF13_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0158+((x)*0x30000))))
834 #define MCF5235_CAN_MBUF13_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0159+((x)*0x30000))))
835 #define MCF5235_CAN_MBUF13_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015A+((x)*0x30000))))
836 #define MCF5235_CAN_MBUF13_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015B+((x)*0x30000))))
837 #define MCF5235_CAN_MBUF13_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015C+((x)*0x30000))))
838 #define MCF5235_CAN_MBUF13_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015D+((x)*0x30000))))
839 #define MCF5235_CAN_MBUF13_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015E+((x)*0x30000))))
840 #define MCF5235_CAN_MBUF13_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015F+((x)*0x30000))))
841 #define MCF5235_CAN_MBUF14_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0160+((x)*0x30000))))
842 #define MCF5235_CAN_MBUF14_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0164+((x)*0x30000))))
843 #define MCF5235_CAN_MBUF14_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0168+((x)*0x30000))))
844 #define MCF5235_CAN_MBUF14_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0169+((x)*0x30000))))
845 #define MCF5235_CAN_MBUF14_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016A+((x)*0x30000))))
846 #define MCF5235_CAN_MBUF14_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016B+((x)*0x30000))))
847 #define MCF5235_CAN_MBUF14_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016C+((x)*0x30000))))
848 #define MCF5235_CAN_MBUF14_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016D+((x)*0x30000))))
849 #define MCF5235_CAN_MBUF14_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016E+((x)*0x30000))))
850 #define MCF5235_CAN_MBUF14_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016F+((x)*0x30000))))
851 #define MCF5235_CAN_MBUF15_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0170+((x)*0x30000))))
852 #define MCF5235_CAN_MBUF15_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0174+((x)*0x30000))))
853 #define MCF5235_CAN_MBUF15_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0178+((x)*0x30000))))
854 #define MCF5235_CAN_MBUF15_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0179+((x)*0x30000))))
855 #define MCF5235_CAN_MBUF15_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017A+((x)*0x30000))))
856 #define MCF5235_CAN_MBUF15_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017B+((x)*0x30000))))
857 #define MCF5235_CAN_MBUF15_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017C+((x)*0x30000))))
858 #define MCF5235_CAN_MBUF15_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017D+((x)*0x30000))))
859 #define MCF5235_CAN_MBUF15_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017E+((x)*0x30000))))
860 #define MCF5235_CAN_MBUF15_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017F+((x)*0x30000))))
861 #define MCF5235_CAN_MBUF0_DATAL(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0088+((x)*0x30000))))
862 #define MCF5235_CAN_MBUF0_DATAH(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C008C+((x)*0x30000))))
863 #define MCF5235_CAN_MBUF1_DATAL(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0098+((x)*0x30000))))
864 #define MCF5235_CAN_MBUF1_DATAH(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C009C+((x)*0x30000))))
865 #define MCF5235_CAN_MBUF2_DATAL(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A8+((x)*0x30000))))
866 #define MCF5235_CAN_MBUF2_DATAH(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AC+((x)*0x30000))))
867 
868 
869 /* Bit definitions and macros for MCF5235_CAN_CANMCR */
870 #define MCF5235_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0)
871 #define MCF5235_CAN_CANMCR_SUPV (0x00800000)
872 #define MCF5235_CAN_CANMCR_FRZACK (0x01000000)
873 #define MCF5235_CAN_CANMCR_SOFTRST (0x02000000)
874 #define MCF5235_CAN_CANMCR_HALT (0x10000000)
875 #define MCF5235_CAN_CANMCR_FRZ (0x40000000)
876 #define MCF5235_CAN_CANMCR_MDIS (0x80000000)
877 #define MCF5235_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0)
878 #define MCF5235_CAN_CANCTRL_LOM (0x00000008)
879 #define MCF5235_CAN_CANCTRL_LBUF (0x00000010)
880 #define MCF5235_CAN_CANCTRL_TSYNC (0x00000020)
881 #define MCF5235_CAN_CANCTRL_BOFFREC (0x00000040)
882 #define MCF5235_CAN_CANCTRL_SAMP (0x00000080)
883 #define MCF5235_CAN_CANCTRL_LPB (0x00001000)
884 #define MCF5235_CAN_CANCTRL_CLKSRC (0x00002000)
885 #define MCF5235_CAN_CANCTRL_ERRMSK (0x00004000)
886 #define MCF5235_CAN_CANCTRL_BOFFMSK (0x00008000)
887 #define MCF5235_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16)
888 #define MCF5235_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19)
889 #define MCF5235_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22)
890 #define MCF5235_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24)
891 #define MCF5235_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0)
892 #define MCF5235_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0)
893 #define MCF5235_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
894 #define MCF5235_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
895 #define MCF5235_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0)
896 #define MCF5235_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8)
897 #define MCF5235_CAN_ERRSTAT_WAKINT (0x00000001)
898 #define MCF5235_CAN_ERRSTAT_ERRINT (0x00000002)
899 #define MCF5235_CAN_ERRSTAT_BOFFINT (0x00000004)
900 #define MCF5235_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4)
901 #define MCF5235_CAN_ERRSTAT_TXRX (0x00000040)
902 #define MCF5235_CAN_ERRSTAT_IDLE (0x00000080)
903 #define MCF5235_CAN_ERRSTAT_RXWRN (0x00000100)
904 #define MCF5235_CAN_ERRSTAT_TXWRN (0x00000200)
905 #define MCF5235_CAN_ERRSTAT_STFERR (0x00000400)
906 #define MCF5235_CAN_ERRSTAT_FRMERR (0x00000800)
907 #define MCF5235_CAN_ERRSTAT_CRCERR (0x00001000)
908 #define MCF5235_CAN_ERRSTAT_ACKERR (0x00002000)
909 #define MCF5235_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14)
910 #define MCF5235_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000)
911 #define MCF5235_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010)
912 #define MCF5235_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020)
913 #define MCF5235_CAN_IMASK_BUF0M (0x0001)
914 #define MCF5235_CAN_IMASK_BUF1M (0x0002)
915 #define MCF5235_CAN_IMASK_BUF2M (0x0004)
916 #define MCF5235_CAN_IMASK_BUF3M (0x0008)
917 #define MCF5235_CAN_IMASK_BUF4M (0x0010)
918 #define MCF5235_CAN_IMASK_BUF5M (0x0020)
919 #define MCF5235_CAN_IMASK_BUF6M (0x0040)
920 #define MCF5235_CAN_IMASK_BUF7M (0x0080)
921 #define MCF5235_CAN_IMASK_BUF8M (0x0100)
922 #define MCF5235_CAN_IMASK_BUF9M (0x0200)
923 #define MCF5235_CAN_IMASK_BUF10M (0x0400)
924 #define MCF5235_CAN_IMASK_BUF11M (0x0800)
925 #define MCF5235_CAN_IMASK_BUF12M (0x1000)
926 #define MCF5235_CAN_IMASK_BUF13M (0x2000)
927 #define MCF5235_CAN_IMASK_BUF14M (0x4000)
928 #define MCF5235_CAN_IMASK_BUF15M (0x8000)
929 
930 /* Bit definitions and macros for MCF5235_CAN_IFLAG */
931 #define MCF5235_CAN_IFLAG_BUF0I (0x0001)
932 #define MCF5235_CAN_IFLAG_BUF1I (0x0002)
933 #define MCF5235_CAN_IFLAG_BUF2I (0x0004)
934 #define MCF5235_CAN_IFLAG_BUF3I (0x0008)
935 #define MCF5235_CAN_IFLAG_BUF4I (0x0010)
936 #define MCF5235_CAN_IFLAG_BUF5I (0x0020)
937 #define MCF5235_CAN_IFLAG_BUF6I (0x0040)
938 #define MCF5235_CAN_IFLAG_BUF7I (0x0080)
939 #define MCF5235_CAN_IFLAG_BUF8I (0x0100)
940 #define MCF5235_CAN_IFLAG_BUF9I (0x0200)
941 #define MCF5235_CAN_IFLAG_BUF10I (0x0400)
942 #define MCF5235_CAN_IFLAG_BUF11I (0x0800)
943 #define MCF5235_CAN_IFLAG_BUF12I (0x1000)
944 #define MCF5235_CAN_IFLAG_BUF13I (0x2000)
945 #define MCF5235_CAN_IFLAG_BUF14I (0x4000)
946 #define MCF5235_CAN_IFLAG_BUF15I (0x8000)
947 
948 
949 /*********************************************************************
950 *
951 * Chip Configuration Module (CCM)
952 *
953 *********************************************************************/
954 
955 /* Register read/write macros */
956 #define MCF5235_CCM_CCR (*(vuint16*)((uintptr_t)__IPSBAR + (0x110004)))
957 #define MCF5235_CCM_LPCR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x110007)))
958 #define MCF5235_CCM_CIR (*(vuint16*)((uintptr_t)__IPSBAR + (0x11000A)))
959 #define MCF5235_CCM_RCON (*(vuint16*)((uintptr_t)__IPSBAR + (0x110008)))
960 
961 /* Bit definitions and macros for MCF5235_CCM_CCR */
962 #define MCF5235_CCM_CCR_BMT(x) (((x)&0x0007)<<0)
963 #define MCF5235_CCM_CCR_BME (0x0008)
964 #define MCF5235_CCM_CCR_SZEN (0x0040)
965 #define MCF5235_CCM_CCR_MODE(x) (((x)&0x0007)<<8)
966 #define MCF5235_CCM_LPCR_STPMD(x) (((x)&0x03)<<3)
967 #define MCF5235_CCM_LPCR_LPMD(x) (((x)&0x03)<<6)
968 #define MCF5235_CCM_LPCR_LPMD_STOP (0xC0)
969 #define MCF5235_CCM_LPCR_LPMD_WAIT (0x80)
970 #define MCF5235_CCM_LPCR_LPMD_DOZE (0x40)
971 #define MCF5235_CCM_LPCR_LPMD_RUN (0x00)
972 #define MCF5235_CCM_CIR_PRN(x) (((x)&0x003F)<<0)
973 #define MCF5235_CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
974 #define MCF5235_CCM_RCON_MODE (0x0001)
975 #define MCF5235_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3)
976 #define MCF5235_CCM_RCON_RLOAD (0x0020)
977 #define MCF5235_CCM_RCON_RCSC(x) (((x)&0x0003)<<8)
978 
979 /*********************************************************************
980 *
981 * Chip Selects (CS)
982 *
983 *********************************************************************/
984 
985 /* Register read/write macros */
986 #define MCF5235_CS_CSAR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000080)))
987 #define MCF5235_CS_CSMR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000084)))
988 #define MCF5235_CS_CSCR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x00008A)))
989 #define MCF5235_CS_CSAR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x00008C)))
990 #define MCF5235_CS_CSMR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000090)))
991 #define MCF5235_CS_CSCR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000096)))
992 #define MCF5235_CS_CSAR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000098)))
993 #define MCF5235_CS_CSMR2 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00009C)))
994 #define MCF5235_CS_CSCR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000A2)))
995 #define MCF5235_CS_CSAR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000A4)))
996 #define MCF5235_CS_CSMR3 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000A8)))
997 #define MCF5235_CS_CSCR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000AE)))
998 #define MCF5235_CS_CSAR4 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000B0)))
999 #define MCF5235_CS_CSMR4 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000B4)))
1000 #define MCF5235_CS_CSCR4 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000BA)))
1001 #define MCF5235_CS_CSAR5 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000BC)))
1002 #define MCF5235_CS_CSMR5 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000C0)))
1003 #define MCF5235_CS_CSCR5 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000C6)))
1004 #define MCF5235_CS_CSAR6 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000C8)))
1005 #define MCF5235_CS_CSMR6 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000CC)))
1006 #define MCF5235_CS_CSCR6 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000D2)))
1007 #define MCF5235_CS_CSAR7 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000D4)))
1008 #define MCF5235_CS_CSMR7 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000D8)))
1009 #define MCF5235_CS_CSCR7 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000DE)))
1010 #define MCF5235_CS_CSAR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x000080+((x)*0x00C))))
1011 #define MCF5235_CS_CSMR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x000084+((x)*0x00C))))
1012 #define MCF5235_CS_CSCR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x00008A+((x)*0x00C))))
1013 
1014 /* Bit definitions and macros for MCF5235_CS_CSAR */
1015 #define MCF5235_CS_CSAR_BA(x) ((uint16)(((x)&0xFFFF0000)>>16))
1016 #define MCF5235_CS_CSMR_V (0x00000001)
1017 #define MCF5235_CS_CSMR_UD (0x00000002)
1018 #define MCF5235_CS_CSMR_UC (0x00000004)
1019 #define MCF5235_CS_CSMR_SD (0x00000008)
1020 #define MCF5235_CS_CSMR_SC (0x00000010)
1021 #define MCF5235_CS_CSMR_CI (0x00000020)
1022 #define MCF5235_CS_CSMR_AM (0x00000040)
1023 #define MCF5235_CS_CSMR_WP (0x00000100)
1024 #define MCF5235_CS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16)
1025 #define MCF5235_CS_CSMR_BAM_4G (0xFFFF0000)
1026 #define MCF5235_CS_CSMR_BAM_2G (0x7FFF0000)
1027 #define MCF5235_CS_CSMR_BAM_1G (0x3FFF0000)
1028 #define MCF5235_CS_CSMR_BAM_1024M (0x3FFF0000)
1029 #define MCF5235_CS_CSMR_BAM_512M (0x1FFF0000)
1030 #define MCF5235_CS_CSMR_BAM_256M (0x0FFF0000)
1031 #define MCF5235_CS_CSMR_BAM_128M (0x07FF0000)
1032 #define MCF5235_CS_CSMR_BAM_64M (0x03FF0000)
1033 #define MCF5235_CS_CSMR_BAM_32M (0x01FF0000)
1034 #define MCF5235_CS_CSMR_BAM_16M (0x00FF0000)
1035 #define MCF5235_CS_CSMR_BAM_8M (0x007F0000)
1036 #define MCF5235_CS_CSMR_BAM_4M (0x003F0000)
1037 #define MCF5235_CS_CSMR_BAM_2M (0x001F0000)
1038 #define MCF5235_CS_CSMR_BAM_1M (0x000F0000)
1039 #define MCF5235_CS_CSMR_BAM_1024K (0x000F0000)
1040 #define MCF5235_CS_CSMR_BAM_512K (0x00070000)
1041 #define MCF5235_CS_CSMR_BAM_256K (0x00030000)
1042 #define MCF5235_CS_CSMR_BAM_128K (0x00010000)
1043 #define MCF5235_CS_CSMR_BAM_64K (0x00000000)
1044 #define MCF5235_CS_CSCR_SWWS(x) (((x)&0x0007)<<0)
1045 #define MCF5235_CS_CSCR_BSTW (0x0008)
1046 #define MCF5235_CS_CSCR_BSTR (0x0010)
1047 #define MCF5235_CS_CSCR_BEM (0x0020)
1048 #define MCF5235_CS_CSCR_PS(x) (((x)&0x0003)<<6)
1049 #define MCF5235_CS_CSCR_AA (0x0100)
1050 #define MCF5235_CS_CSCR_IWS(x) (((x)&0x000F)<<10)
1051 #define MCF5235_CS_CSCR_SRWS(x) (((x)&0x0003)<<14)
1052 #define MCF5235_CS_CSCR_PS_8 (0x0040)
1053 #define MCF5235_CS_CSCR_PS_16 (0x0080)
1054 #define MCF5235_CS_CSCR_PS_32 (0x0000)
1055 
1056 /*********************************************************************
1057 *
1058 * Edge Port Module (EPORT)
1059 *
1060 *********************************************************************/
1061 
1062 /* Register read/write macros */
1063 #define MCF5235_EPORT_EPPAR (*(vuint16*)((uintptr_t)__IPSBAR + (0x130000)))
1064 #define MCF5235_EPORT_EPDDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130002)))
1065 #define MCF5235_EPORT_EPIER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130003)))
1066 #define MCF5235_EPORT_EPDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130004)))
1067 #define MCF5235_EPORT_EPPDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130005)))
1068 #define MCF5235_EPORT_EPFR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130006)))
1069 
1070 /* Bit definitions and macros for MCF5235_EPORT_EPPAR */
1071 #define MCF5235_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
1072 #define MCF5235_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
1073 #define MCF5235_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
1074 #define MCF5235_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
1075 #define MCF5235_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
1076 #define MCF5235_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
1077 #define MCF5235_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
1078 #define MCF5235_EPORT_EPPAR_EPPAx_LEVEL (0)
1079 #define MCF5235_EPORT_EPPAR_EPPAx_RISING (1)
1080 #define MCF5235_EPORT_EPPAR_EPPAx_FALLING (2)
1081 #define MCF5235_EPORT_EPPAR_EPPAx_BOTH (3)
1082 #define MCF5235_EPORT_EPDDR_EPDD1 (0x02)
1083 #define MCF5235_EPORT_EPDDR_EPDD2 (0x04)
1084 #define MCF5235_EPORT_EPDDR_EPDD3 (0x08)
1085 #define MCF5235_EPORT_EPDDR_EPDD4 (0x10)
1086 #define MCF5235_EPORT_EPDDR_EPDD5 (0x20)
1087 #define MCF5235_EPORT_EPDDR_EPDD6 (0x40)
1088 #define MCF5235_EPORT_EPDDR_EPDD7 (0x80)
1089 #define MCF5235_EPORT_EPIER_EPIE1 (0x02)
1090 #define MCF5235_EPORT_EPIER_EPIE2 (0x04)
1091 #define MCF5235_EPORT_EPIER_EPIE3 (0x08)
1092 #define MCF5235_EPORT_EPIER_EPIE4 (0x10)
1093 #define MCF5235_EPORT_EPIER_EPIE5 (0x20)
1094 #define MCF5235_EPORT_EPIER_EPIE6 (0x40)
1095 #define MCF5235_EPORT_EPIER_EPIE7 (0x80)
1096 #define MCF5235_EPORT_EPDR_EPD1 (0x02)
1097 #define MCF5235_EPORT_EPDR_EPD2 (0x04)
1098 #define MCF5235_EPORT_EPDR_EPD3 (0x08)
1099 #define MCF5235_EPORT_EPDR_EPD4 (0x10)
1100 #define MCF5235_EPORT_EPDR_EPD5 (0x20)
1101 #define MCF5235_EPORT_EPDR_EPD6 (0x40)
1102 #define MCF5235_EPORT_EPDR_EPD7 (0x80)
1103 #define MCF5235_EPORT_EPPDR_EPPD1 (0x02)
1104 #define MCF5235_EPORT_EPPDR_EPPD2 (0x04)
1105 #define MCF5235_EPORT_EPPDR_EPPD3 (0x08)
1106 #define MCF5235_EPORT_EPPDR_EPPD4 (0x10)
1107 #define MCF5235_EPORT_EPPDR_EPPD5 (0x20)
1108 #define MCF5235_EPORT_EPPDR_EPPD6 (0x40)
1109 #define MCF5235_EPORT_EPPDR_EPPD7 (0x80)
1110 #define MCF5235_EPORT_EPFR_EPF1 (0x02)
1111 #define MCF5235_EPORT_EPFR_EPF2 (0x04)
1112 #define MCF5235_EPORT_EPFR_EPF3 (0x08)
1113 #define MCF5235_EPORT_EPFR_EPF4 (0x10)
1114 #define MCF5235_EPORT_EPFR_EPF5 (0x20)
1115 #define MCF5235_EPORT_EPFR_EPF6 (0x40)
1116 #define MCF5235_EPORT_EPFR_EPF7 (0x80)
1117 
1118 
1119 /*********************************************************************
1120 *
1121 * enhanced Time Processor Unit (ETPU)
1122 *
1123 *********************************************************************/
1124 
1125 /* Register read/write macros */
1126 #define MCF5235_ETPU_EMCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0000)))
1127 #define MCF5235_ETPU_ECDCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0004)))
1128 #define MCF5235_ETPU_EMISCCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D000C)))
1129 #define MCF5235_ETPU_ESCMODR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0010)))
1130 #define MCF5235_ETPU_EECR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0014)))
1131 #define MCF5235_ETPU_ETBCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0020)))
1132 #define MCF5235_ETPU_ETB1R (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0024)))
1133 #define MCF5235_ETPU_ETB2R (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0028)))
1134 #define MCF5235_ETPU_EREDCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D002C)))
1135 #define MCF5235_ETPU_ECISR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0200)))
1136 #define MCF5235_ETPU_ECDTRSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0210)))
1137 #define MCF5235_ETPU_ECIOSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0220)))
1138 #define MCF5235_ETPU_ECDTROSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0230)))
1139 #define MCF5235_ETPU_ECIER (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0240)))
1140 #define MCF5235_ETPU_ECDTRER (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0250)))
1141 #define MCF5235_ETPU_ECPSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0280)))
1142 #define MCF5235_ETPU_ECSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0290)))
1143 #define MCF5235_ETPU_EC0SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0404)))
1144 #define MCF5235_ETPU_EC1SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0414)))
1145 #define MCF5235_ETPU_EC2SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0424)))
1146 #define MCF5235_ETPU_EC3SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0434)))
1147 #define MCF5235_ETPU_EC4SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0444)))
1148 #define MCF5235_ETPU_EC5SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0454)))
1149 #define MCF5235_ETPU_EC6SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0464)))
1150 #define MCF5235_ETPU_EC7SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0474)))
1151 #define MCF5235_ETPU_EC8SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0484)))
1152 #define MCF5235_ETPU_EC9SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0494)))
1153 #define MCF5235_ETPU_EC10SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04A4)))
1154 #define MCF5235_ETPU_EC11SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04B4)))
1155 #define MCF5235_ETPU_EC12SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04C4)))
1156 #define MCF5235_ETPU_EC13SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04D4)))
1157 #define MCF5235_ETPU_EC14SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04E4)))
1158 #define MCF5235_ETPU_EC15SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04F4)))
1159 #define MCF5235_ETPU_EC16SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0504)))
1160 #define MCF5235_ETPU_EC17SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0514)))
1161 #define MCF5235_ETPU_EC18SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0524)))
1162 #define MCF5235_ETPU_EC19SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0534)))
1163 #define MCF5235_ETPU_EC20SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0544)))
1164 #define MCF5235_ETPU_EC21SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0554)))
1165 #define MCF5235_ETPU_EC22SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0564)))
1166 #define MCF5235_ETPU_EC23SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0574)))
1167 #define MCF5235_ETPU_EC24SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0584)))
1168 #define MCF5235_ETPU_EC25SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0594)))
1169 #define MCF5235_ETPU_EC26SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05A4)))
1170 #define MCF5235_ETPU_EC27SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05B4)))
1171 #define MCF5235_ETPU_EC28SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05C4)))
1172 #define MCF5235_ETPU_EC29SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05D4)))
1173 #define MCF5235_ETPU_EC30SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05E4)))
1174 #define MCF5235_ETPU_EC31SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05F4)))
1175 #define MCF5235_ETPU_ECnSCR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0404+((x)*0x010))))
1176 #define MCF5235_ETPU_EC0CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0400)))
1177 #define MCF5235_ETPU_EC1CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0410)))
1178 #define MCF5235_ETPU_EC2CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0420)))
1179 #define MCF5235_ETPU_EC3CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0430)))
1180 #define MCF5235_ETPU_EC4CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0440)))
1181 #define MCF5235_ETPU_EC5CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0450)))
1182 #define MCF5235_ETPU_EC6CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0460)))
1183 #define MCF5235_ETPU_EC7CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0470)))
1184 #define MCF5235_ETPU_EC8CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0480)))
1185 #define MCF5235_ETPU_EC9CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0490)))
1186 #define MCF5235_ETPU_EC10CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04A0)))
1187 #define MCF5235_ETPU_EC11CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04B0)))
1188 #define MCF5235_ETPU_EC12CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04C0)))
1189 #define MCF5235_ETPU_EC13CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04D0)))
1190 #define MCF5235_ETPU_EC14CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04E0)))
1191 #define MCF5235_ETPU_EC15CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04F0)))
1192 #define MCF5235_ETPU_EC16CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0500)))
1193 #define MCF5235_ETPU_EC17CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0510)))
1194 #define MCF5235_ETPU_EC18CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0520)))
1195 #define MCF5235_ETPU_EC19CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0530)))
1196 #define MCF5235_ETPU_EC20CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0540)))
1197 #define MCF5235_ETPU_EC21CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0550)))
1198 #define MCF5235_ETPU_EC22CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0560)))
1199 #define MCF5235_ETPU_EC23CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0570)))
1200 #define MCF5235_ETPU_EC24CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0580)))
1201 #define MCF5235_ETPU_EC25CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0590)))
1202 #define MCF5235_ETPU_EC26CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05A0)))
1203 #define MCF5235_ETPU_EC27CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05B0)))
1204 #define MCF5235_ETPU_EC28CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05C0)))
1205 #define MCF5235_ETPU_EC29CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05D0)))
1206 #define MCF5235_ETPU_EC30CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05E0)))
1207 #define MCF5235_ETPU_EC31CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05F0)))
1208 #define MCF5235_ETPU_ECnCR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0400+((x)*0x010))))
1209 #define MCF5235_ETPU_EC0HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0408)))
1210 #define MCF5235_ETPU_EC1HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0418)))
1211 #define MCF5235_ETPU_EC2HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0428)))
1212 #define MCF5235_ETPU_EC3HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0438)))
1213 #define MCF5235_ETPU_EC4HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0448)))
1214 #define MCF5235_ETPU_EC5HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0458)))
1215 #define MCF5235_ETPU_EC6HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0468)))
1216 #define MCF5235_ETPU_EC7HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0478)))
1217 #define MCF5235_ETPU_EC8HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0488)))
1218 #define MCF5235_ETPU_EC9HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0498)))
1219 #define MCF5235_ETPU_EC10HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04A8)))
1220 #define MCF5235_ETPU_EC11HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04B8)))
1221 #define MCF5235_ETPU_EC12HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04C8)))
1222 #define MCF5235_ETPU_EC13HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04D8)))
1223 #define MCF5235_ETPU_EC14HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04E8)))
1224 #define MCF5235_ETPU_EC15HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04F8)))
1225 #define MCF5235_ETPU_EC16HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0508)))
1226 #define MCF5235_ETPU_EC17HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0518)))
1227 #define MCF5235_ETPU_EC18HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0528)))
1228 #define MCF5235_ETPU_EC19HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0538)))
1229 #define MCF5235_ETPU_EC20HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0548)))
1230 #define MCF5235_ETPU_EC21HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0558)))
1231 #define MCF5235_ETPU_EC22HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0568)))
1232 #define MCF5235_ETPU_EC23HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0578)))
1233 #define MCF5235_ETPU_EC24HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0588)))
1234 #define MCF5235_ETPU_EC25HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0598)))
1235 #define MCF5235_ETPU_EC26HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05A8)))
1236 #define MCF5235_ETPU_EC27HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05B8)))
1237 #define MCF5235_ETPU_EC28HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05C8)))
1238 #define MCF5235_ETPU_EC29HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05D8)))
1239 #define MCF5235_ETPU_EC30HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05E8)))
1240 #define MCF5235_ETPU_EC31HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05F8)))
1241 #define MCF5235_ETPU_ECnHSSR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0408+((x)*0x010))))
1242 
1243 /* Bit definitions and macros for MCF5235_ETPU_EMCR */
1244 #define MCF5235_ETPU_EMCR_GTBE (0x00000001)
1245 #define MCF5235_ETPU_EMCR_VIS (0x00000040)
1246 #define MCF5235_ETPU_EMCR_SCMMISEN (0x00000200)
1247 #define MCF5235_ETPU_EMCR_SCMMISF (0x00000400)
1248 #define MCF5235_ETPU_EMCR_SCMSIZE(x) (((x)&0x0000001F)<<16)
1249 #define MCF5235_ETPU_EMCR_ILF2 (0x01000000)
1250 #define MCF5235_ETPU_EMCR_ILF1 (0x02000000)
1251 #define MCF5235_ETPU_EMCR_MGE2 (0x04000000)
1252 #define MCF5235_ETPU_EMCR_MGE1 (0x08000000)
1253 #define MCF5235_ETPU_EMCR_GEC (0x80000000)
1254 #define MCF5235_ETPU_ECDCR_PARM1(x) (((x)&0x0000007F)<<0)
1255 #define MCF5235_ETPU_ECDCR_WR (0x00000080)
1256 #define MCF5235_ETPU_ECDCR_PARM0(x) (((x)&0x0000007F)<<8)
1257 #define MCF5235_ETPU_ECDCR_PWIDTH (0x00008000)
1258 #define MCF5235_ETPU_ECDCR_PBASE(x) (((x)&0x000003FF)<<16)
1259 #define MCF5235_ETPU_ECDCR_CTBASE(x) (((x)&0x0000001F)<<26)
1260 #define MCF5235_ETPU_ECDCR_STS (0x80000000)
1261 #define MCF5235_ETPU_EECR_ETB(x) (((x)&0x0000001F)<<0)
1262 #define MCF5235_ETPU_EECR_CDFC(x) (((x)&0x00000003)<<14)
1263 #define MCF5235_ETPU_EECR_FPSK(x) (((x)&0x00000007)<<16)
1264 #define MCF5235_ETPU_EECR_HLTF (0x00800000)
1265 #define MCF5235_ETPU_EECR_STF (0x10000000)
1266 #define MCF5235_ETPU_EECR_MDIS (0x40000000)
1267 #define MCF5235_ETPU_EECR_FEND (0x80000000)
1268 #define MCF5235_ETPU_ETBCR_TCR1P(x) (((x)&0x000000FF)<<0)
1269 #define MCF5235_ETPU_ETBCR_TCR1CTL(x) (((x)&0x00000003)<<14)
1270 #define MCF5235_ETPU_ETBCR_TCR2P(x) (((x)&0x0000003F)<<16)
1271 #define MCF5235_ETPU_ETBCR_AM (0x02000000)
1272 #define MCF5235_ETPU_ETBCR_TCRCF(x) (((x)&0x00000003)<<27)
1273 #define MCF5235_ETPU_ETBCR_TCR2CTL(x) (((x)&0x00000007)<<29)
1274 #define MCF5235_ETPU_ETB1R_TCR1(x) (((x)&0x00FFFFFF)<<0)
1275 #define MCF5235_ETPU_ETB2R_TCR2(x) (((x)&0x00FFFFFF)<<0)
1276 #define MCF5235_ETPU_EREDCR_SRV2(x) (((x)&0x0000000F)<<0)
1277 #define MCF5235_ETPU_EREDCR_SERVER_ID2(x) (((x)&0x0000000F)<<8)
1278 #define MCF5235_ETPU_EREDCR_RSC2 (0x00004000)
1279 #define MCF5235_ETPU_EREDCR_REN2 (0x00008000)
1280 #define MCF5235_ETPU_EREDCR_SRV1(x) (((x)&0x0000000F)<<16)
1281 #define MCF5235_ETPU_EREDCR_SERVER_ID1(x) (((x)&0x0000000F)<<24)
1282 #define MCF5235_ETPU_EREDCR_RSC1 (0x40000000)
1283 #define MCF5235_ETPU_EREDCR_REN1 (0x80000000)
1284 #define MCF5235_ETPU_ECISR_CIS0 (0x00000001)
1285 #define MCF5235_ETPU_ECISR_CIS1 (0x00000002)
1286 #define MCF5235_ETPU_ECISR_CIS2 (0x00000004)
1287 #define MCF5235_ETPU_ECISR_CIS3 (0x00000008)
1288 #define MCF5235_ETPU_ECISR_CIS4 (0x00000010)
1289 #define MCF5235_ETPU_ECISR_CIS5 (0x00000020)
1290 #define MCF5235_ETPU_ECISR_CIS6 (0x00000040)
1291 #define MCF5235_ETPU_ECISR_CIS7 (0x00000080)
1292 #define MCF5235_ETPU_ECISR_CIS8 (0x00000100)
1293 #define MCF5235_ETPU_ECISR_CIS9 (0x00000200)
1294 #define MCF5235_ETPU_ECISR_CIS10 (0x00000400)
1295 #define MCF5235_ETPU_ECISR_CIS11 (0x00000800)
1296 #define MCF5235_ETPU_ECISR_CIS12 (0x00001000)
1297 #define MCF5235_ETPU_ECISR_CIS13 (0x00002000)
1298 #define MCF5235_ETPU_ECISR_CIS14 (0x00004000)
1299 #define MCF5235_ETPU_ECISR_CIS15 (0x00008000)
1300 #define MCF5235_ETPU_ECISR_CIS16 (0x00010000)
1301 #define MCF5235_ETPU_ECISR_CIS17 (0x00020000)
1302 #define MCF5235_ETPU_ECISR_CIS18 (0x00040000)
1303 #define MCF5235_ETPU_ECISR_CIS19 (0x00080000)
1304 #define MCF5235_ETPU_ECISR_CIS20 (0x00100000)
1305 #define MCF5235_ETPU_ECISR_CIS21 (0x00200000)
1306 #define MCF5235_ETPU_ECISR_CIS22 (0x00400000)
1307 #define MCF5235_ETPU_ECISR_CIS23 (0x00800000)
1308 #define MCF5235_ETPU_ECISR_CIS24 (0x01000000)
1309 #define MCF5235_ETPU_ECISR_CIS25 (0x02000000)
1310 #define MCF5235_ETPU_ECISR_CIS26 (0x04000000)
1311 #define MCF5235_ETPU_ECISR_CIS27 (0x08000000)
1312 #define MCF5235_ETPU_ECISR_CIS28 (0x10000000)
1313 #define MCF5235_ETPU_ECISR_CIS29 (0x20000000)
1314 #define MCF5235_ETPU_ECISR_CIS30 (0x40000000)
1315 #define MCF5235_ETPU_ECISR_CIS31 (0x80000000)
1316 #define MCF5235_ETPU_ECDTRSR_DTRS0 (0x00000001)
1317 #define MCF5235_ETPU_ECDTRSR_DTRS1 (0x00000002)
1318 #define MCF5235_ETPU_ECDTRSR_DTRS2 (0x00000004)
1319 #define MCF5235_ETPU_ECDTRSR_DTRS3 (0x00000008)
1320 #define MCF5235_ETPU_ECDTRSR_DTRS4 (0x00000010)
1321 #define MCF5235_ETPU_ECDTRSR_DTRS5 (0x00000020)
1322 #define MCF5235_ETPU_ECDTRSR_DTRS6 (0x00000040)
1323 #define MCF5235_ETPU_ECDTRSR_DTRS7 (0x00000080)
1324 #define MCF5235_ETPU_ECDTRSR_DTRS8 (0x00000100)
1325 #define MCF5235_ETPU_ECDTRSR_DTRS9 (0x00000200)
1326 #define MCF5235_ETPU_ECDTRSR_DTRS10 (0x00000400)
1327 #define MCF5235_ETPU_ECDTRSR_DTRS11 (0x00000800)
1328 #define MCF5235_ETPU_ECDTRSR_DTRS12 (0x00001000)
1329 #define MCF5235_ETPU_ECDTRSR_DTRS13 (0x00002000)
1330 #define MCF5235_ETPU_ECDTRSR_DTRS14 (0x00004000)
1331 #define MCF5235_ETPU_ECDTRSR_DTRS15 (0x00008000)
1332 #define MCF5235_ETPU_ECDTRSR_DTRS16 (0x00010000)
1333 #define MCF5235_ETPU_ECDTRSR_DTRS17 (0x00020000)
1334 #define MCF5235_ETPU_ECDTRSR_DTRS18 (0x00040000)
1335 #define MCF5235_ETPU_ECDTRSR_DTRS19 (0x00080000)
1336 #define MCF5235_ETPU_ECDTRSR_DTRS20 (0x00100000)
1337 #define MCF5235_ETPU_ECDTRSR_DTRS21 (0x00200000)
1338 #define MCF5235_ETPU_ECDTRSR_DTRS22 (0x00400000)
1339 #define MCF5235_ETPU_ECDTRSR_DTRS23 (0x00800000)
1340 #define MCF5235_ETPU_ECDTRSR_DTRS24 (0x01000000)
1341 #define MCF5235_ETPU_ECDTRSR_DTRS25 (0x02000000)
1342 #define MCF5235_ETPU_ECDTRSR_DTRS26 (0x04000000)
1343 #define MCF5235_ETPU_ECDTRSR_DTRS27 (0x08000000)
1344 #define MCF5235_ETPU_ECDTRSR_DTRS28 (0x10000000)
1345 #define MCF5235_ETPU_ECDTRSR_DTRS29 (0x20000000)
1346 #define MCF5235_ETPU_ECDTRSR_DTRS30 (0x40000000)
1347 #define MCF5235_ETPU_ECDTRSR_DTRS31 (0x80000000)
1348 #define MCF5235_ETPU_ECIOSR_CIOS0 (0x00000001)
1349 #define MCF5235_ETPU_ECIOSR_CIOS1 (0x00000002)
1350 #define MCF5235_ETPU_ECIOSR_CIOS2 (0x00000004)
1351 #define MCF5235_ETPU_ECIOSR_CIOS3 (0x00000008)
1352 #define MCF5235_ETPU_ECIOSR_CIOS4 (0x00000010)
1353 #define MCF5235_ETPU_ECIOSR_CIOS5 (0x00000020)
1354 #define MCF5235_ETPU_ECIOSR_CIOS6 (0x00000040)
1355 #define MCF5235_ETPU_ECIOSR_CIOS7 (0x00000080)
1356 #define MCF5235_ETPU_ECIOSR_CIOS8 (0x00000100)
1357 #define MCF5235_ETPU_ECIOSR_CIOS9 (0x00000200)
1358 #define MCF5235_ETPU_ECIOSR_CIOS10 (0x00000400)
1359 #define MCF5235_ETPU_ECIOSR_CIOS11 (0x00000800)
1360 #define MCF5235_ETPU_ECIOSR_CIOS12 (0x00001000)
1361 #define MCF5235_ETPU_ECIOSR_CIOS13 (0x00002000)
1362 #define MCF5235_ETPU_ECIOSR_CIOS14 (0x00004000)
1363 #define MCF5235_ETPU_ECIOSR_CIOS15 (0x00008000)
1364 #define MCF5235_ETPU_ECIOSR_CIOS16 (0x00010000)
1365 #define MCF5235_ETPU_ECIOSR_CIOS17 (0x00020000)
1366 #define MCF5235_ETPU_ECIOSR_CIOS18 (0x00040000)
1367 #define MCF5235_ETPU_ECIOSR_CIOS19 (0x00080000)
1368 #define MCF5235_ETPU_ECIOSR_CIOS20 (0x00100000)
1369 #define MCF5235_ETPU_ECIOSR_CIOS21 (0x00200000)
1370 #define MCF5235_ETPU_ECIOSR_CIOS22 (0x00400000)
1371 #define MCF5235_ETPU_ECIOSR_CIOS23 (0x00800000)
1372 #define MCF5235_ETPU_ECIOSR_CIOS24 (0x01000000)
1373 #define MCF5235_ETPU_ECIOSR_CIOS25 (0x02000000)
1374 #define MCF5235_ETPU_ECIOSR_CIOS26 (0x04000000)
1375 #define MCF5235_ETPU_ECIOSR_CIOS27 (0x08000000)
1376 #define MCF5235_ETPU_ECIOSR_CIOS28 (0x10000000)
1377 #define MCF5235_ETPU_ECIOSR_CIOS29 (0x20000000)
1378 #define MCF5235_ETPU_ECIOSR_CIOS30 (0x40000000)
1379 #define MCF5235_ETPU_ECIOSR_CIOS31 (0x80000000)
1380 #define MCF5235_ETPU_ECDTROSR_DTROS0 (0x00000001)
1381 #define MCF5235_ETPU_ECDTROSR_DTROS1 (0x00000002)
1382 #define MCF5235_ETPU_ECDTROSR_DTROS2 (0x00000004)
1383 #define MCF5235_ETPU_ECDTROSR_DTROS3 (0x00000008)
1384 #define MCF5235_ETPU_ECDTROSR_DTROS4 (0x00000010)
1385 #define MCF5235_ETPU_ECDTROSR_DTROS5 (0x00000020)
1386 #define MCF5235_ETPU_ECDTROSR_DTROS6 (0x00000040)
1387 #define MCF5235_ETPU_ECDTROSR_DTROS7 (0x00000080)
1388 #define MCF5235_ETPU_ECDTROSR_DTROS8 (0x00000100)
1389 #define MCF5235_ETPU_ECDTROSR_DTROS9 (0x00000200)
1390 #define MCF5235_ETPU_ECDTROSR_DTROS10 (0x00000400)
1391 #define MCF5235_ETPU_ECDTROSR_DTROS11 (0x00000800)
1392 #define MCF5235_ETPU_ECDTROSR_DTROS12 (0x00001000)
1393 #define MCF5235_ETPU_ECDTROSR_DTROS13 (0x00002000)
1394 #define MCF5235_ETPU_ECDTROSR_DTROS14 (0x00004000)
1395 #define MCF5235_ETPU_ECDTROSR_DTROS15 (0x00008000)
1396 #define MCF5235_ETPU_ECDTROSR_DTROS16 (0x00010000)
1397 #define MCF5235_ETPU_ECDTROSR_DTROS17 (0x00020000)
1398 #define MCF5235_ETPU_ECDTROSR_DTROS18 (0x00040000)
1399 #define MCF5235_ETPU_ECDTROSR_DTROS19 (0x00080000)
1400 #define MCF5235_ETPU_ECDTROSR_DTROS20 (0x00100000)
1401 #define MCF5235_ETPU_ECDTROSR_DTROS21 (0x00200000)
1402 #define MCF5235_ETPU_ECDTROSR_DTROS22 (0x00400000)
1403 #define MCF5235_ETPU_ECDTROSR_DTROS23 (0x00800000)
1404 #define MCF5235_ETPU_ECDTROSR_DTROS24 (0x01000000)
1405 #define MCF5235_ETPU_ECDTROSR_DTROS25 (0x02000000)
1406 #define MCF5235_ETPU_ECDTROSR_DTROS26 (0x04000000)
1407 #define MCF5235_ETPU_ECDTROSR_DTROS27 (0x08000000)
1408 #define MCF5235_ETPU_ECDTROSR_DTROS28 (0x10000000)
1409 #define MCF5235_ETPU_ECDTROSR_DTROS29 (0x20000000)
1410 #define MCF5235_ETPU_ECDTROSR_DTROS30 (0x40000000)
1411 #define MCF5235_ETPU_ECDTROSR_DTROS31 (0x80000000)
1412 #define MCF5235_ETPU_ECIER_CIE0 (0x00000001)
1413 #define MCF5235_ETPU_ECIER_CIE1 (0x00000002)
1414 #define MCF5235_ETPU_ECIER_CIE2 (0x00000004)
1415 #define MCF5235_ETPU_ECIER_CIE3 (0x00000008)
1416 #define MCF5235_ETPU_ECIER_CIE4 (0x00000010)
1417 #define MCF5235_ETPU_ECIER_CIE5 (0x00000020)
1418 #define MCF5235_ETPU_ECIER_CIE6 (0x00000040)
1419 #define MCF5235_ETPU_ECIER_CIE7 (0x00000080)
1420 #define MCF5235_ETPU_ECIER_CIE8 (0x00000100)
1421 #define MCF5235_ETPU_ECIER_CIE9 (0x00000200)
1422 #define MCF5235_ETPU_ECIER_CIE10 (0x00000400)
1423 #define MCF5235_ETPU_ECIER_CIE11 (0x00000800)
1424 #define MCF5235_ETPU_ECIER_CIE12 (0x00001000)
1425 #define MCF5235_ETPU_ECIER_CIE13 (0x00002000)
1426 #define MCF5235_ETPU_ECIER_CIE14 (0x00004000)
1427 #define MCF5235_ETPU_ECIER_CIE15 (0x00008000)
1428 #define MCF5235_ETPU_ECIER_CIE16 (0x00010000)
1429 #define MCF5235_ETPU_ECIER_CIE17 (0x00020000)
1430 #define MCF5235_ETPU_ECIER_CIE18 (0x00040000)
1431 #define MCF5235_ETPU_ECIER_CIE19 (0x00080000)
1432 #define MCF5235_ETPU_ECIER_CIE20 (0x00100000)
1433 #define MCF5235_ETPU_ECIER_CIE21 (0x00200000)
1434 #define MCF5235_ETPU_ECIER_CIE22 (0x00400000)
1435 #define MCF5235_ETPU_ECIER_CIE23 (0x00800000)
1436 #define MCF5235_ETPU_ECIER_CIE24 (0x01000000)
1437 #define MCF5235_ETPU_ECIER_CIE25 (0x02000000)
1438 #define MCF5235_ETPU_ECIER_CIE26 (0x04000000)
1439 #define MCF5235_ETPU_ECIER_CIE27 (0x08000000)
1440 #define MCF5235_ETPU_ECIER_CIE28 (0x10000000)
1441 #define MCF5235_ETPU_ECIER_CIE29 (0x20000000)
1442 #define MCF5235_ETPU_ECIER_CIE30 (0x40000000)
1443 #define MCF5235_ETPU_ECIER_CIE31 (0x80000000)
1444 #define MCF5235_ETPU_ECDTRER_DTRE0 (0x00000001)
1445 #define MCF5235_ETPU_ECDTRER_DTRE1 (0x00000002)
1446 #define MCF5235_ETPU_ECDTRER_DTRE2 (0x00000004)
1447 #define MCF5235_ETPU_ECDTRER_DTRE3 (0x00000008)
1448 #define MCF5235_ETPU_ECDTRER_DTRE4 (0x00000010)
1449 #define MCF5235_ETPU_ECDTRER_DTRE5 (0x00000020)
1450 #define MCF5235_ETPU_ECDTRER_DTRE6 (0x00000040)
1451 #define MCF5235_ETPU_ECDTRER_DTRE7 (0x00000080)
1452 #define MCF5235_ETPU_ECDTRER_DTRE8 (0x00000100)
1453 #define MCF5235_ETPU_ECDTRER_DTRE9 (0x00000200)
1454 #define MCF5235_ETPU_ECDTRER_DTRE10 (0x00000400)
1455 #define MCF5235_ETPU_ECDTRER_DTRE11 (0x00000800)
1456 #define MCF5235_ETPU_ECDTRER_DTRE12 (0x00001000)
1457 #define MCF5235_ETPU_ECDTRER_DTRE13 (0x00002000)
1458 #define MCF5235_ETPU_ECDTRER_DTRE14 (0x00004000)
1459 #define MCF5235_ETPU_ECDTRER_DTRE15 (0x00008000)
1460 #define MCF5235_ETPU_ECDTRER_DTRE16 (0x00010000)
1461 #define MCF5235_ETPU_ECDTRER_DTRE17 (0x00020000)
1462 #define MCF5235_ETPU_ECDTRER_DTRE18 (0x00040000)
1463 #define MCF5235_ETPU_ECDTRER_DTRE19 (0x00080000)
1464 #define MCF5235_ETPU_ECDTRER_DTRE20 (0x00100000)
1465 #define MCF5235_ETPU_ECDTRER_DTRE21 (0x00200000)
1466 #define MCF5235_ETPU_ECDTRER_DTRE22 (0x00400000)
1467 #define MCF5235_ETPU_ECDTRER_DTRE23 (0x00800000)
1468 #define MCF5235_ETPU_ECDTRER_DTRE24 (0x01000000)
1469 #define MCF5235_ETPU_ECDTRER_DTRE25 (0x02000000)
1470 #define MCF5235_ETPU_ECDTRER_DTRE26 (0x04000000)
1471 #define MCF5235_ETPU_ECDTRER_DTRE27 (0x08000000)
1472 #define MCF5235_ETPU_ECDTRER_DTRE28 (0x10000000)
1473 #define MCF5235_ETPU_ECDTRER_DTRE29 (0x20000000)
1474 #define MCF5235_ETPU_ECDTRER_DTRE30 (0x40000000)
1475 #define MCF5235_ETPU_ECDTRER_DTRE31 (0x80000000)
1476 #define MCF5235_ETPU_ECPSSR_SR0 (0x00000001)
1477 #define MCF5235_ETPU_ECPSSR_SR1 (0x00000002)
1478 #define MCF5235_ETPU_ECPSSR_SR2 (0x00000004)
1479 #define MCF5235_ETPU_ECPSSR_SR3 (0x00000008)
1480 #define MCF5235_ETPU_ECPSSR_SR4 (0x00000010)
1481 #define MCF5235_ETPU_ECPSSR_SR5 (0x00000020)
1482 #define MCF5235_ETPU_ECPSSR_SR6 (0x00000040)
1483 #define MCF5235_ETPU_ECPSSR_SR7 (0x00000080)
1484 #define MCF5235_ETPU_ECPSSR_SR8 (0x00000100)
1485 #define MCF5235_ETPU_ECPSSR_SR9 (0x00000200)
1486 #define MCF5235_ETPU_ECPSSR_SR10 (0x00000400)
1487 #define MCF5235_ETPU_ECPSSR_SR11 (0x00000800)
1488 #define MCF5235_ETPU_ECPSSR_SR12 (0x00001000)
1489 #define MCF5235_ETPU_ECPSSR_SR13 (0x00002000)
1490 #define MCF5235_ETPU_ECPSSR_SR14 (0x00004000)
1491 #define MCF5235_ETPU_ECPSSR_SR15 (0x00008000)
1492 #define MCF5235_ETPU_ECPSSR_SR16 (0x00010000)
1493 #define MCF5235_ETPU_ECPSSR_SR17 (0x00020000)
1494 #define MCF5235_ETPU_ECPSSR_SR18 (0x00040000)
1495 #define MCF5235_ETPU_ECPSSR_SR19 (0x00080000)
1496 #define MCF5235_ETPU_ECPSSR_SR20 (0x00100000)
1497 #define MCF5235_ETPU_ECPSSR_SR21 (0x00200000)
1498 #define MCF5235_ETPU_ECPSSR_SR22 (0x00400000)
1499 #define MCF5235_ETPU_ECPSSR_SR23 (0x00800000)
1500 #define MCF5235_ETPU_ECPSSR_SR24 (0x01000000)
1501 #define MCF5235_ETPU_ECPSSR_SR25 (0x02000000)
1502 #define MCF5235_ETPU_ECPSSR_SR26 (0x04000000)
1503 #define MCF5235_ETPU_ECPSSR_SR27 (0x08000000)
1504 #define MCF5235_ETPU_ECPSSR_SR28 (0x10000000)
1505 #define MCF5235_ETPU_ECPSSR_SR29 (0x20000000)
1506 #define MCF5235_ETPU_ECPSSR_SR30 (0x40000000)
1507 #define MCF5235_ETPU_ECPSSR_SR31 (0x80000000)
1508 #define MCF5235_ETPU_ECSSR_SS0 (0x00000001)
1509 #define MCF5235_ETPU_ECSSR_SS1 (0x00000002)
1510 #define MCF5235_ETPU_ECSSR_SS2 (0x00000004)
1511 #define MCF5235_ETPU_ECSSR_SS3 (0x00000008)
1512 #define MCF5235_ETPU_ECSSR_SS4 (0x00000010)
1513 #define MCF5235_ETPU_ECSSR_SS5 (0x00000020)
1514 #define MCF5235_ETPU_ECSSR_SS6 (0x00000040)
1515 #define MCF5235_ETPU_ECSSR_SS7 (0x00000080)
1516 #define MCF5235_ETPU_ECSSR_SS8 (0x00000100)
1517 #define MCF5235_ETPU_ECSSR_SS9 (0x00000200)
1518 #define MCF5235_ETPU_ECSSR_SS10 (0x00000400)
1519 #define MCF5235_ETPU_ECSSR_SS11 (0x00000800)
1520 #define MCF5235_ETPU_ECSSR_SS12 (0x00001000)
1521 #define MCF5235_ETPU_ECSSR_SS13 (0x00002000)
1522 #define MCF5235_ETPU_ECSSR_SS14 (0x00004000)
1523 #define MCF5235_ETPU_ECSSR_SS15 (0x00008000)
1524 #define MCF5235_ETPU_ECSSR_SS16 (0x00010000)
1525 #define MCF5235_ETPU_ECSSR_SS17 (0x00020000)
1526 #define MCF5235_ETPU_ECSSR_SS18 (0x00040000)
1527 #define MCF5235_ETPU_ECSSR_SS19 (0x00080000)
1528 #define MCF5235_ETPU_ECSSR_SS20 (0x00100000)
1529 #define MCF5235_ETPU_ECSSR_SS21 (0x00200000)
1530 #define MCF5235_ETPU_ECSSR_SS22 (0x00400000)
1531 #define MCF5235_ETPU_ECSSR_SS23 (0x00800000)
1532 #define MCF5235_ETPU_ECSSR_SS24 (0x01000000)
1533 #define MCF5235_ETPU_ECSSR_SS25 (0x02000000)
1534 #define MCF5235_ETPU_ECSSR_SS26 (0x04000000)
1535 #define MCF5235_ETPU_ECSSR_SS27 (0x08000000)
1536 #define MCF5235_ETPU_ECSSR_SS28 (0x10000000)
1537 #define MCF5235_ETPU_ECSSR_SS29 (0x20000000)
1538 #define MCF5235_ETPU_ECSSR_SS30 (0x40000000)
1539 #define MCF5235_ETPU_ECSSR_SS31 (0x80000000)
1540 #define MCF5235_ETPU_ECnSCR_FM(x) (((x)&0x00000003)<<0)
1541 #define MCF5235_ETPU_ECnSCR_OBE (0x00002000)
1542 #define MCF5235_ETPU_ECnSCR_OPS (0x00004000)
1543 #define MCF5235_ETPU_ECnSCR_IPS (0x00008000)
1544 #define MCF5235_ETPU_ECnSCR_DTROS (0x00400000)
1545 #define MCF5235_ETPU_ECnSCR_DTRS (0x00800000)
1546 #define MCF5235_ETPU_ECnSCR_CIOS (0x40000000)
1547 #define MCF5235_ETPU_ECnSCR_CIS (0x80000000)
1548 #define MCF5235_ETPU_ECnCR_CPBA(x) (((x)&0x000007FF)<<0)
1549 #define MCF5235_ETPU_ECnCR_OPOL (0x00004000)
1550 #define MCF5235_ETPU_ECnCR_ODIS (0x00008000)
1551 #define MCF5235_ETPU_ECnCR_CFS(x) (((x)&0x0000001F)<<16)
1552 #define MCF5235_ETPU_ECnCR_ETCS (0x01000000)
1553 #define MCF5235_ETPU_ECnCR_CPR(x) (((x)&0x00000003)<<28)
1554 #define MCF5235_ETPU_ECnCR_DTRE (0x40000000)
1555 #define MCF5235_ETPU_ECnCR_CIE (0x80000000)
1556 #define MCF5235_ETPU_ECnHSSR_HSR(x) (((x)&0x00000007)<<0)
1557 
1558 
1559 /*********************************************************************
1560 *
1561 * Fast Ethernet Controller (FEC)
1562 *
1563 *********************************************************************/
1564 
1565 /* Register read/write macros */
1566 #define MCF5235_FEC_EIR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001004)))
1567 #define MCF5235_FEC_EIMR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001008)))
1568 #define MCF5235_FEC_RDAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001010)))
1569 #define MCF5235_FEC_TDAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001014)))
1570 #define MCF5235_FEC_ECR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001024)))
1571 #define MCF5235_FEC_MMFR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001040)))
1572 #define MCF5235_FEC_MSCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001044)))
1573 #define MCF5235_FEC_MIBC (*(vuint32*)((uintptr_t)__IPSBAR + (0x001064)))
1574 #define MCF5235_FEC_RCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001084)))
1575 #define MCF5235_FEC_TCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x0010C4)))
1576 #define MCF5235_FEC_PALR (*(vuint32*)((uintptr_t)__IPSBAR + (0x0010E4)))
1577 #define MCF5235_FEC_PAUR (*(vuint32*)((uintptr_t)__IPSBAR + (0x0010E8)))
1578 #define MCF5235_FEC_OPD (*(vuint32*)((uintptr_t)__IPSBAR + (0x0010EC)))
1579 #define MCF5235_FEC_IAUR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001118)))
1580 #define MCF5235_FEC_IALR (*(vuint32*)((uintptr_t)__IPSBAR + (0x00111C)))
1581 #define MCF5235_FEC_GAUR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001120)))
1582 #define MCF5235_FEC_GALR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001124)))
1583 #define MCF5235_FEC_TFWR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001144)))
1584 #define MCF5235_FEC_FRBR (*(vuint32*)((uintptr_t)__IPSBAR + (0x00114C)))
1585 #define MCF5235_FEC_FRSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001150)))
1586 #define MCF5235_FEC_ERDSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001180)))
1587 #define MCF5235_FEC_ETDSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001184)))
1588 #define MCF5235_FEC_EMRBR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001188)))
1589 #define MCF5235_FEC_RMON_T_DROP (*(vuint32*)((uintptr_t)__IPSBAR + (0x001200)))
1590 #define MCF5235_FEC_RMON_T_PACKETS (*(vuint32*)((uintptr_t)__IPSBAR + (0x001204)))
1591 #define MCF5235_FEC_RMON_T_BC_PKT (*(vuint32*)((uintptr_t)__IPSBAR + (0x001208)))
1592 #define MCF5235_FEC_RMON_T_MC_PKT (*(vuint32*)((uintptr_t)__IPSBAR + (0x00120C)))
1593 #define MCF5235_FEC_RMON_T_CRC_ALIGN (*(vuint32*)((uintptr_t)__IPSBAR + (0x001210)))
1594 #define MCF5235_FEC_RMON_T_UNDERSIZE (*(vuint32*)((uintptr_t)__IPSBAR + (0x001214)))
1595 #define MCF5235_FEC_RMON_T_OVERSIZE (*(vuint32*)((uintptr_t)__IPSBAR + (0x001218)))
1596 #define MCF5235_FEC_RMON_T_FRAG (*(vuint32*)((uintptr_t)__IPSBAR + (0x00121C)))
1597 #define MCF5235_FEC_RMON_T_JAB (*(vuint32*)((uintptr_t)__IPSBAR + (0x001220)))
1598 #define MCF5235_FEC_RMON_T_COL (*(vuint32*)((uintptr_t)__IPSBAR + (0x001224)))
1599 #define MCF5235_FEC_RMON_T_P64 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001228)))
1600 #define MCF5235_FEC_RMON_T_P65TO127 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00122C)))
1601 #define MCF5235_FEC_RMON_T_P128TO255 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001230)))
1602 #define MCF5235_FEC_RMON_T_P256TO511 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001234)))
1603 #define MCF5235_FEC_RMON_T_P512TO1023 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001238)))
1604 #define MCF5235_FEC_RMON_T_P1024TO2047 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00123C)))
1605 #define MCF5235_FEC_RMON_T_P_GTE2048 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001240)))
1606 #define MCF5235_FEC_RMON_T_OCTETS (*(vuint32*)((uintptr_t)__IPSBAR + (0x001244)))
1607 #define MCF5235_FEC_IEEE_T_DROP (*(vuint32*)((uintptr_t)__IPSBAR + (0x001248)))
1608 #define MCF5235_FEC_IEEE_T_FRAME_OK (*(vuint32*)((uintptr_t)__IPSBAR + (0x00124C)))
1609 #define MCF5235_FEC_IEEE_T_1COL (*(vuint32*)((uintptr_t)__IPSBAR + (0x001250)))
1610 #define MCF5235_FEC_IEEE_T_MCOL (*(vuint32*)((uintptr_t)__IPSBAR + (0x001254)))
1611 #define MCF5235_FEC_IEEE_T_DEF (*(vuint32*)((uintptr_t)__IPSBAR + (0x001258)))
1612 #define MCF5235_FEC_IEEE_T_LCOL (*(vuint32*)((uintptr_t)__IPSBAR + (0x00125C)))
1613 #define MCF5235_FEC_IEEE_T_EXCOL (*(vuint32*)((uintptr_t)__IPSBAR + (0x001260)))
1614 #define MCF5235_FEC_IEEE_T_MACERR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001264)))
1615 #define MCF5235_FEC_IEEE_T_CSERR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001268)))
1616 #define MCF5235_FEC_IEEE_T_SQE (*(vuint32*)((uintptr_t)__IPSBAR + (0x00126C)))
1617 #define MCF5235_FEC_IEEE_T_FDXFC (*(vuint32*)((uintptr_t)__IPSBAR + (0x001270)))
1618 #define MCF5235_FEC_IEEE_T_OCTETS_OK (*(vuint32*)((uintptr_t)__IPSBAR + (0x001274)))
1619 #define MCF5235_FEC_RMON_R_PACKETS (*(vuint32*)((uintptr_t)__IPSBAR + (0x001284)))
1620 #define MCF5235_FEC_RMON_R_BC_PKT (*(vuint32*)((uintptr_t)__IPSBAR + (0x001288)))
1621 #define MCF5235_FEC_RMON_R_MC_PKT (*(vuint32*)((uintptr_t)__IPSBAR + (0x00128C)))
1622 #define MCF5235_FEC_RMON_R_CRC_ALIGN (*(vuint32*)((uintptr_t)__IPSBAR + (0x001290)))
1623 #define MCF5235_FEC_RMON_R_UNDERSIZE (*(vuint32*)((uintptr_t)__IPSBAR + (0x001294)))
1624 #define MCF5235_FEC_RMON_R_OVERSIZE (*(vuint32*)((uintptr_t)__IPSBAR + (0x001298)))
1625 #define MCF5235_FEC_RMON_R_FRAG (*(vuint32*)((uintptr_t)__IPSBAR + (0x00129C)))
1626 #define MCF5235_FEC_RMON_R_JAB (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012A0)))
1627 #define MCF5235_FEC_RMON_R_RESVD_0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012A4)))
1628 #define MCF5235_FEC_RMON_R_P64 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012A8)))
1629 #define MCF5235_FEC_RMON_R_P65T0127 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012AC)))
1630 #define MCF5235_FEC_RMON_R_P128TO255 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012B0)))
1631 #define MCF5235_FEC_RMON_R_P256TO511 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012B4)))
1632 #define MCF5235_FEC_RMON_R_P512TO1023 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012B8)))
1633 #define MCF5235_FEC_RMON_R_GTE2048 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012C0)))
1634 #define MCF5235_FEC_RMON_R_P1024TO2047 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012BC)))
1635 #define MCF5235_FEC_RMON_R_OCTETS (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012C4)))
1636 #define MCF5235_FEC_IEEE_R_DROP (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012C8)))
1637 #define MCF5235_FEC_IEEE_R_FRAME_OK (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012CC)))
1638 #define MCF5235_FEC_IEEE_R_CRC (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012D0)))
1639 #define MCF5235_FEC_IEEE_R_ALIGN (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012D4)))
1640 #define MCF5235_FEC_IEEE_R_MACERR (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012D8)))
1641 #define MCF5235_FEC_IEEE_R_FDXFC (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012DC)))
1642 #define MCF5235_FEC_IEEE_R_OCTETS_OK (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012E0)))
1643 
1644 /* Bit definitions and macros for MCF5235_FEC_EIR */
1645 #define MCF5235_FEC_EIR_UN (0x00080000)
1646 #define MCF5235_FEC_EIR_RL (0x00100000)
1647 #define MCF5235_FEC_EIR_LC (0x00200000)
1648 #define MCF5235_FEC_EIR_EBERR (0x00400000)
1649 #define MCF5235_FEC_EIR_MII (0x00800000)
1650 #define MCF5235_FEC_EIR_RXB (0x01000000)
1651 #define MCF5235_FEC_EIR_RXF (0x02000000)
1652 #define MCF5235_FEC_EIR_TXB (0x04000000)
1653 #define MCF5235_FEC_EIR_TXF (0x08000000)
1654 #define MCF5235_FEC_EIR_GRA (0x10000000)
1655 #define MCF5235_FEC_EIR_BABT (0x20000000)
1656 #define MCF5235_FEC_EIR_BABR (0x40000000)
1657 #define MCF5235_FEC_EIR_HBERR (0x80000000)
1658 #define MCF5235_FEC_EIMR_UN (0x00080000)
1659 #define MCF5235_FEC_EIMR_RL (0x00100000)
1660 #define MCF5235_FEC_EIMR_LC (0x00200000)
1661 #define MCF5235_FEC_EIMR_EBERR (0x00400000)
1662 #define MCF5235_FEC_EIMR_MII (0x00800000)
1663 #define MCF5235_FEC_EIMR_RXB (0x01000000)
1664 #define MCF5235_FEC_EIMR_RXF (0x02000000)
1665 #define MCF5235_FEC_EIMR_TXB (0x04000000)
1666 #define MCF5235_FEC_EIMR_TXF (0x08000000)
1667 #define MCF5235_FEC_EIMR_GRA (0x10000000)
1668 #define MCF5235_FEC_EIMR_BABT (0x20000000)
1669 #define MCF5235_FEC_EIMR_BABR (0x40000000)
1670 #define MCF5235_FEC_EIMR_HBERR (0x80000000)
1671 #define MCF5235_FEC_RDAR_R_DES_ACTIVE (0x01000000)
1672 #define MCF5235_FEC_TDAR_X_DES_ACTIVE (0x01000000)
1673 #define MCF5235_FEC_ECR_RESET (0x00000001)
1674 #define MCF5235_FEC_ECR_ETHER_EN (0x00000002)
1675 #define MCF5235_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0)
1676 #define MCF5235_FEC_MMFR_TA(x) (((x)&0x00000003)<<16)
1677 #define MCF5235_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18)
1678 #define MCF5235_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23)
1679 #define MCF5235_FEC_MMFR_OP(x) (((x)&0x00000003)<<28)
1680 #define MCF5235_FEC_MMFR_ST(x) (((x)&0x00000003)<<30)
1681 #define MCF5235_FEC_MMFR_ST_01 (0x40000000)
1682 #define MCF5235_FEC_MMFR_OP_READ (0x20000000)
1683 #define MCF5235_FEC_MMFR_OP_WRITE (0x10000000)
1684 #define MCF5235_FEC_MMFR_TA_10 (0x00020000)
1685 #define MCF5235_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1)
1686 #define MCF5235_FEC_MSCR_DIS_PREAMBLE (0x00000080)
1687 #define MCF5235_FEC_MIBC_MIB_IDLE (0x40000000)
1688 #define MCF5235_FEC_MIBC_MIB_DISABLE (0x80000000)
1689 #define MCF5235_FEC_RCR_LOOP (0x00000001)
1690 #define MCF5235_FEC_RCR_DRT (0x00000002)
1691 #define MCF5235_FEC_RCR_MII_MODE (0x00000004)
1692 #define MCF5235_FEC_RCR_PROM (0x00000008)
1693 #define MCF5235_FEC_RCR_BC_REJ (0x00000010)
1694 #define MCF5235_FEC_RCR_FCE (0x00000020)
1695 #define MCF5235_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16)
1696 #define MCF5235_FEC_TCR_GTS (0x00000001)
1697 #define MCF5235_FEC_TCR_HBC (0x00000002)
1698 #define MCF5235_FEC_TCR_FDEN (0x00000004)
1699 #define MCF5235_FEC_TCR_TFC_PAUSE (0x00000008)
1700 #define MCF5235_FEC_TCR_RFC_PAUSE (0x00000010)
1701 #define MCF5235_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0)
1702 #define MCF5235_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16)
1703 #define MCF5235_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
1704 #define MCF5235_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
1705 #define MCF5235_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0)
1706 #define MCF5235_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2)
1707 #define MCF5235_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2)
1708 #define MCF5235_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
1709 #define MCF5235_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
1710 #define MCF5235_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4)
1711 #define MCF5235_FEC_TxBD_R 0x8000
1712 #define MCF5235_FEC_TxBD_BUSY 0x4000
1713 #define MCF5235_FEC_TxBD_TO1 0x4000
1714 #define MCF5235_FEC_TxBD_W 0x2000
1715 #define MCF5235_FEC_TxBD_TO2 0x1000
1716 #define MCF5235_FEC_TxBD_FIRST 0x1000
1717 #define MCF5235_FEC_TxBD_L 0x0800
1718 #define MCF5235_FEC_TxBD_TC 0x0400
1719 #define MCF5235_FEC_TxBD_DEF 0x0200
1720 #define MCF5235_FEC_TxBD_HB 0x0100
1721 #define MCF5235_FEC_TxBD_LC 0x0080
1722 #define MCF5235_FEC_TxBD_RL 0x0040
1723 #define MCF5235_FEC_TxBD_UN 0x0002
1724 #define MCF5235_FEC_TxBD_CSL 0x0001
1725 #define MCF5235_FEC_RxBD_E 0x8000
1726 #define MCF5235_FEC_RxBD_INUSE 0x4000
1727 #define MCF5235_FEC_RxBD_R01 0x4000
1728 #define MCF5235_FEC_RxBD_W 0x2000
1729 #define MCF5235_FEC_RxBD_R02 0x1000
1730 #define MCF5235_FEC_RxBD_L 0x0800
1731 #define MCF5235_FEC_RxBD_M 0x0100
1732 #define MCF5235_FEC_RxBD_BC 0x0080
1733 #define MCF5235_FEC_RxBD_MC 0x0040
1734 #define MCF5235_FEC_RxBD_LG 0x0020
1735 #define MCF5235_FEC_RxBD_NO 0x0010
1736 #define MCF5235_FEC_RxBD_CR 0x0004
1737 #define MCF5235_FEC_RxBD_OV 0x0002
1738 #define MCF5235_FEC_RxBD_TR 0x0001
1739 
1740 /************************************************************
1741 *
1742 * Clock
1743 *************************************************************/
1744 /* Register read/write macros */
1745 #define MCF5235_FMPLL_SYNCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x120000)))
1746 #define MCF5235_FMPLL_SYNSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x120004)))
1747 
1748 /* Bit definitions and macros for MCF5235_FMPLL_SYNCR */
1749 #define MCF5235_FMPLL_SYNCR_EXP(x) (((x)&0x000003FF)<<0)
1750 #define MCF5235_FMPLL_SYNCR_DEPTH(x) (((x)&0x00000003)<<10)
1751 #define MCF5235_FMPLL_SYNCR_RATE (0x00001000)
1752 #define MCF5235_FMPLL_SYNCR_LOCIRQ (0x00002000)
1753 #define MCF5235_FMPLL_SYNCR_LOLIRQ (0x00004000)
1754 #define MCF5235_FMPLL_SYNCR_DISCLK (0x00008000)
1755 #define MCF5235_FMPLL_SYNCR_LOCRE (0x00010000)
1756 #define MCF5235_FMPLL_SYNCR_LOLRE (0x00020000)
1757 #define MCF5235_FMPLL_SYNCR_LOCEN (0x00040000)
1758 #define MCF5235_FMPLL_SYNCR_RFD(x) (((x)&0x00000007)<<19)
1759 #define MCF5235_FMPLL_SYNCR_MFD(x) (((x)&0x00000007)<<24)
1760 #define MCF5235_FMPLL_SYNSR_CALPASS (0x00000001)
1761 #define MCF5235_FMPLL_SYNSR_CALDONE (0x00000002)
1762 #define MCF5235_FMPLL_SYNSR_LOCF (0x00000004)
1763 #define MCF5235_FMPLL_SYNSR_LOCK (0x00000008)
1764 #define MCF5235_FMPLL_SYNSR_LOCKS (0x00000010)
1765 #define MCF5235_FMPLL_SYNSR_PLLREF (0x00000020)
1766 #define MCF5235_FMPLL_SYNSR_PLLSEL (0x00000040)
1767 #define MCF5235_FMPLL_SYNSR_MODE (0x00000080)
1768 #define MCF5235_FMPLL_SYNSR_LOC (0x00000100)
1769 #define MCF5235_FMPLL_SYNSR_LOLF (0x00000200)
1770 
1771 
1772 /*********************************************************************
1773 *
1774 * General Purpose I/O (GPIO)
1775 *
1776 *********************************************************************/
1777 
1778 /* Register read/write macros */
1779 #define MCF5235_GPIO_PODR_ADDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100000)))
1780 #define MCF5235_GPIO_PODR_DATAH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100001)))
1781 #define MCF5235_GPIO_PODR_DATAL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100002)))
1782 #define MCF5235_GPIO_PODR_BUSCTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100003)))
1783 #define MCF5235_GPIO_PODR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100004)))
1784 #define MCF5235_GPIO_PODR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100005)))
1785 #define MCF5235_GPIO_PODR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100006)))
1786 #define MCF5235_GPIO_PODR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100007)))
1787 #define MCF5235_GPIO_PODR_UARTH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100008)))
1788 #define MCF5235_GPIO_PODR_UARTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100009)))
1789 #define MCF5235_GPIO_PODR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10000A)))
1790 #define MCF5235_GPIO_PODR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10000B)))
1791 #define MCF5235_GPIO_PODR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10000C)))
1792 #define MCF5235_GPIO_PDDR_APDDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100010)))
1793 #define MCF5235_GPIO_PDDR_DATAH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100011)))
1794 #define MCF5235_GPIO_PDDR_DATAL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100012)))
1795 #define MCF5235_GPIO_PDDR_BUSCTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100013)))
1796 #define MCF5235_GPIO_PDDR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100014)))
1797 #define MCF5235_GPIO_PDDR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100015)))
1798 #define MCF5235_GPIO_PDDR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100016)))
1799 #define MCF5235_GPIO_PDDR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100017)))
1800 #define MCF5235_GPIO_PDDR_UARTH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100018)))
1801 #define MCF5235_GPIO_PDDR_UARTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100019)))
1802 #define MCF5235_GPIO_PDDR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10001A)))
1803 #define MCF5235_GPIO_PDDR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10001B)))
1804 #define MCF5235_GPIO_PDDR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10001C)))
1805 #define MCF5235_GPIO_PPDSDR_ADDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100020)))
1806 #define MCF5235_GPIO_PPDSDR_DATAH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100021)))
1807 #define MCF5235_GPIO_PPDSDR_DATAL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100022)))
1808 #define MCF5235_GPIO_PPDSDR_BUSCTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100023)))
1809 #define MCF5235_GPIO_PPDSDR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100024)))
1810 #define MCF5235_GPIO_PPDSDR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100027)))
1811 #define MCF5235_GPIO_PPDSDR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100025)))
1812 #define MCF5235_GPIO_PPDSDR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100026)))
1813 #define MCF5235_GPIO_PPDSDR_UARTH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100028)))
1814 #define MCF5235_GPIO_PPDSDR_UARTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100029)))
1815 #define MCF5235_GPIO_PPDSDR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10002A)))
1816 #define MCF5235_GPIO_PPDSDR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10002B)))
1817 #define MCF5235_GPIO_PPDSDR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10002C)))
1818 #define MCF5235_GPIO_PCLRR_ADDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100030)))
1819 #define MCF5235_GPIO_PCLRR_DATAH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100031)))
1820 #define MCF5235_GPIO_PCLRR_DATAL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100032)))
1821 #define MCF5235_GPIO_PCLRR_BUSCTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100033)))
1822 #define MCF5235_GPIO_PCLRR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100034)))
1823 #define MCF5235_GPIO_PCLRR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100035)))
1824 #define MCF5235_GPIO_PCLRR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100036)))
1825 #define MCF5235_GPIO_PCLRR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100037)))
1826 #define MCF5235_GPIO_PCLRR_UARTH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100038)))
1827 #define MCF5235_GPIO_PCLRR_UARTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100039)))
1828 #define MCF5235_GPIO_PCLRR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10003A)))
1829 #define MCF5235_GPIO_PCLRR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10003B)))
1830 #define MCF5235_GPIO_PCLRR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10003C)))
1831 #define MCF5235_GPIO_PAR_AD (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100040)))
1832 #define MCF5235_GPIO_PAR_BUSCTL (*(vuint16*)((uintptr_t)__IPSBAR + (0x100042)))
1833 #define MCF5235_GPIO_PAR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100044)))
1834 #define MCF5235_GPIO_PAR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100045)))
1835 #define MCF5235_GPIO_PAR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100046)))
1836 #define MCF5235_GPIO_PAR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100047)))
1837 #define MCF5235_GPIO_UART (*(vuint16*)((uintptr_t)__IPSBAR + (0x100048)))
1838 #define MCF5235_GPIO_PAR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10004A)))
1839 #define MCF5235_GPIO_PAR_TIMER (*(vuint16*)((uintptr_t)__IPSBAR + (0x10004C)))
1840 #define MCF5235_GPIO_PAR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10004E)))
1841 #define MCF5235_GPIO_DSCR_EIM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100050)))
1842 #define MCF5235_GPIO_DSCR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100051)))
1843 #define MCF5235_GPIO_DSCR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100052)))
1844 #define MCF5235_GPIO_DSCR_UART (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100053)))
1845 #define MCF5235_GPIO_DSCR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100054)))
1846 #define MCF5235_GPIO_DSCR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100055)))
1847 
1848 /* Bit definitions and macros for MCF5235_GPIO_PODR_ADDR */
1849 #define MCF5235_GPIO_PODR_ADDR_PODR_ADDR5 (0x20)
1850 #define MCF5235_GPIO_PODR_ADDR_PODR_ADDR6 (0x40)
1851 #define MCF5235_GPIO_PODR_ADDR_PODR_ADDR7 (0x80)
1852 #define MCF5235_GPIO_PODR_DATAH_PODR_DATAH0 (0x01)
1853 #define MCF5235_GPIO_PODR_DATAH_PODR_DATAH1 (0x02)
1854 #define MCF5235_GPIO_PODR_DATAH_PODR_DATAH2 (0x04)
1855 #define MCF5235_GPIO_PODR_DATAH_PODR_DATAH3 (0x08)
1856 #define MCF5235_GPIO_PODR_DATAH_PODR_DATAH4 (0x10)
1857 #define MCF5235_GPIO_PODR_DATAH_PODR_DATAH5 (0x20)
1858 #define MCF5235_GPIO_PODR_DATAH_PODR_DATAH6 (0x40)
1859 #define MCF5235_GPIO_PODR_DATAH_PODR_DATAH7 (0x80)
1860 #define MCF5235_GPIO_PODR_DATAL_PODR_DATAL0 (0x01)
1861 #define MCF5235_GPIO_PODR_DATAL_PODR_DATAL1 (0x02)
1862 #define MCF5235_GPIO_PODR_DATAL_PODR_DATAL2 (0x04)
1863 #define MCF5235_GPIO_PODR_DATAL_PODR_DATAL3 (0x08)
1864 #define MCF5235_GPIO_PODR_DATAL_PODR_DATAL4 (0x10)
1865 #define MCF5235_GPIO_PODR_DATAL_PODR_DATAL5 (0x20)
1866 #define MCF5235_GPIO_PODR_DATAL_PODR_DATAL6 (0x40)
1867 #define MCF5235_GPIO_PODR_DATAL_PODR_DATAL7 (0x80)
1868 #define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL0 (0x01)
1869 #define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02)
1870 #define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04)
1871 #define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08)
1872 #define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL4 (0x10)
1873 #define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL5 (0x20)
1874 #define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL6 (0x40)
1875 #define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL7 (0x80)
1876 #define MCF5235_GPIO_PODR_BS_PODR_BS0 (0x01)
1877 #define MCF5235_GPIO_PODR_BS_PODR_BS1 (0x02)
1878 #define MCF5235_GPIO_PODR_BS_PODR_BS2 (0x04)
1879 #define MCF5235_GPIO_PODR_BS_PODR_BS3 (0x08)
1880 #define MCF5235_GPIO_PODR_CS_PODR_CS1 (0x02)
1881 #define MCF5235_GPIO_PODR_CS_PODR_CS2 (0x04)
1882 #define MCF5235_GPIO_PODR_CS_PODR_CS3 (0x08)
1883 #define MCF5235_GPIO_PODR_CS_PODR_CS4 (0x10)
1884 #define MCF5235_GPIO_PODR_CS_PODR_CS5 (0x20)
1885 #define MCF5235_GPIO_PODR_CS_PODR_CS6 (0x40)
1886 #define MCF5235_GPIO_PODR_CS_PODR_CS7 (0x80)
1887 #define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM0 (0x01)
1888 #define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM1 (0x02)
1889 #define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM2 (0x04)
1890 #define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM3 (0x08)
1891 #define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM4 (0x10)
1892 #define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM5 (0x20)
1893 #define MCF5235_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01)
1894 #define MCF5235_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02)
1895 #define MCF5235_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04)
1896 #define MCF5235_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08)
1897 #define MCF5235_GPIO_PODR_UARTH_PODR_UARTH0 (0x01)
1898 #define MCF5235_GPIO_PODR_UARTH_PODR_UARTH1 (0x02)
1899 #define MCF5235_GPIO_PODR_UARTL_PODR_UARTL0 (0x01)
1900 #define MCF5235_GPIO_PODR_UARTL_PODR_UARTL1 (0x02)
1901 #define MCF5235_GPIO_PODR_UARTL_PODR_UARTL2 (0x04)
1902 #define MCF5235_GPIO_PODR_UARTL_PODR_UARTL3 (0x08)
1903 #define MCF5235_GPIO_PODR_UARTL_PODR_UARTL4 (0x10)
1904 #define MCF5235_GPIO_PODR_UARTL_PODR_UARTL5 (0x20)
1905 #define MCF5235_GPIO_PODR_UARTL_PODR_UARTL6 (0x40)
1906 #define MCF5235_GPIO_PODR_UARTL_PODR_UARTL7 (0x80)
1907 #define MCF5235_GPIO_PODR_QSPI_PODR_QSPI0 (0x01)
1908 #define MCF5235_GPIO_PODR_QSPI_PODR_QSPI1 (0x02)
1909 #define MCF5235_GPIO_PODR_QSPI_PODR_QSPI2 (0x04)
1910 #define MCF5235_GPIO_PODR_QSPI_PODR_QSPI3 (0x08)
1911 #define MCF5235_GPIO_PODR_QSPI_PODR_QSPI4 (0x10)
1912 #define MCF5235_GPIO_PODR_TIMER_PODR_TIMER0 (0x01)
1913 #define MCF5235_GPIO_PODR_TIMER_PODR_TIMER1 (0x02)
1914 #define MCF5235_GPIO_PODR_TIMER_PODR_TIMER2 (0x04)
1915 #define MCF5235_GPIO_PODR_TIMER_PODR_TIMER3 (0x08)
1916 #define MCF5235_GPIO_PODR_TIMER_PODR_TIMER4 (0x10)
1917 #define MCF5235_GPIO_PODR_TIMER_PODR_TIMER5 (0x20)
1918 #define MCF5235_GPIO_PODR_TIMER_PODR_TIMER6 (0x40)
1919 #define MCF5235_GPIO_PODR_TIMER_PODR_TIMER7 (0x80)
1920 #define MCF5235_GPIO_PODR_ETPU_PODR_ETPU0 (0x01)
1921 #define MCF5235_GPIO_PODR_ETPU_PODR_ETPU1 (0x02)
1922 #define MCF5235_GPIO_PODR_ETPU_PODR_ETPU2 (0x04)
1923 #define MCF5235_GPIO_PDDR_APDDR_PDDR_APDDR5 (0x20)
1924 #define MCF5235_GPIO_PDDR_APDDR_PDDR_APDDR6 (0x40)
1925 #define MCF5235_GPIO_PDDR_APDDR_PDDR_APDDR7 (0x80)
1926 #define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH0 (0x01)
1927 #define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH1 (0x02)
1928 #define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH2 (0x04)
1929 #define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH3 (0x08)
1930 #define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH4 (0x10)
1931 #define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH5 (0x20)
1932 #define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH6 (0x40)
1933 #define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH7 (0x80)
1934 #define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL0 (0x01)
1935 #define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL1 (0x02)
1936 #define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL2 (0x04)
1937 #define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL3 (0x08)
1938 #define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL4 (0x10)
1939 #define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL5 (0x20)
1940 #define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL6 (0x40)
1941 #define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL7 (0x80)
1942 #define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL0 (0x01)
1943 #define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02)
1944 #define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04)
1945 #define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08)
1946 #define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL4 (0x10)
1947 #define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL5 (0x20)
1948 #define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL6 (0x40)
1949 #define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL7 (0x80)
1950 #define MCF5235_GPIO_PDDR_BS_PDDR_BS0 (0x01)
1951 #define MCF5235_GPIO_PDDR_BS_PDDR_BS3(x) (((x)&0x07)<<1)
1952 #define MCF5235_GPIO_PDDR_CS_PDDR_CS1 (0x02)
1953 #define MCF5235_GPIO_PDDR_CS_PDDR_CS2 (0x04)
1954 #define MCF5235_GPIO_PDDR_CS_PDDR_CS3 (0x08)
1955 #define MCF5235_GPIO_PDDR_CS_PDDR_CS4 (0x10)
1956 #define MCF5235_GPIO_PDDR_CS_PDDR_CS5 (0x20)
1957 #define MCF5235_GPIO_PDDR_CS_PDDR_CS6 (0x40)
1958 #define MCF5235_GPIO_PDDR_CS_PDDR_CS7 (0x80)
1959 #define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM0 (0x01)
1960 #define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM1 (0x02)
1961 #define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM2 (0x04)
1962 #define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM3 (0x08)
1963 #define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM4 (0x10)
1964 #define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM5 (0x20)
1965 #define MCF5235_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01)
1966 #define MCF5235_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02)
1967 #define MCF5235_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04)
1968 #define MCF5235_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08)
1969 #define MCF5235_GPIO_PDDR_UARTH_PDDR_UARTH0 (0x01)
1970 #define MCF5235_GPIO_PDDR_UARTH_PDDR_UARTH1 (0x02)
1971 #define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL0 (0x01)
1972 #define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL1 (0x02)
1973 #define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL2 (0x04)
1974 #define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL3 (0x08)
1975 #define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL4 (0x10)
1976 #define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL5 (0x20)
1977 #define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL6 (0x40)
1978 #define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL7 (0x80)
1979 #define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01)
1980 #define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02)
1981 #define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04)
1982 #define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08)
1983 #define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10)
1984 #define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01)
1985 #define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02)
1986 #define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04)
1987 #define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08)
1988 #define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER4 (0x10)
1989 #define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER5 (0x20)
1990 #define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER6 (0x40)
1991 #define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER7 (0x80)
1992 #define MCF5235_GPIO_PDDR_ETPU_PDDR_ETPU0 (0x01)
1993 #define MCF5235_GPIO_PDDR_ETPU_PDDR_ETPU1 (0x02)
1994 #define MCF5235_GPIO_PDDR_ETPU_PDDR_ETPU2 (0x04)
1995 #define MCF5235_GPIO_PPDSDR_ADDR_PPDSDR_ADDR5 (0x20)
1996 #define MCF5235_GPIO_PPDSDR_ADDR_PPDSDR_ADDR6 (0x40)
1997 #define MCF5235_GPIO_PPDSDR_ADDR_PPDSDR_ADDR7 (0x80)
1998 #define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH0 (0x01)
1999 #define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH1 (0x02)
2000 #define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH2 (0x04)
2001 #define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH3 (0x08)
2002 #define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH4 (0x10)
2003 #define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH5 (0x20)
2004 #define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH6 (0x40)
2005 #define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH7 (0x80)
2006 #define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL0 (0x01)
2007 #define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL1 (0x02)
2008 #define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL2 (0x04)
2009 #define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL3 (0x08)
2010 #define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL4 (0x10)
2011 #define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL5 (0x20)
2012 #define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL6 (0x40)
2013 #define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL7 (0x80)
2014 #define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL0 (0x01)
2015 #define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02)
2016 #define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04)
2017 #define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08)
2018 #define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL4 (0x10)
2019 #define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL5 (0x20)
2020 #define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL6 (0x40)
2021 #define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL7 (0x80)
2022 #define MCF5235_GPIO_PPDSDR_BS_PPDSDR_BS0 (0x01)
2023 #define MCF5235_GPIO_PPDSDR_BS_PPDSDR_BS1 (0x02)
2024 #define MCF5235_GPIO_PPDSDR_BS_PPDSDR_BS2 (0x04)
2025 #define MCF5235_GPIO_PPDSDR_BS_PPDSDR_BS3 (0x08)
2026 #define MCF5235_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01)
2027 #define MCF5235_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02)
2028 #define MCF5235_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04)
2029 #define MCF5235_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08)
2030 #define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02)
2031 #define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04)
2032 #define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08)
2033 #define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10)
2034 #define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20)
2035 #define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS6 (0x40)
2036 #define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS7 (0x80)
2037 #define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM0 (0x01)
2038 #define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM1 (0x02)
2039 #define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM2 (0x04)
2040 #define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM3 (0x08)
2041 #define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM4 (0x10)
2042 #define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM5 (0x20)
2043 #define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM6 (0x40)
2044 #define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM7 (0x80)
2045 #define MCF5235_GPIO_PPDSDR_UARTH_PPDSDR_UARTH0 (0x01)
2046 #define MCF5235_GPIO_PPDSDR_UARTH_PPDSDR_UARTH1 (0x02)
2047 #define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL0 (0x01)
2048 #define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL1 (0x02)
2049 #define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL2 (0x04)
2050 #define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL3 (0x08)
2051 #define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL4 (0x10)
2052 #define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL5 (0x20)
2053 #define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL6 (0x40)
2054 #define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL7 (0x80)
2055 #define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01)
2056 #define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02)
2057 #define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04)
2058 #define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08)
2059 #define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10)
2060 #define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01)
2061 #define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02)
2062 #define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04)
2063 #define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08)
2064 #define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER4 (0x10)
2065 #define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER5 (0x20)
2066 #define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER6 (0x40)
2067 #define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER7 (0x80)
2068 #define MCF5235_GPIO_PPDSDR_ETPU_PPDSDR_ETPU0 (0x01)
2069 #define MCF5235_GPIO_PPDSDR_ETPU_PPDSDR_ETPU1 (0x02)
2070 #define MCF5235_GPIO_PPDSDR_ETPU_PPDSDR_ETPU2 (0x04)
2071 #define MCF5235_GPIO_PCLRR_ADDR_PCLRR_ADDR5 (0x20)
2072 #define MCF5235_GPIO_PCLRR_ADDR_PCLRR_ADDR6 (0x40)
2073 #define MCF5235_GPIO_PCLRR_ADDR_PCLRR_ADDR7 (0x80)
2074 #define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH0 (0x01)
2075 #define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH1 (0x02)
2076 #define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH2 (0x04)
2077 #define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH3 (0x08)
2078 #define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH4 (0x10)
2079 #define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH5 (0x20)
2080 #define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH6 (0x40)
2081 #define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH7 (0x80)
2082 #define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL0 (0x01)
2083 #define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL1 (0x02)
2084 #define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL2 (0x04)
2085 #define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL3 (0x08)
2086 #define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL4 (0x10)
2087 #define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL5 (0x20)
2088 #define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL6 (0x40)
2089 #define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL7 (0x80)
2090 #define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL0 (0x01)
2091 #define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02)
2092 #define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04)
2093 #define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08)
2094 #define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL4 (0x10)
2095 #define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL5 (0x20)
2096 #define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL6 (0x40)
2097 #define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL7 (0x80)
2098 #define MCF5235_GPIO_PCLRR_BS_PCLRR_BS0 (0x01)
2099 #define MCF5235_GPIO_PCLRR_BS_PCLRR_BS1 (0x02)
2100 #define MCF5235_GPIO_PCLRR_BS_PCLRR_BS2 (0x04)
2101 #define MCF5235_GPIO_PCLRR_BS_PCLRR_BS3 (0x08)
2102 #define MCF5235_GPIO_PCLRR_CS_PCLRR_CS1 (0x02)
2103 #define MCF5235_GPIO_PCLRR_CS_PCLRR_CS2 (0x04)
2104 #define MCF5235_GPIO_PCLRR_CS_PCLRR_CS3 (0x08)
2105 #define MCF5235_GPIO_PCLRR_CS_PCLRR_CS4 (0x10)
2106 #define MCF5235_GPIO_PCLRR_CS_PCLRR_CS5 (0x20)
2107 #define MCF5235_GPIO_PCLRR_CS_PCLRR_CS6 (0x40)
2108 #define MCF5235_GPIO_PCLRR_CS_PCLRR_CS7 (0x80)*/
2109 #define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM0 (0x01)
2110 #define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM1 (0x02)
2111 #define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM2 (0x04)
2112 #define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM3 (0x08)
2113 #define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM4 (0x10)
2114 #define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM5 (0x20)
2115 #define MCF5235_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01)
2116 #define MCF5235_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02)
2117 #define MCF5235_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04)
2118 #define MCF5235_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08)
2119 #define MCF5235_GPIO_PCLRR_UARTH_PCLRR_UARTH0 (0x01)
2120 #define MCF5235_GPIO_PCLRR_UARTH_PCLRR_UARTH1 (0x02)
2121 #define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL0 (0x01)
2122 #define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL1 (0x02)
2123 #define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL2 (0x04)
2124 #define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL3 (0x08)
2125 #define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL4 (0x10)
2126 #define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL5 (0x20)
2127 #define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL6 (0x40)
2128 #define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL7 (0x80)
2129 #define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01)
2130 #define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02)
2131 #define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04)
2132 #define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08)
2133 #define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10)
2134 #define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01)
2135 #define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02)
2136 #define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04)
2137 #define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08)
2138 #define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER4 (0x10)
2139 #define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER5 (0x20)
2140 #define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER6 (0x40)
2141 #define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER7 (0x80)
2142 #define MCF5235_GPIO_PCLRR_ETPU_PCLRR_ETPU0 (0x01)
2143 #define MCF5235_GPIO_PCLRR_ETPU_PCLRR_ETPU1 (0x02)
2144 #define MCF5235_GPIO_PCLRR_ETPU_PCLRR_ETPU2 (0x04)
2145 #define MCF5235_GPIO_PAR_AD_PAR_DATAL (0x01)
2146 #define MCF5235_GPIO_PAR_AD_PAR_ADDR21 (0x20)
2147 #define MCF5235_GPIO_PAR_AD_PAR_ADDR22 (0x40)
2148 #define MCF5235_GPIO_PAR_AD_PAR_ADDR23 (0x80)
2149 #define MCF5235_GPIO_PAR_BUSCTL_PAR_TIP(x) (((x)&0x0003)<<0)
2150 #define MCF5235_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x0003)<<2)
2151 #define MCF5235_GPIO_PAR_BUSCTL_PAR_TSIZ0 (0x0010)
2152 #define MCF5235_GPIO_PAR_BUSCTL_PAR_TSIZ1 (0x0040)
2153 #define MCF5235_GPIO_PAR_BUSCTL_PAR_RWB (0x0100)
2154 #define MCF5235_GPIO_PAR_BUSCTL_PAR_TEA(x) (((x)&0x0003)<<10)
2155 #define MCF5235_GPIO_PAR_BUSCTL_PAR_TA (0x1000)
2156 #define MCF5235_GPIO_PAR_BUSCTL_PAR_OE (0x4000)
2157 #define MCF5235_GPIO_PAR_BUSCTL_PAR_TEA_GPIO (0x0000)
2158 #define MCF5235_GPIO_PAR_BUSCTL_PAR_TEA_DMA (0x0800)
2159 #define MCF5235_GPIO_PAR_BUSCTL_PAR_TEA_TEA (0x0C00)
2160 #define MCF5235_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x0000)
2161 #define MCF5235_GPIO_PAR_BUSCTL_PAR_TS_DMA (0x0080)
2162 #define MCF5235_GPIO_PAR_BUSCTL_PAR_TS_TS (0x00C0)
2163 #define MCF5235_GPIO_PAR_BUSCTL_PAR_TIP_GPIO (0x0000)
2164 #define MCF5235_GPIO_PAR_BUSCTL_PAR_TIP_DMA (0x0002)
2165 #define MCF5235_GPIO_PAR_BUSCTL_PAR_TIP_TEA (0x0003)
2166 #define MCF5235_GPIO_PAR_BS_PAR_BS0 (0x01)
2167 #define MCF5235_GPIO_PAR_BS_PAR_BS1 (0x02)
2168 #define MCF5235_GPIO_PAR_BS_PAR_BS2 (0x04)
2169 #define MCF5235_GPIO_PAR_BS_PAR_BS3 (0x08)
2170 #define MCF5235_GPIO_PAR_CS_PAR_CS1 (0x02)
2171 #define MCF5235_GPIO_PAR_CS_PAR_CS2 (0x04)
2172 #define MCF5235_GPIO_PAR_CS_PAR_CS3 (0x08)
2173 #define MCF5235_GPIO_PAR_CS_PAR_CS4 (0x10)
2174 #define MCF5235_GPIO_PAR_CS_PAR_CS5 (0x20)
2175 #define MCF5235_GPIO_PAR_CS_PAR_CS6 (0x40)
2176 #define MCF5235_GPIO_PAR_CS_PAR_CS7 (0x80)
2177 #define MCF5235_GPIO_PAR_SDRAM_PAR_SDCS0 (0x01)
2178 #define MCF5235_GPIO_PAR_SDRAM_PAR_SDCS1 (0x02)
2179 #define MCF5235_GPIO_PAR_SDRAM_PAR_SCKE (0x04)
2180 #define MCF5235_GPIO_PAR_SDRAM_PAR_SRAS (0x08)
2181 #define MCF5235_GPIO_PAR_SDRAM_PAR_SCAS (0x10)
2182 #define MCF5235_GPIO_PAR_SDRAM_PAR_SDWE (0x20)
2183 #define MCF5235_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
2184 #define MCF5235_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0)
2185 #define MCF5235_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2)
2186 #define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO(x) (((x)&0x03)<<4)
2187 #define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC(x) (((x)&0x03)<<6)
2188 #define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC_GPIO (0x00)
2189 #define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC_UART2 (0x40)
2190 #define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC_I2C (0x80)
2191 #define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC_FEC (0xC0)
2192 #define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO_GPIO (0x00)
2193 #define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO_UART2 (0x10)
2194 #define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO_I2C (0x20)
2195 #define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO_FEC (0x30)
2196 #define MCF5235_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00)
2197 #define MCF5235_GPIO_PAR_FECI2C_PAR_SCL_FLEX (0x08)
2198 #define MCF5235_GPIO_PAR_FECI2C_PAR_SCL_I2C (0x0C)
2199 #define MCF5235_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00)
2200 #define MCF5235_GPIO_PAR_FECI2C_PAR_SDA_FLEX (0x02)
2201 #define MCF5235_GPIO_PAR_FECI2C_PAR_SDA_I2C (0x03)
2202 #define MCF5235_GPIO_PAR_UART_PAR_U0RTS (0x0001)
2203 #define MCF5235_GPIO_PAR_UART_PAR_U0CTS (0x0002)
2204 #define MCF5235_GPIO_PAR_UART_PAR_U0TXD (0x0004)
2205 #define MCF5235_GPIO_PAR_UART_PAR_U0RXD (0x0008)
2206 #define MCF5235_GPIO_PAR_UART_PAR_U1RTS(x) (((x)&0x0003)<<4)
2207 #define MCF5235_GPIO_PAR_UART_PAR_U1CTS(x) (((x)&0x0003)<<6)
2208 #define MCF5235_GPIO_PAR_UART_PAR_U1TXD(x) (((x)&0x0003)<<8)
2209 #define MCF5235_GPIO_PAR_UART_PAR_U1RXD(x) (((x)&0x0003)<<10)
2210 #define MCF5235_GPIO_PAR_UART_PAR_U2TXD (0x1000)
2211 #define MCF5235_GPIO_PAR_UART_PAR_U2RXD (0x2000)
2212 #define MCF5235_GPIO_PAR_UART_PAR_CAN1EN (0x4000)
2213 #define MCF5235_GPIO_PAR_UART_PAR_DREQ2 (0x8000)
2214 #define MCF5235_GPIO_PAR_UART_PAR_U1RXD_GPIO (0x0000)
2215 #define MCF5235_GPIO_PAR_UART_PAR_U1RXD_FLEX (0x0800)
2216 #define MCF5235_GPIO_PAR_UART_PAR_U1RXD_UART1 (0x0C00)
2217 #define MCF5235_GPIO_PAR_UART_PAR_U1TXD_GPIO (0x0000)
2218 #define MCF5235_GPIO_PAR_UART_PAR_U1TXD_FLEX (0x0200)
2219 #define MCF5235_GPIO_PAR_UART_PAR_U1TXD_UART1 (0x0300)
2220 #define MCF5235_GPIO_PAR_UART_PAR_U1CTS_GPIO (0x0000)
2221 #define MCF5235_GPIO_PAR_UART_PAR_U1CTS_UART2 (0x0080)
2222 #define MCF5235_GPIO_PAR_UART_PAR_U1CTS_UART1 (0x00C0)
2223 #define MCF5235_GPIO_PAR_UART_PAR_U1RTS_GPIO (0x0000)
2224 #define MCF5235_GPIO_PAR_UART_PAR_U1RTS_UART2 (0x0020)
2225 #define MCF5235_GPIO_PAR_UART_PAR_U1RTS_UART1 (0x0030)
2226 #define MCF5235_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x03)<<0)
2227 #define MCF5235_GPIO_PAR_QSPI_PAR_DOUT (0x04)
2228 #define MCF5235_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x03)<<3)
2229 #define MCF5235_GPIO_PAR_QSPI_PAR_PCS0 (0x20)
2230 #define MCF5235_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x03)<<6)
2231 #define MCF5235_GPIO_PAR_QSPI_PAR_PCS1_GPIO (0x00)
2232 #define MCF5235_GPIO_PAR_QSPI_PAR_PCS1_SDRAMC (0x80)
2233 #define MCF5235_GPIO_PAR_QSPI_PAR_PCS1_QSPI (0xC0)
2234 #define MCF5235_GPIO_PAR_QSPI_PAR_DIN_GPIO (0x00)
2235 #define MCF5235_GPIO_PAR_QSPI_PAR_DIN_I2C (0x10)
2236 #define MCF5235_GPIO_PAR_QSPI_PAR_DIN_QSPI (0x1C)
2237 #define MCF5235_GPIO_PAR_QSPI_PAR_SCK_GPIO (0x00)
2238 #define MCF5235_GPIO_PAR_QSPI_PAR_SCK_I2C (0x02)
2239 #define MCF5235_GPIO_PAR_QSPI_PAR_SCK_QSPI (0x03)
2240 #define MCF5235_GPIO_PAR_TIMER_PAR_T0OUT(x) (((x)&0x0003)<<0)
2241 #define MCF5235_GPIO_PAR_TIMER_PAR_T1OUT(x) (((x)&0x0003)<<2)
2242 #define MCF5235_GPIO_PAR_TIMER_PAR_T2OUT(x) (((x)&0x0003)<<4)
2243 #define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT(x) (((x)&0x0003)<<6)
2244 #define MCF5235_GPIO_PAR_TIMER_PAR_T0IN(x) (((x)&0x0003)<<8)
2245 #define MCF5235_GPIO_PAR_TIMER_PAR_T1IN(x) (((x)&0x0003)<<10)
2246 #define MCF5235_GPIO_PAR_TIMER_PAR_T2IN(x) (((x)&0x0003)<<12)
2247 #define MCF5235_GPIO_PAR_TIMER_PAR_T3IN(x) (((x)&0x0003)<<14)
2248 #define MCF5235_GPIO_PAR_TIMER_PAR_T3IN_GPIO (0x0000)
2249 #define MCF5235_GPIO_PAR_TIMER_PAR_T3IN_QSPI (0x4000)
2250 #define MCF5235_GPIO_PAR_TIMER_PAR_T3IN_UART2 (0x8000)
2251 #define MCF5235_GPIO_PAR_TIMER_PAR_T3IN_T3IN (0xC000)
2252 #define MCF5235_GPIO_PAR_TIMER_PAR_T2IN_GPIO (0x0000)
2253 #define MCF5235_GPIO_PAR_TIMER_PAR_T2IN_T2OUT (0x1000)
2254 #define MCF5235_GPIO_PAR_TIMER_PAR_T2IN_DMA (0x2000)
2255 #define MCF5235_GPIO_PAR_TIMER_PAR_T2IN_T2IN (0x3000)
2256 #define MCF5235_GPIO_PAR_TIMER_PAR_T1IN_GPIO (0x0000)
2257 #define MCF5235_GPIO_PAR_TIMER_PAR_T1IN_T1OUT (0x0400)
2258 #define MCF5235_GPIO_PAR_TIMER_PAR_T1IN_DMA (0x0800)
2259 #define MCF5235_GPIO_PAR_TIMER_PAR_T1IN_T1IN (0x0C00)
2260 #define MCF5235_GPIO_PAR_TIMER_PAR_T0IN_GPIO (0x0000)
2261 #define MCF5235_GPIO_PAR_TIMER_PAR_T0IN_DMA (0x0200)
2262 #define MCF5235_GPIO_PAR_TIMER_PAR_T0IN_T0IN (0x0300)
2263 #define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT_GPIO (0x0000)
2264 #define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT_QSPI (0x0040)
2265 #define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT_UART2 (0x0080)
2266 #define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT_T3OUT (0x00C0)
2267 #define MCF5235_GPIO_PAR_TIMER_PAR_T2OUT_GPIO (0x0000)
2268 #define MCF5235_GPIO_PAR_TIMER_PAR_T2OUT_DMA (0x0020)
2269 #define MCF5235_GPIO_PAR_TIMER_PAR_T2OUT_T2OUT (0x0030)
2270 #define MCF5235_GPIO_PAR_TIMER_PAR_T1OUT_GPIO (0x0000)
2271 #define MCF5235_GPIO_PAR_TIMER_PAR_T1OUT_DMA (0x0008)
2272 #define MCF5235_GPIO_PAR_TIMER_PAR_T1OUT_T1OUT (0x000C)
2273 #define MCF5235_GPIO_PAR_TIMER_PAR_T0OUT_GPIO (0x0000)
2274 #define MCF5235_GPIO_PAR_TIMER_PAR_T0OUT_DMA (0x0002)
2275 #define MCF5235_GPIO_PAR_TIMER_PAR_T0OUT_T0OUT (0x0003)
2276 #define MCF5235_GPIO_PAR_ETPU_PAR_LTPU_ODIS (0x01)
2277 #define MCF5235_GPIO_PAR_ETPU_PAR_UTPU_ODIS (0x02)
2278 #define MCF5235_GPIO_PAR_ETPU_PAR_TCRCLK (0x04)
2279 #define MCF5235_GPIO_DSCR_EIM_DSCR_EIM0 (0x01)
2280 #define MCF5235_GPIO_DSCR_EIM_DSCR_EIM1 (0x10)
2281 #define MCF5235_GPIO_DSCR_ETPU_DSCR_ETPU_7_0 (0x01)
2282 #define MCF5235_GPIO_DSCR_ETPU_DSCR_ETPU_15_8 (0x04)
2283 #define MCF5235_GPIO_DSCR_ETPU_DSCR_ETPU_23_16 (0x10)
2284 #define MCF5235_GPIO_DSCR_ETPU_DSCR_ETPU_31_24 (0x40)
2285 #define MCF5235_GPIO_DSCR_FECI2C_DSCR_I2C (0x01)
2286 #define MCF5235_GPIO_DSCR_FECI2C_DSCR_FEC (0x10)
2287 #define MCF5235_GPIO_DSCR_UART_DSCR_UART0 (0x01)
2288 #define MCF5235_GPIO_DSCR_UART_DSCR_UART1 (0x04)
2289 #define MCF5235_GPIO_DSCR_UART_DSCR_UART2 (0x10)
2290 #define MCF5235_GPIO_DSCR_UART_DSCR_IRQ (0x40)
2291 #define MCF5235_GPIO_DSCR_QSPI_DSCR_QSPI (0x01)*/
2292 #define MCF5235_GPIO_DSCR_TIMER_DSCR_TIMER (0x01)
2293 
2294 /*********************************************************************
2295 *
2296 * I2C Module (I2C)
2297 *
2298 *********************************************************************/
2299 
2300 /* Register read/write macros */
2301 #define MCF5235_I2C_I2AR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000300)))
2302 #define MCF5235_I2C_I2FDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000304)))
2303 #define MCF5235_I2C_I2CR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000308)))
2304 #define MCF5235_I2C_I2SR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00030C)))
2305 #define MCF5235_I2C_I2DR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000310)))
2306 #define MCF5235_I2C_I2ICR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000320)))
2307 
2308 /* Bit definitions and macros for MCF5235_I2C_I2AR */
2309 #define MCF5235_I2C_I2AR_ADR(x) (((x)&0x7F)<<1)
2310 #define MCF5235_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
2311 #define MCF5235_I2C_I2CR_RSTA (0x04)
2312 #define MCF5235_I2C_I2CR_TXAK (0x08)
2313 #define MCF5235_I2C_I2CR_MTX (0x10)
2314 #define MCF5235_I2C_I2CR_MSTA (0x20)
2315 #define MCF5235_I2C_I2CR_IIEN (0x40)
2316 #define MCF5235_I2C_I2CR_IEN (0x80)
2317 #define MCF5235_I2C_I2SR_RXAK (0x01)
2318 #define MCF5235_I2C_I2SR_IIF (0x02)
2319 #define MCF5235_I2C_I2SR_SRW (0x04)
2320 #define MCF5235_I2C_I2SR_IAL (0x10)
2321 #define MCF5235_I2C_I2SR_IBB (0x20)
2322 #define MCF5235_I2C_I2SR_IAAS (0x40)
2323 #define MCF5235_I2C_I2SR_ICF (0x80)
2324 #define MCF5235_I2C_I2ICR_IE (0x01)
2325 #define MCF5235_I2C_I2ICR_RE (0x02)
2326 #define MCF5235_I2C_I2ICR_TE (0x04)
2327 #define MCF5235_I2C_I2ICR_BNBE (0x08)
2328 
2329 /*********************************************************************
2330 *
2331 * Interrupt Controller 0 (INTC0)
2332 *
2333 *********************************************************************/
2334 
2335 /* Register read/write macros */
2336 #define MCF5235_INTC0_IPRH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C00)))
2337 #define MCF5235_INTC0_IPRL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C04)))
2338 #define MCF5235_INTC0_IMRH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C08)))
2339 #define MCF5235_INTC0_IMRL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C0C)))
2340 #define MCF5235_INTC0_INTFRCH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C10)))
2341 #define MCF5235_INTC0_INTFRCL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C14)))
2342 #define MCF5235_INTC0_IRLR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C18)))
2343 #define MCF5235_INTC0_IACKLPR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C19)))
2344 #define MCF5235_INTC0_ICR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C40)))
2345 #define MCF5235_INTC0_ICR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C41)))
2346 #define MCF5235_INTC0_ICR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C42)))
2347 #define MCF5235_INTC0_ICR3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C43)))
2348 #define MCF5235_INTC0_ICR4 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C44)))
2349 #define MCF5235_INTC0_ICR5 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C45)))
2350 #define MCF5235_INTC0_ICR6 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C46)))
2351 #define MCF5235_INTC0_ICR7 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C47)))
2352 #define MCF5235_INTC0_ICR8 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C48)))
2353 #define MCF5235_INTC0_ICR9 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C49)))
2354 #define MCF5235_INTC0_ICR10 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4A)))
2355 #define MCF5235_INTC0_ICR11 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4B)))
2356 #define MCF5235_INTC0_ICR12 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4C)))
2357 #define MCF5235_INTC0_ICR13 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4D)))
2358 #define MCF5235_INTC0_ICR14 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4E)))
2359 #define MCF5235_INTC0_ICR15 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4F)))
2360 #define MCF5235_INTC0_ICR16 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C50)))
2361 #define MCF5235_INTC0_ICR17 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C51)))
2362 #define MCF5235_INTC0_ICR18 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C52)))
2363 #define MCF5235_INTC0_ICR19 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C53)))
2364 #define MCF5235_INTC0_ICR20 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C54)))
2365 #define MCF5235_INTC0_ICR21 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C55)))
2366 #define MCF5235_INTC0_ICR22 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C56)))
2367 #define MCF5235_INTC0_ICR23 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C57)))
2368 #define MCF5235_INTC0_ICR24 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C58)))
2369 #define MCF5235_INTC0_ICR25 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C59)))
2370 #define MCF5235_INTC0_ICR26 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5A)))
2371 #define MCF5235_INTC0_ICR27 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5B)))
2372 #define MCF5235_INTC0_ICR28 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5C)))
2373 #define MCF5235_INTC0_ICR29 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5D)))
2374 #define MCF5235_INTC0_ICR30 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5E)))
2375 #define MCF5235_INTC0_ICR31 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5F)))
2376 #define MCF5235_INTC0_ICR32 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C60)))
2377 #define MCF5235_INTC0_ICR33 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C61)))
2378 #define MCF5235_INTC0_ICR34 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C62)))
2379 #define MCF5235_INTC0_ICR35 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C63)))
2380 #define MCF5235_INTC0_ICR36 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C64)))
2381 #define MCF5235_INTC0_ICR37 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C65)))
2382 #define MCF5235_INTC0_ICR38 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C66)))
2383 #define MCF5235_INTC0_ICR39 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C67)))
2384 #define MCF5235_INTC0_ICR40 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C68)))
2385 #define MCF5235_INTC0_ICR41 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C69)))
2386 #define MCF5235_INTC0_ICR42 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6A)))
2387 #define MCF5235_INTC0_ICR43 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6B)))
2388 #define MCF5235_INTC0_ICR44 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6C)))
2389 #define MCF5235_INTC0_ICR45 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6D)))
2390 #define MCF5235_INTC0_ICR46 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6E)))
2391 #define MCF5235_INTC0_ICR47 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6F)))
2392 #define MCF5235_INTC0_ICR48 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C70)))
2393 #define MCF5235_INTC0_ICR49 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C71)))
2394 #define MCF5235_INTC0_ICR50 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C72)))
2395 #define MCF5235_INTC0_ICR51 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C73)))
2396 #define MCF5235_INTC0_ICR52 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C74)))
2397 #define MCF5235_INTC0_ICR53 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C75)))
2398 #define MCF5235_INTC0_ICR54 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C76)))
2399 #define MCF5235_INTC0_ICR55 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C77)))
2400 #define MCF5235_INTC0_ICR56 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C78)))
2401 #define MCF5235_INTC0_ICR57 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C79)))
2402 #define MCF5235_INTC0_ICR58 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7A)))
2403 #define MCF5235_INTC0_ICR59 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7B)))
2404 #define MCF5235_INTC0_ICR60 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7C)))
2405 #define MCF5235_INTC0_ICR61 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7D)))
2406 #define MCF5235_INTC0_ICR62 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7E)))
2407 #define MCF5235_INTC0_ICR63 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7F)))
2408 #define MCF5235_INTC0_ICRn(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C40+((x)*0x001))))
2409 #define MCF5235_INTC0_SWIACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CE0)))
2410 #define MCF5235_INTC0_L1IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CE4)))
2411 #define MCF5235_INTC0_L2IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CE8)))
2412 #define MCF5235_INTC0_L3IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CEC)))
2413 #define MCF5235_INTC0_L4IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CF0)))
2414 #define MCF5235_INTC0_L5IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CF4)))
2415 #define MCF5235_INTC0_L6IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CF8)))
2416 #define MCF5235_INTC0_L7IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CFC)))
2417 #define MCF5235_INTC0_LnIACK(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CE4+((x)*0x004))))
2418 #define MCF5235_INTC1_IPRH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D00)))
2419 #define MCF5235_INTC1_IPRL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D04)))
2420 #define MCF5235_INTC1_IMRH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D08)))
2421 #define MCF5235_INTC1_IMRL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D0C)))
2422 #define MCF5235_INTC1_INTFRCH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D10)))
2423 #define MCF5235_INTC1_INTFRCL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D14)))
2424 #define MCF5235_INTC1_IRLR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D18)))
2425 #define MCF5235_INTC1_IACKLPR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D19)))
2426 #define MCF5235_INTC1_ICR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D40)))
2427 #define MCF5235_INTC1_ICR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D41)))
2428 #define MCF5235_INTC1_ICR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D42)))
2429 #define MCF5235_INTC1_ICR3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D43)))
2430 #define MCF5235_INTC1_ICR4 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D44)))
2431 #define MCF5235_INTC1_ICR5 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D45)))
2432 #define MCF5235_INTC1_ICR6 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D46)))
2433 #define MCF5235_INTC1_ICR7 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D47)))
2434 #define MCF5235_INTC1_ICR8 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D48)))
2435 #define MCF5235_INTC1_ICR9 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D49)))
2436 #define MCF5235_INTC1_ICR10 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4A)))
2437 #define MCF5235_INTC1_ICR11 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4B)))
2438 #define MCF5235_INTC1_ICR12 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4C)))
2439 #define MCF5235_INTC1_ICR13 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4D)))
2440 #define MCF5235_INTC1_ICR14 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4E)))
2441 #define MCF5235_INTC1_ICR15 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4F)))
2442 #define MCF5235_INTC1_ICR16 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D50)))
2443 #define MCF5235_INTC1_ICR17 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D51)))
2444 #define MCF5235_INTC1_ICR18 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D52)))
2445 #define MCF5235_INTC1_ICR19 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D53)))
2446 #define MCF5235_INTC1_ICR20 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D54)))
2447 #define MCF5235_INTC1_ICR21 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D55)))
2448 #define MCF5235_INTC1_ICR22 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D56)))
2449 #define MCF5235_INTC1_ICR23 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D57)))
2450 #define MCF5235_INTC1_ICR24 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D58)))
2451 #define MCF5235_INTC1_ICR25 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D59)))
2452 #define MCF5235_INTC1_ICR26 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5A)))
2453 #define MCF5235_INTC1_ICR27 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5B)))
2454 #define MCF5235_INTC1_ICR28 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5C)))
2455 #define MCF5235_INTC1_ICR29 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5D)))
2456 #define MCF5235_INTC1_ICR30 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5E)))
2457 #define MCF5235_INTC1_ICR31 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5F)))
2458 #define MCF5235_INTC1_ICR32 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D60)))
2459 #define MCF5235_INTC1_ICR33 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D61)))
2460 #define MCF5235_INTC1_ICR34 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D62)))
2461 #define MCF5235_INTC1_ICR35 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D63)))
2462 #define MCF5235_INTC1_ICR36 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D64)))
2463 #define MCF5235_INTC1_ICR37 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D65)))
2464 #define MCF5235_INTC1_ICR38 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D66)))
2465 #define MCF5235_INTC1_ICR39 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D67)))
2466 #define MCF5235_INTC1_ICR40 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D68)))
2467 #define MCF5235_INTC1_ICR41 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D69)))
2468 #define MCF5235_INTC1_ICR42 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6A)))
2469 #define MCF5235_INTC1_ICR43 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6B)))
2470 #define MCF5235_INTC1_ICR44 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6C)))
2471 #define MCF5235_INTC1_ICR45 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6D)))
2472 #define MCF5235_INTC1_ICR46 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6E)))
2473 #define MCF5235_INTC1_ICR47 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6F)))
2474 #define MCF5235_INTC1_ICR48 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D70)))
2475 #define MCF5235_INTC1_ICR49 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D71)))
2476 #define MCF5235_INTC1_ICR50 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D72)))
2477 #define MCF5235_INTC1_ICR51 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D73)))
2478 #define MCF5235_INTC1_ICR52 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D74)))
2479 #define MCF5235_INTC1_ICR53 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D75)))
2480 #define MCF5235_INTC1_ICR54 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D76)))
2481 #define MCF5235_INTC1_ICR55 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D77)))
2482 #define MCF5235_INTC1_ICR56 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D78)))
2483 #define MCF5235_INTC1_ICR57 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D79)))
2484 #define MCF5235_INTC1_ICR58 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7A)))
2485 #define MCF5235_INTC1_ICR59 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7B)))
2486 #define MCF5235_INTC1_ICR60 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7C)))
2487 #define MCF5235_INTC1_ICR61 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7D)))
2488 #define MCF5235_INTC1_ICR62 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7E)))
2489 #define MCF5235_INTC1_ICR63 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7F)))
2490 #define MCF5235_INTC1_ICRn(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D40+((x)*0x001))))
2491 #define MCF5235_INTC1_SWIACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DE0)))
2492 #define MCF5235_INTC1_L1IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DE4)))
2493 #define MCF5235_INTC1_L2IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DE8)))
2494 #define MCF5235_INTC1_L3IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DEC)))
2495 #define MCF5235_INTC1_L4IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DF0)))
2496 #define MCF5235_INTC1_L5IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DF4)))
2497 #define MCF5235_INTC1_L6IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DF8)))
2498 #define MCF5235_INTC1_L7IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DFC)))
2499 #define MCF5235_INTC1_LnIACK(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DE4+((x)*0x004))))
2500 
2501 /* Bit definitions and macros for MCF5235_INTC0_IPRH */
2502 #define MCF5235_INTC0_IPRH_INT32 (0x00000001)
2503 #define MCF5235_INTC0_IPRH_INT33 (0x00000002)
2504 #define MCF5235_INTC0_IPRH_INT34 (0x00000004)
2505 #define MCF5235_INTC0_IPRH_INT35 (0x00000008)
2506 #define MCF5235_INTC0_IPRH_INT36 (0x00000010)
2507 #define MCF5235_INTC0_IPRH_INT37 (0x00000020)
2508 #define MCF5235_INTC0_IPRH_INT38 (0x00000040)
2509 #define MCF5235_INTC0_IPRH_INT39 (0x00000080)
2510 #define MCF5235_INTC0_IPRH_INT40 (0x00000100)
2511 #define MCF5235_INTC0_IPRH_INT41 (0x00000200)
2512 #define MCF5235_INTC0_IPRH_INT42 (0x00000400)
2513 #define MCF5235_INTC0_IPRH_INT43 (0x00000800)
2514 #define MCF5235_INTC0_IPRH_INT44 (0x00001000)
2515 #define MCF5235_INTC0_IPRH_INT45 (0x00002000)
2516 #define MCF5235_INTC0_IPRH_INT46 (0x00004000)
2517 #define MCF5235_INTC0_IPRH_INT47 (0x00008000)
2518 #define MCF5235_INTC0_IPRH_INT48 (0x00010000)
2519 #define MCF5235_INTC0_IPRH_INT49 (0x00020000)
2520 #define MCF5235_INTC0_IPRH_INT50 (0x00040000)
2521 #define MCF5235_INTC0_IPRH_INT51 (0x00080000)
2522 #define MCF5235_INTC0_IPRH_INT52 (0x00100000)
2523 #define MCF5235_INTC0_IPRH_INT53 (0x00200000)
2524 #define MCF5235_INTC0_IPRH_INT54 (0x00400000)
2525 #define MCF5235_INTC0_IPRH_INT55 (0x00800000)
2526 #define MCF5235_INTC0_IPRH_INT56 (0x01000000)
2527 #define MCF5235_INTC0_IPRH_INT57 (0x02000000)
2528 #define MCF5235_INTC0_IPRH_INT58 (0x04000000)
2529 #define MCF5235_INTC0_IPRH_INT59 (0x08000000)
2530 #define MCF5235_INTC0_IPRH_INT60 (0x10000000)
2531 #define MCF5235_INTC0_IPRH_INT61 (0x20000000)
2532 #define MCF5235_INTC0_IPRH_INT62 (0x40000000)
2533 #define MCF5235_INTC0_IPRH_INT63 (0x80000000)
2534 #define MCF5235_INTC0_IPRL_INT1 (0x00000002)
2535 #define MCF5235_INTC0_IPRL_INT2 (0x00000004)
2536 #define MCF5235_INTC0_IPRL_INT3 (0x00000008)
2537 #define MCF5235_INTC0_IPRL_INT4 (0x00000010)
2538 #define MCF5235_INTC0_IPRL_INT5 (0x00000020)
2539 #define MCF5235_INTC0_IPRL_INT6 (0x00000040)
2540 #define MCF5235_INTC0_IPRL_INT7 (0x00000080)
2541 #define MCF5235_INTC0_IPRL_INT8 (0x00000100)
2542 #define MCF5235_INTC0_IPRL_INT9 (0x00000200)
2543 #define MCF5235_INTC0_IPRL_INT10 (0x00000400)
2544 #define MCF5235_INTC0_IPRL_INT11 (0x00000800)
2545 #define MCF5235_INTC0_IPRL_INT12 (0x00001000)
2546 #define MCF5235_INTC0_IPRL_INT13 (0x00002000)
2547 #define MCF5235_INTC0_IPRL_INT14 (0x00004000)
2548 #define MCF5235_INTC0_IPRL_INT15 (0x00008000)
2549 #define MCF5235_INTC0_IPRL_INT16 (0x00010000)
2550 #define MCF5235_INTC0_IPRL_INT17 (0x00020000)
2551 #define MCF5235_INTC0_IPRL_INT18 (0x00040000)
2552 #define MCF5235_INTC0_IPRL_INT19 (0x00080000)
2553 #define MCF5235_INTC0_IPRL_INT20 (0x00100000)
2554 #define MCF5235_INTC0_IPRL_INT21 (0x00200000)
2555 #define MCF5235_INTC0_IPRL_INT22 (0x00400000)
2556 #define MCF5235_INTC0_IPRL_INT23 (0x00800000)
2557 #define MCF5235_INTC0_IPRL_INT24 (0x01000000)
2558 #define MCF5235_INTC0_IPRL_INT25 (0x02000000)
2559 #define MCF5235_INTC0_IPRL_INT26 (0x04000000)
2560 #define MCF5235_INTC0_IPRL_INT27 (0x08000000)
2561 #define MCF5235_INTC0_IPRL_INT28 (0x10000000)
2562 #define MCF5235_INTC0_IPRL_INT29 (0x20000000)
2563 #define MCF5235_INTC0_IPRL_INT30 (0x40000000)
2564 #define MCF5235_INTC0_IPRL_INT31 (0x80000000)
2565 #define MCF5235_INTC0_IMRH_INT32 (0x00000001)
2566 #define MCF5235_INTC0_IMRH_INT33 (0x00000002)
2567 #define MCF5235_INTC0_IMRH_INT34 (0x00000004)
2568 #define MCF5235_INTC0_IMRH_INT35 (0x00000008)
2569 #define MCF5235_INTC0_IMRH_INT36 (0x00000010)
2570 #define MCF5235_INTC0_IMRH_INT37 (0x00000020)
2571 #define MCF5235_INTC0_IMRH_INT38 (0x00000040)
2572 #define MCF5235_INTC0_IMRH_INT39 (0x00000080)
2573 #define MCF5235_INTC0_IMRH_INT40 (0x00000100)
2574 #define MCF5235_INTC0_IMRH_INT41 (0x00000200)
2575 #define MCF5235_INTC0_IMRH_INT42 (0x00000400)
2576 #define MCF5235_INTC0_IMRH_INT43 (0x00000800)
2577 #define MCF5235_INTC0_IMRH_INT44 (0x00001000)
2578 #define MCF5235_INTC0_IMRH_INT45 (0x00002000)
2579 #define MCF5235_INTC0_IMRH_INT46 (0x00004000)
2580 #define MCF5235_INTC0_IMRH_INT47 (0x00008000)
2581 #define MCF5235_INTC0_IMRH_INT48 (0x00010000)
2582 #define MCF5235_INTC0_IMRH_INT49 (0x00020000)
2583 #define MCF5235_INTC0_IMRH_INT50 (0x00040000)
2584 #define MCF5235_INTC0_IMRH_INT51 (0x00080000)
2585 #define MCF5235_INTC0_IMRH_INT52 (0x00100000)
2586 #define MCF5235_INTC0_IMRH_INT53 (0x00200000)
2587 #define MCF5235_INTC0_IMRH_INT54 (0x00400000)
2588 #define MCF5235_INTC0_IMRH_INT55 (0x00800000)
2589 #define MCF5235_INTC0_IMRH_INT56 (0x01000000)
2590 #define MCF5235_INTC0_IMRH_INT57 (0x02000000)
2591 #define MCF5235_INTC0_IMRH_INT58 (0x04000000)
2592 #define MCF5235_INTC0_IMRH_INT59 (0x08000000)
2593 #define MCF5235_INTC0_IMRH_INT60 (0x10000000)
2594 #define MCF5235_INTC0_IMRH_INT61 (0x20000000)
2595 #define MCF5235_INTC0_IMRH_INT62 (0x40000000)
2596 #define MCF5235_INTC0_IMRH_INT63 (0x80000000)
2597 #define MCF5235_INTC0_IMRL_MASKALL (0x00000001)
2598 #define MCF5235_INTC0_IMRL_INT1 (0x00000002)
2599 #define MCF5235_INTC0_IMRL_INT2 (0x00000004)
2600 #define MCF5235_INTC0_IMRL_INT3 (0x00000008)
2601 #define MCF5235_INTC0_IMRL_INT4 (0x00000010)
2602 #define MCF5235_INTC0_IMRL_INT5 (0x00000020)
2603 #define MCF5235_INTC0_IMRL_INT6 (0x00000040)
2604 #define MCF5235_INTC0_IMRL_INT7 (0x00000080)
2605 #define MCF5235_INTC0_IMRL_INT8 (0x00000100)
2606 #define MCF5235_INTC0_IMRL_INT9 (0x00000200)
2607 #define MCF5235_INTC0_IMRL_INT10 (0x00000400)
2608 #define MCF5235_INTC0_IMRL_INT11 (0x00000800)
2609 #define MCF5235_INTC0_IMRL_INT12 (0x00001000)
2610 #define MCF5235_INTC0_IMRL_INT13 (0x00002000)
2611 #define MCF5235_INTC0_IMRL_INT14 (0x00004000)
2612 #define MCF5235_INTC0_IMRL_INT15 (0x00008000)
2613 #define MCF5235_INTC0_IMRL_INT16 (0x00010000)
2614 #define MCF5235_INTC0_IMRL_INT17 (0x00020000)
2615 #define MCF5235_INTC0_IMRL_INT18 (0x00040000)
2616 #define MCF5235_INTC0_IMRL_INT19 (0x00080000)
2617 #define MCF5235_INTC0_IMRL_INT20 (0x00100000)
2618 #define MCF5235_INTC0_IMRL_INT21 (0x00200000)
2619 #define MCF5235_INTC0_IMRL_INT22 (0x00400000)
2620 #define MCF5235_INTC0_IMRL_INT23 (0x00800000)
2621 #define MCF5235_INTC0_IMRL_INT24 (0x01000000)
2622 #define MCF5235_INTC0_IMRL_INT25 (0x02000000)
2623 #define MCF5235_INTC0_IMRL_INT26 (0x04000000)
2624 #define MCF5235_INTC0_IMRL_INT27 (0x08000000)
2625 #define MCF5235_INTC0_IMRL_INT28 (0x10000000)
2626 #define MCF5235_INTC0_IMRL_INT29 (0x20000000)
2627 #define MCF5235_INTC0_IMRL_INT30 (0x40000000)
2628 #define MCF5235_INTC0_IMRL_INT31 (0x80000000)
2629 #define MCF5235_INTC0_INTFRCH_INTFRC32 (0x00000001)
2630 #define MCF5235_INTC0_INTFRCH_INTFRC33 (0x00000002)
2631 #define MCF5235_INTC0_INTFRCH_INTFRC34 (0x00000004)
2632 #define MCF5235_INTC0_INTFRCH_INTFRC35 (0x00000008)
2633 #define MCF5235_INTC0_INTFRCH_INTFRC36 (0x00000010)
2634 #define MCF5235_INTC0_INTFRCH_INTFRC37 (0x00000020)
2635 #define MCF5235_INTC0_INTFRCH_INTFRC38 (0x00000040)
2636 #define MCF5235_INTC0_INTFRCH_INTFRC39 (0x00000080)
2637 #define MCF5235_INTC0_INTFRCH_INTFRC40 (0x00000100)
2638 #define MCF5235_INTC0_INTFRCH_INTFRC41 (0x00000200)
2639 #define MCF5235_INTC0_INTFRCH_INTFRC42 (0x00000400)
2640 #define MCF5235_INTC0_INTFRCH_INTFRC43 (0x00000800)
2641 #define MCF5235_INTC0_INTFRCH_INTFRC44 (0x00001000)
2642 #define MCF5235_INTC0_INTFRCH_INTFRC45 (0x00002000)
2643 #define MCF5235_INTC0_INTFRCH_INTFRC46 (0x00004000)
2644 #define MCF5235_INTC0_INTFRCH_INTFRC47 (0x00008000)
2645 #define MCF5235_INTC0_INTFRCH_INTFRC48 (0x00010000)
2646 #define MCF5235_INTC0_INTFRCH_INTFRC49 (0x00020000)
2647 #define MCF5235_INTC0_INTFRCH_INTFRC50 (0x00040000)
2648 #define MCF5235_INTC0_INTFRCH_INTFRC51 (0x00080000)
2649 #define MCF5235_INTC0_INTFRCH_INTFRC52 (0x00100000)
2650 #define MCF5235_INTC0_INTFRCH_INTFRC53 (0x00200000)
2651 #define MCF5235_INTC0_INTFRCH_INTFRC54 (0x00400000)
2652 #define MCF5235_INTC0_INTFRCH_INTFRC55 (0x00800000)
2653 #define MCF5235_INTC0_INTFRCH_INTFRC56 (0x01000000)
2654 #define MCF5235_INTC0_INTFRCH_INTFRC57 (0x02000000)
2655 #define MCF5235_INTC0_INTFRCH_INTFRC58 (0x04000000)
2656 #define MCF5235_INTC0_INTFRCH_INTFRC59 (0x08000000)
2657 #define MCF5235_INTC0_INTFRCH_INTFRC60 (0x10000000)
2658 #define MCF5235_INTC0_INTFRCH_INTFRC61 (0x20000000)
2659 #define MCF5235_INTC0_INTFRCH_INTFRC62 (0x40000000)
2660 #define MCF5235_INTC0_INTFRCH_INTFRC63 (0x80000000)
2661 #define MCF5235_INTC0_INTFRCL_INTFRC1 (0x00000002)
2662 #define MCF5235_INTC0_INTFRCL_INTFRC2 (0x00000004)
2663 #define MCF5235_INTC0_INTFRCL_INTFRC3 (0x00000008)
2664 #define MCF5235_INTC0_INTFRCL_INTFRC4 (0x00000010)
2665 #define MCF5235_INTC0_INTFRCL_INTFRC5 (0x00000020)
2666 #define MCF5235_INTC0_INTFRCL_INT6 (0x00000040)
2667 #define MCF5235_INTC0_INTFRCL_INT7 (0x00000080)
2668 #define MCF5235_INTC0_INTFRCL_INT8 (0x00000100)
2669 #define MCF5235_INTC0_INTFRCL_INT9 (0x00000200)
2670 #define MCF5235_INTC0_INTFRCL_INT10 (0x00000400)
2671 #define MCF5235_INTC0_INTFRCL_INTFRC11 (0x00000800)
2672 #define MCF5235_INTC0_INTFRCL_INTFRC12 (0x00001000)
2673 #define MCF5235_INTC0_INTFRCL_INTFRC13 (0x00002000)
2674 #define MCF5235_INTC0_INTFRCL_INTFRC14 (0x00004000)
2675 #define MCF5235_INTC0_INTFRCL_INT15 (0x00008000)
2676 #define MCF5235_INTC0_INTFRCL_INTFRC16 (0x00010000)
2677 #define MCF5235_INTC0_INTFRCL_INTFRC17 (0x00020000)
2678 #define MCF5235_INTC0_INTFRCL_INTFRC18 (0x00040000)
2679 #define MCF5235_INTC0_INTFRCL_INTFRC19 (0x00080000)
2680 #define MCF5235_INTC0_INTFRCL_INTFRC20 (0x00100000)
2681 #define MCF5235_INTC0_INTFRCL_INTFRC21 (0x00200000)
2682 #define MCF5235_INTC0_INTFRCL_INTFRC22 (0x00400000)
2683 #define MCF5235_INTC0_INTFRCL_INTFRC23 (0x00800000)
2684 #define MCF5235_INTC0_INTFRCL_INTFRC24 (0x01000000)
2685 #define MCF5235_INTC0_INTFRCL_INTFRC25 (0x02000000)
2686 #define MCF5235_INTC0_INTFRCL_INTFRC26 (0x04000000)
2687 #define MCF5235_INTC0_INTFRCL_INTFRC27 (0x08000000)
2688 #define MCF5235_INTC0_INTFRCL_INTFRC28 (0x10000000)
2689 #define MCF5235_INTC0_INTFRCL_INTFRC29 (0x20000000)
2690 #define MCF5235_INTC0_INTFRCL_INTFRC30 (0x40000000)
2691 #define MCF5235_INTC0_INTFRCL_INTFRC31 (0x80000000)
2692 #define MCF5235_INTC0_IRLR_IRQ(x) (((x)&0x7F)<<1)
2693 #define MCF5235_INTC0_IACKLPR_PRI(x) (((x)&0x0F)<<0)
2694 #define MCF5235_INTC0_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
2695 #define MCF5235_INTC_ICR_IP(x) (((x)&0x07)<<0)
2696 #define MCF5235_INTC_ICR_IL(x) (((x)&0x07)<<3)
2697 #define MCF5235_INTC1_IPRH_INT32 (0x00000001)
2698 #define MCF5235_INTC1_IPRH_INT33 (0x00000002)
2699 #define MCF5235_INTC1_IPRH_INT34 (0x00000004)
2700 #define MCF5235_INTC1_IPRH_INT35 (0x00000008)
2701 #define MCF5235_INTC1_IPRH_INT36 (0x00000010)
2702 #define MCF5235_INTC1_IPRH_INT37 (0x00000020)
2703 #define MCF5235_INTC1_IPRH_INT38 (0x00000040)
2704 #define MCF5235_INTC1_IPRH_INT39 (0x00000080)
2705 #define MCF5235_INTC1_IPRH_INT40 (0x00000100)
2706 #define MCF5235_INTC1_IPRH_INT41 (0x00000200)
2707 #define MCF5235_INTC1_IPRH_INT42 (0x00000400)
2708 #define MCF5235_INTC1_IPRH_INT43 (0x00000800)
2709 #define MCF5235_INTC1_IPRH_INT44 (0x00001000)
2710 #define MCF5235_INTC1_IPRH_INT45 (0x00002000)
2711 #define MCF5235_INTC1_IPRH_INT46 (0x00004000)
2712 #define MCF5235_INTC1_IPRH_INT47 (0x00008000)
2713 #define MCF5235_INTC1_IPRH_INT48 (0x00010000)
2714 #define MCF5235_INTC1_IPRH_INT49 (0x00020000)
2715 #define MCF5235_INTC1_IPRH_INT50 (0x00040000)
2716 #define MCF5235_INTC1_IPRH_INT51 (0x00080000)
2717 #define MCF5235_INTC1_IPRH_INT52 (0x00100000)
2718 #define MCF5235_INTC1_IPRH_INT53 (0x00200000)
2719 #define MCF5235_INTC1_IPRH_INT54 (0x00400000)
2720 #define MCF5235_INTC1_IPRH_INT55 (0x00800000)
2721 #define MCF5235_INTC1_IPRH_INT56 (0x01000000)
2722 #define MCF5235_INTC1_IPRH_INT57 (0x02000000)
2723 #define MCF5235_INTC1_IPRH_INT58 (0x04000000)
2724 #define MCF5235_INTC1_IPRH_INT59 (0x08000000)
2725 #define MCF5235_INTC1_IPRH_INT60 (0x10000000)
2726 #define MCF5235_INTC1_IPRH_INT61 (0x20000000)
2727 #define MCF5235_INTC1_IPRH_INT62 (0x40000000)
2728 #define MCF5235_INTC1_IPRH_INT63 (0x80000000)
2729 #define MCF5235_INTC1_IPRL_INT1 (0x00000002)
2730 #define MCF5235_INTC1_IPRL_INT2 (0x00000004)
2731 #define MCF5235_INTC1_IPRL_INT3 (0x00000008)
2732 #define MCF5235_INTC1_IPRL_INT4 (0x00000010)
2733 #define MCF5235_INTC1_IPRL_INT5 (0x00000020)
2734 #define MCF5235_INTC1_IPRL_INT6 (0x00000040)
2735 #define MCF5235_INTC1_IPRL_INT7 (0x00000080)
2736 #define MCF5235_INTC1_IPRL_INT8 (0x00000100)
2737 #define MCF5235_INTC1_IPRL_INT9 (0x00000200)
2738 #define MCF5235_INTC1_IPRL_INT10 (0x00000400)
2739 #define MCF5235_INTC1_IPRL_INT11 (0x00000800)
2740 #define MCF5235_INTC1_IPRL_INT12 (0x00001000)
2741 #define MCF5235_INTC1_IPRL_INT13 (0x00002000)
2742 #define MCF5235_INTC1_IPRL_INT14 (0x00004000)
2743 #define MCF5235_INTC1_IPRL_INT15 (0x00008000)
2744 #define MCF5235_INTC1_IPRL_INT16 (0x00010000)
2745 #define MCF5235_INTC1_IPRL_INT17 (0x00020000)
2746 #define MCF5235_INTC1_IPRL_INT18 (0x00040000)
2747 #define MCF5235_INTC1_IPRL_INT19 (0x00080000)
2748 #define MCF5235_INTC1_IPRL_INT20 (0x00100000)
2749 #define MCF5235_INTC1_IPRL_INT21 (0x00200000)
2750 #define MCF5235_INTC1_IPRL_INT22 (0x00400000)
2751 #define MCF5235_INTC1_IPRL_INT23 (0x00800000)
2752 #define MCF5235_INTC1_IPRL_INT24 (0x01000000)
2753 #define MCF5235_INTC1_IPRL_INT25 (0x02000000)
2754 #define MCF5235_INTC1_IPRL_INT26 (0x04000000)
2755 #define MCF5235_INTC1_IPRL_INT27 (0x08000000)
2756 #define MCF5235_INTC1_IPRL_INT28 (0x10000000)
2757 #define MCF5235_INTC1_IPRL_INT29 (0x20000000)
2758 #define MCF5235_INTC1_IPRL_INT30 (0x40000000)
2759 #define MCF5235_INTC1_IPRL_INT31 (0x80000000)
2760 #define MCF5235_INTC1_IMRH_INT_MASK32 (0x00000001)
2761 #define MCF5235_INTC1_IMRH_INT_MASK33 (0x00000002)
2762 #define MCF5235_INTC1_IMRH_INT_MASK34 (0x00000004)
2763 #define MCF5235_INTC1_IMRH_INT_MASK35 (0x00000008)
2764 #define MCF5235_INTC1_IMRH_INT_MASK36 (0x00000010)
2765 #define MCF5235_INTC1_IMRH_INT_MASK37 (0x00000020)
2766 #define MCF5235_INTC1_IMRH_INT_MASK38 (0x00000040)
2767 #define MCF5235_INTC1_IMRH_INT_MASK39 (0x00000080)
2768 #define MCF5235_INTC1_IMRH_INT_MASK40 (0x00000100)
2769 #define MCF5235_INTC1_IMRH_INT_MASK41 (0x00000200)
2770 #define MCF5235_INTC1_IMRH_INT_MASK42 (0x00000400)
2771 #define MCF5235_INTC1_IMRH_INT_MASK43 (0x00000800)
2772 #define MCF5235_INTC1_IMRH_INT_MASK44 (0x00001000)
2773 #define MCF5235_INTC1_IMRH_INT_MASK45 (0x00002000)
2774 #define MCF5235_INTC1_IMRH_INT_MASK46 (0x00004000)
2775 #define MCF5235_INTC1_IMRH_INT_MASK47 (0x00008000)
2776 #define MCF5235_INTC1_IMRH_INT_MASK48 (0x00010000)
2777 #define MCF5235_INTC1_IMRH_INT_MASK49 (0x00020000)
2778 #define MCF5235_INTC1_IMRH_INT_MASK50 (0x00040000)
2779 #define MCF5235_INTC1_IMRH_INT_MASK51 (0x00080000)
2780 #define MCF5235_INTC1_IMRH_INT_MASK52 (0x00100000)
2781 #define MCF5235_INTC1_IMRH_INT_MASK53 (0x00200000)
2782 #define MCF5235_INTC1_IMRH_INT_MASK54 (0x00400000)
2783 #define MCF5235_INTC1_IMRH_INT_MASK55 (0x00800000)
2784 #define MCF5235_INTC1_IMRH_INT_MASK56 (0x01000000)
2785 #define MCF5235_INTC1_IMRH_INT_MASK57 (0x02000000)
2786 #define MCF5235_INTC1_IMRH_INT_MASK58 (0x04000000)
2787 #define MCF5235_INTC1_IMRH_INT_MASK59 (0x08000000)
2788 #define MCF5235_INTC1_IMRH_INT_MASK60 (0x10000000)
2789 #define MCF5235_INTC1_IMRH_INT_MASK61 (0x20000000)
2790 #define MCF5235_INTC1_IMRH_INT_MASK62 (0x40000000)
2791 #define MCF5235_INTC1_IMRH_INT_MASK63 (0x80000000)
2792 #define MCF5235_INTC1_IMRL_MASKALL (0x00000001)
2793 #define MCF5235_INTC1_IMRL_INT_MASK1 (0x00000002)
2794 #define MCF5235_INTC1_IMRL_INT_MASK2 (0x00000004)
2795 #define MCF5235_INTC1_IMRL_INT_MASK3 (0x00000008)
2796 #define MCF5235_INTC1_IMRL_INT_MASK4 (0x00000010)
2797 #define MCF5235_INTC1_IMRL_INT_MASK5 (0x00000020)
2798 #define MCF5235_INTC1_IMRL_INT_MASK6 (0x00000040)
2799 #define MCF5235_INTC1_IMRL_INT_MASK7 (0x00000080)
2800 #define MCF5235_INTC1_IMRL_INT_MASK8 (0x00000100)
2801 #define MCF5235_INTC1_IMRL_INT_MASK9 (0x00000200)
2802 #define MCF5235_INTC1_IMRL_INT_MASK10 (0x00000400)
2803 #define MCF5235_INTC1_IMRL_INT_MASK11 (0x00000800)
2804 #define MCF5235_INTC1_IMRL_INT_MASK12 (0x00001000)
2805 #define MCF5235_INTC1_IMRL_INT_MASK13 (0x00002000)
2806 #define MCF5235_INTC1_IMRL_INT_MASK14 (0x00004000)
2807 #define MCF5235_INTC1_IMRL_INT_MASK15 (0x00008000)
2808 #define MCF5235_INTC1_IMRL_INT_MASK16 (0x00010000)
2809 #define MCF5235_INTC1_IMRL_INT_MASK17 (0x00020000)
2810 #define MCF5235_INTC1_IMRL_INT_MASK18 (0x00040000)
2811 #define MCF5235_INTC1_IMRL_INT_MASK19 (0x00080000)
2812 #define MCF5235_INTC1_IMRL_INT_MASK20 (0x00100000)
2813 #define MCF5235_INTC1_IMRL_INT_MASK21 (0x00200000)
2814 #define MCF5235_INTC1_IMRL_INT_MASK22 (0x00400000)
2815 #define MCF5235_INTC1_IMRL_INT_MASK23 (0x00800000)
2816 #define MCF5235_INTC1_IMRL_INT_MASK24 (0x01000000)
2817 #define MCF5235_INTC1_IMRL_INT_MASK25 (0x02000000)
2818 #define MCF5235_INTC1_IMRL_INT_MASK26 (0x04000000)
2819 #define MCF5235_INTC1_IMRL_INT_MASK27 (0x08000000)
2820 #define MCF5235_INTC1_IMRL_INT_MASK28 (0x10000000)
2821 #define MCF5235_INTC1_IMRL_INT_MASK29 (0x20000000)
2822 #define MCF5235_INTC1_IMRL_INT_MASK30 (0x40000000)
2823 #define MCF5235_INTC1_IMRL_INT_MASK31 (0x80000000)
2824 #define MCF5235_INTC1_INTFRCH_INTFRC32 (0x00000001)
2825 #define MCF5235_INTC1_INTFRCH_INTFRC33 (0x00000002)
2826 #define MCF5235_INTC1_INTFRCH_INTFRC34 (0x00000004)
2827 #define MCF5235_INTC1_INTFRCH_INTFRC35 (0x00000008)
2828 #define MCF5235_INTC1_INTFRCH_INTFRC36 (0x00000010)
2829 #define MCF5235_INTC1_INTFRCH_INTFRC37 (0x00000020)
2830 #define MCF5235_INTC1_INTFRCH_INTFRC38 (0x00000040)
2831 #define MCF5235_INTC1_INTFRCH_INTFRC39 (0x00000080)
2832 #define MCF5235_INTC1_INTFRCH_INTFRC40 (0x00000100)
2833 #define MCF5235_INTC1_INTFRCH_INTFRC41 (0x00000200)
2834 #define MCF5235_INTC1_INTFRCH_INTFRC42 (0x00000400)
2835 #define MCF5235_INTC1_INTFRCH_INTFRC43 (0x00000800)
2836 #define MCF5235_INTC1_INTFRCH_INTFRC44 (0x00001000)
2837 #define MCF5235_INTC1_INTFRCH_INTFRC45 (0x00002000)
2838 #define MCF5235_INTC1_INTFRCH_INTFRC46 (0x00004000)
2839 #define MCF5235_INTC1_INTFRCH_INTFRC47 (0x00008000)
2840 #define MCF5235_INTC1_INTFRCH_INTFRC48 (0x00010000)
2841 #define MCF5235_INTC1_INTFRCH_INTFRC49 (0x00020000)
2842 #define MCF5235_INTC1_INTFRCH_INTFRC50 (0x00040000)
2843 #define MCF5235_INTC1_INTFRCH_INTFRC51 (0x00080000)
2844 #define MCF5235_INTC1_INTFRCH_INTFRC52 (0x00100000)
2845 #define MCF5235_INTC1_INTFRCH_INTFRC53 (0x00200000)
2846 #define MCF5235_INTC1_INTFRCH_INTFRC54 (0x00400000)
2847 #define MCF5235_INTC1_INTFRCH_INTFRC55 (0x00800000)
2848 #define MCF5235_INTC1_INTFRCH_INTFRC56 (0x01000000)
2849 #define MCF5235_INTC1_INTFRCH_INTFRC57 (0x02000000)
2850 #define MCF5235_INTC1_INTFRCH_INTFRC58 (0x04000000)
2851 #define MCF5235_INTC1_INTFRCH_INTFRC59 (0x08000000)
2852 #define MCF5235_INTC1_INTFRCH_INTFRC60 (0x10000000)
2853 #define MCF5235_INTC1_INTFRCH_INTFRC61 (0x20000000)
2854 #define MCF5235_INTC1_INTFRCH_INTFRC62 (0x40000000)
2855 #define MCF5235_INTC1_INTFRCH_INTFRC63 (0x80000000)
2856 #define MCF5235_INTC1_INTFRCL_INTFRC1 (0x00000002)
2857 #define MCF5235_INTC1_INTFRCL_INTFRC2 (0x00000004)
2858 #define MCF5235_INTC1_INTFRCL_INTFRC3 (0x00000008)
2859 #define MCF5235_INTC1_INTFRCL_INTFRC4 (0x00000010)
2860 #define MCF5235_INTC1_INTFRCL_INTFRC5 (0x00000020)
2861 #define MCF5235_INTC1_INTFRCL_INT6 (0x00000040)
2862 #define MCF5235_INTC1_INTFRCL_INT7 (0x00000080)
2863 #define MCF5235_INTC1_INTFRCL_INT8 (0x00000100)
2864 #define MCF5235_INTC1_INTFRCL_INT9 (0x00000200)
2865 #define MCF5235_INTC1_INTFRCL_INT10 (0x00000400)
2866 #define MCF5235_INTC1_INTFRCL_INTFRC11 (0x00000800)
2867 #define MCF5235_INTC1_INTFRCL_INTFRC12 (0x00001000)
2868 #define MCF5235_INTC1_INTFRCL_INTFRC13 (0x00002000)
2869 #define MCF5235_INTC1_INTFRCL_INTFRC14 (0x00004000)
2870 #define MCF5235_INTC1_INTFRCL_INT15 (0x00008000)
2871 #define MCF5235_INTC1_INTFRCL_INTFRC16 (0x00010000)
2872 #define MCF5235_INTC1_INTFRCL_INTFRC17 (0x00020000)
2873 #define MCF5235_INTC1_INTFRCL_INTFRC18 (0x00040000)
2874 #define MCF5235_INTC1_INTFRCL_INTFRC19 (0x00080000)
2875 #define MCF5235_INTC1_INTFRCL_INTFRC20 (0x00100000)
2876 #define MCF5235_INTC1_INTFRCL_INTFRC21 (0x00200000)
2877 #define MCF5235_INTC1_INTFRCL_INTFRC22 (0x00400000)
2878 #define MCF5235_INTC1_INTFRCL_INTFRC23 (0x00800000)
2879 #define MCF5235_INTC1_INTFRCL_INTFRC24 (0x01000000)
2880 #define MCF5235_INTC1_INTFRCL_INTFRC25 (0x02000000)
2881 #define MCF5235_INTC1_INTFRCL_INTFRC26 (0x04000000)
2882 #define MCF5235_INTC1_INTFRCL_INTFRC27 (0x08000000)
2883 #define MCF5235_INTC1_INTFRCL_INTFRC28 (0x10000000)
2884 #define MCF5235_INTC1_INTFRCL_INTFRC29 (0x20000000)
2885 #define MCF5235_INTC1_INTFRCL_INTFRC30 (0x40000000)
2886 #define MCF5235_INTC1_INTFRCL_INTFRC31 (0x80000000)
2887 #define MCF5235_INTC1_IRLR_IRQ(x) (((x)&0x7F)<<1)
2888 #define MCF5235_INTC1_IACKLPR_PRI(x) (((x)&0x0F)<<0)
2889 #define MCF5235_INTC1_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
2890 
2891 /*********************************************************************
2892 *
2893 * Programmable Interrupt Timer Modules (PIT)
2894 *
2895 *********************************************************************/
2896 
2897 /* Register read/write macros */
2898 #define MCF5235_PIT_PCSR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x150000)))
2899 #define MCF5235_PIT_PMR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x150002)))
2900 #define MCF5235_PIT_PCNTR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x150004)))
2901 #define MCF5235_PIT_PCSR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x160000)))
2902 #define MCF5235_PIT_PMR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x160002)))
2903 #define MCF5235_PIT_PCNTR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x160004)))
2904 #define MCF5235_PIT_PCSR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x170000)))
2905 #define MCF5235_PIT_PMR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x170002)))
2906 #define MCF5235_PIT_PCNTR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x170004)))
2907 #define MCF5235_PIT_PCSR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x180000)))
2908 #define MCF5235_PIT_PMR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x180002)))
2909 #define MCF5235_PIT_PCNTR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x180004)))
2910 #define MCF5235_PIT_PCSR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x150000+((x)*0x10000))))
2911 #define MCF5235_PIT_PMR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x150002+((x)*0x10000))))
2912 #define MCF5235_PIT_PCNTR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x150004+((x)*0x10000))))
2913 #define MCF5235_PIT_PCSR_EN (0x0001)
2914 #define MCF5235_PIT_PCSR_RLD (0x0002)
2915 #define MCF5235_PIT_PCSR_PIF (0x0004)
2916 #define MCF5235_PIT_PCSR_PIE (0x0008)
2917 #define MCF5235_PIT_PCSR_OVW (0x0010)
2918 #define MCF5235_PIT_PCSR_HALTED (0x0020)
2919 #define MCF5235_PIT_PCSR_DOZE (0x0040)
2920 #define MCF5235_PIT_PCSR_PRE(x) (((x)&0x000F)<<8)
2921 #define MCF5235_PIT_PMR_PM0 (0x0001)
2922 #define MCF5235_PIT_PMR_PM1 (0x0002)
2923 #define MCF5235_PIT_PMR_PM2 (0x0004)
2924 #define MCF5235_PIT_PMR_PM3 (0x0008)
2925 #define MCF5235_PIT_PMR_PM4 (0x0010)
2926 #define MCF5235_PIT_PMR_PM5 (0x0020)
2927 #define MCF5235_PIT_PMR_PM6 (0x0040)
2928 #define MCF5235_PIT_PMR_PM7 (0x0080)
2929 #define MCF5235_PIT_PMR_PM8 (0x0100)
2930 #define MCF5235_PIT_PMR_PM9 (0x0200)
2931 #define MCF5235_PIT_PMR_PM10 (0x0400)
2932 #define MCF5235_PIT_PMR_PM11 (0x0800)
2933 #define MCF5235_PIT_PMR_PM12 (0x1000)
2934 #define MCF5235_PIT_PMR_PM13 (0x2000)
2935 #define MCF5235_PIT_PMR_PM14 (0x4000)
2936 #define MCF5235_PIT_PMR_PM15 (0x8000)
2937 #define MCF5235_PIT_PCNTR_PC0 (0x0001)
2938 #define MCF5235_PIT_PCNTR_PC1 (0x0002)
2939 #define MCF5235_PIT_PCNTR_PC2 (0x0004)
2940 #define MCF5235_PIT_PCNTR_PC3 (0x0008)
2941 #define MCF5235_PIT_PCNTR_PC4 (0x0010)
2942 #define MCF5235_PIT_PCNTR_PC5 (0x0020)
2943 #define MCF5235_PIT_PCNTR_PC6 (0x0040)
2944 #define MCF5235_PIT_PCNTR_PC7 (0x0080)
2945 #define MCF5235_PIT_PCNTR_PC8 (0x0100)
2946 #define MCF5235_PIT_PCNTR_PC9 (0x0200)
2947 #define MCF5235_PIT_PCNTR_PC10 (0x0400)
2948 #define MCF5235_PIT_PCNTR_PC11 (0x0800)
2949 #define MCF5235_PIT_PCNTR_PC12 (0x1000)
2950 #define MCF5235_PIT_PCNTR_PC13 (0x2000)
2951 #define MCF5235_PIT_PCNTR_PC14 (0x4000)
2952 #define MCF5235_PIT_PCNTR_PC15 (0x8000)
2953 
2954 /*********************************************************************
2955 *
2956 * Queued Serial Peripheral Interface (QSPI)
2957 *
2958 *********************************************************************/
2959 
2960 /* Register read/write macros */
2961 #define MCF5235_QSPI_QMR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000340)))
2962 #define MCF5235_QSPI_QDLYR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000344)))
2963 #define MCF5235_QSPI_QWR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000348)))
2964 #define MCF5235_QSPI_QIR (*(vuint16*)((uintptr_t)__IPSBAR + (0x00034C)))
2965 #define MCF5235_QSPI_QAR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000350)))
2966 #define MCF5235_QSPI_QDR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000354)))
2967 
2968 /* Bit definitions and macros for MCF5235_QSPI_QMR */
2969 #define MCF5235_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0)
2970 #define MCF5235_QSPI_QMR_CPHA (0x0100)
2971 #define MCF5235_QSPI_QMR_CPOL (0x0200)
2972 #define MCF5235_QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
2973 #define MCF5235_QSPI_QMR_DOHIE (0x4000)
2974 #define MCF5235_QSPI_QMR_MSTR (0x8000)
2975 #define MCF5235_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0)
2976 #define MCF5235_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
2977 #define MCF5235_QSPI_QDLYR_SPE (0x8000)
2978 #define MCF5235_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0)
2979 #define MCF5235_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
2980 #define MCF5235_QSPI_QWR_CSIV (0x1000)
2981 #define MCF5235_QSPI_QWR_WRTO (0x2000)
2982 #define MCF5235_QSPI_QWR_WREN (0x4000)
2983 #define MCF5235_QSPI_QWR_HALT (0x8000)
2984 #define MCF5235_QSPI_QIR_SPIF (0x0001)
2985 #define MCF5235_QSPI_QIR_ABRT (0x0004)
2986 #define MCF5235_QSPI_QIR_WCEF (0x0008)
2987 #define MCF5235_QSPI_QIR_SPIFE (0x0100)
2988 #define MCF5235_QSPI_QIR_ABRTE (0x0400)
2989 #define MCF5235_QSPI_QIR_WCEFE (0x0800)
2990 #define MCF5235_QSPI_QIR_ABRTL (0x1000)
2991 #define MCF5235_QSPI_QIR_ABRTB (0x4000)
2992 #define MCF5235_QSPI_QIR_WCEFB (0x8000)
2993 #define MCF5235_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0)
2994 
2995 /********************************************************************/
2996 
2997 
2998 #endif /* _CPU_MCF5235_H */
__IPSBAR
#define __IPSBAR
Definition: bsp.h:40
vuint8
volatile unsigned char vuint8
Definition: bsp.h:40
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