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#define | M360_RCCR_TIME (1<<15) /* Enable timer */ |
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#define | M360_RCCR_TIMEP(x) ((x)<<8) /* Timer period */ |
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#define | M360_TM_CMD_V (1<<31) /* Set to enable timer */ |
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#define | M360_TM_CMD_R (1<<30) /* Set for automatic restart */ |
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#define | M360_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */ |
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#define | M360_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */ |
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#define | M360_RFCR_MOT (1<<4) |
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#define | M360_RFCR_DMA_SPACE 0x8 |
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#define | M360_TFCR_MOT (1<<4) |
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#define | M360_TFCR_DMA_SPACE 0x8 |
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#define | M360_SMCMR_CLEN(x) ((x)<<11) /* Character length */ |
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#define | M360_SMCMR_2STOP (1<<10) /* 2 stop bits */ |
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#define | M360_SMCMR_PARITY (1<<9) /* Enable parity */ |
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#define | M360_SMCMR_EVEN (1<<8) /* Even parity */ |
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#define | M360_SMCMR_SM_GCI (0<<4) /* GCI Mode */ |
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#define | M360_SMCMR_SM_UART (2<<4) /* UART Mode */ |
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#define | M360_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */ |
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#define | M360_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */ |
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#define | M360_SMCMR_DM_ECHO (2<<2) /* Echo mode */ |
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#define | M360_SMCMR_TEN (1<<1) /* Enable transmitter */ |
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#define | M360_SMCMR_REN (1<<0) /* Enable receiver */ |
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#define | M360_SMCE_BRK (1<<4) |
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#define | M360_SMCE_BSY (1<<2) |
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#define | M360_SMCE_TX (1<<1) |
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#define | M360_SMCE_RX (1<<0) |
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#define | M360_SPMODE_LOOP (1<<14) /* Local loopback mode */ |
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#define | M360_SPMODE_CI (1<<13) /* Clock invert */ |
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#define | M360_SPMODE_CP (1<<12) /* Clock phase */ |
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#define | M360_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */ |
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#define | M360_SPMODE_REV (1<<10) /* Reverse data */ |
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#define | M360_SPMODE_MASTER (1<<9) /* SPI is master */ |
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#define | M360_SPMODE_EN (1<<8) /* Enable SPI */ |
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#define | M360_SPMODE_CLEN(x) ((x)<<4) /* Character length */ |
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#define | M360_SPMODE_PM(x) (x) /* Prescaler modulus */ |
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#define | M360_SPCOM_STR (1<<7) /* Start transmit */ |
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#define | M360_SPIE_MME (1<<5) /* Multi-master error */ |
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#define | M360_SPIE_TXE (1<<4) /* Tx error */ |
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#define | M360_SPIE_BSY (1<<2) /* Busy condition*/ |
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#define | M360_SPIE_TXB (1<<1) /* Tx buffer */ |
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#define | M360_SPIE_RXB (1<<0) /* Rx buffer */ |
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#define | M360_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ |
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#define | M360_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ |
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#define | M360_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ |
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#define | M360_BD_LAST (1<<11) /* Ethernet, SPI */ |
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#define | M360_BD_CONTROL_CHAR (1<<11) /* SCC UART */ |
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#define | M360_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ |
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#define | M360_BD_ADDRESS (1<<10) /* SCC UART */ |
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#define | M360_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ |
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#define | M360_BD_MISS (1<<8) /* Ethernet */ |
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#define | M360_BD_IDLE (1<<8) /* SCC UART, SMC UART */ |
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#define | M360_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ |
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#define | M360_BD_LONG (1<<5) /* Ethernet */ |
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#define | M360_BD_BREAK (1<<5) /* SCC UART, SMC UART */ |
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#define | M360_BD_NONALIGNED (1<<4) /* Ethernet */ |
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#define | M360_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ |
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#define | M360_BD_SHORT (1<<3) /* Ethernet */ |
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#define | M360_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ |
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#define | M360_BD_CRC_ERROR (1<<2) /* Ethernet */ |
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#define | M360_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ |
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#define | M360_BD_COLLISION (1<<0) /* Ethernet */ |
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#define | M360_BD_CARRIER_LOST (1<<0) /* SCC UART */ |
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#define | M360_BD_MASTER_ERROR (1<<0) /* SPI */ |
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#define | M360_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ |
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#define | M360_BD_PAD (1<<14) /* Ethernet */ |
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#define | M360_BD_CTS_REPORT (1<<11) /* SCC UART */ |
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#define | M360_BD_TX_CRC (1<<10) /* Ethernet */ |
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#define | M360_BD_DEFER (1<<9) /* Ethernet */ |
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#define | M360_BD_HEARTBEAT (1<<8) /* Ethernet */ |
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#define | M360_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ |
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#define | M360_BD_LATE_COLLISION (1<<7) /* Ethernet */ |
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#define | M360_BD_NO_STOP_BIT (1<<7) /* SCC UART */ |
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#define | M360_BD_RETRY_LIMIT (1<<6) /* Ethernet */ |
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#define | M360_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ |
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#define | M360_BD_UNDERRUN (1<<1) /* Ethernet, SPI */ |
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#define | M360_BD_CARRIER_LOST (1<<0) /* Ethernet */ |
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#define | M360_BD_CTS_LOST (1<<0) /* SCC UART */ |
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#define | M360_CR_RST (1<<15) /* Reset communication processor */ |
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#define | M360_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */ |
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#define | M360_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */ |
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#define | M360_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */ |
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#define | M360_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */ |
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#define | M360_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */ |
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#define | M360_CR_OP_GR_STOP_TX (5<<8) /* SCC */ |
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#define | M360_CR_OP_INIT_IDMA (5<<8) /* IDMA */ |
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#define | M360_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */ |
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#define | M360_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */ |
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#define | M360_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */ |
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#define | M360_CR_OP_SET_TIMER (8<<8) /* Timer */ |
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#define | M360_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */ |
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#define | M360_CR_OP_RESERT_BCS (10<<8) /* SCC */ |
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#define | M360_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */ |
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#define | M360_CR_CHAN_SCC1 (0<<4) /* Channel selection */ |
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#define | M360_CR_CHAN_SCC2 (4<<4) |
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#define | M360_CR_CHAN_SPI (5<<4) |
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#define | M360_CR_CHAN_TIMER (5<<4) |
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#define | M360_CR_CHAN_SCC3 (8<<4) |
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#define | M360_CR_CHAN_SMC1 (9<<4) |
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#define | M360_CR_CHAN_IDMA1 (9<<4) |
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#define | M360_CR_CHAN_SCC4 (12<<4) |
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#define | M360_CR_CHAN_SMC2 (13<<4) |
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#define | M360_CR_CHAN_IDMA2 (13<<4) |
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#define | M360_CR_FLG (1<<0) /* Command flag */ |
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#define | M360_SYPCR_SWE (1<<7) /* Software watchdog enable */ |
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#define | M360_SYPCR_SWRI (1<<6) /* Software watchdog reset select */ |
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#define | M360_SYPCR_SWT1 (1<<5) /* Software watchdog timing bit 1 */ |
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#define | M360_SYPCR_SWT0 (1<<4) /* Software watchdog timing bit 0 */ |
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#define | M360_SYPCR_DBFE (1<<3) /* Double bus fault monitor enable */ |
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#define | M360_SYPCR_BME (1<<2) /* Bus monitor external enable */ |
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#define | M360_SYPCR_BMT1 (1<<1) /* Bus monitor timing bit 1 */ |
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#define | M360_SYPCR_BMT0 (1<<0) /* Bus monitor timing bit 0 */ |
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#define | M360_GMR_RCNT(x) ((x)<<24) /* Refresh count */ |
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#define | M360_GMR_RFEN (1<<23) /* Refresh enable */ |
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#define | M360_GMR_RCYC(x) ((x)<<21) /* Refresh cycle length */ |
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#define | M360_GMR_PGS(x) ((x)<<18) /* Page size */ |
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#define | M360_GMR_DPS_32BIT (0<<16) /* DRAM port size */ |
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#define | M360_GMR_DPS_16BIT (1<<16) |
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#define | M360_GMR_DPS_8BIT (2<<16) |
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#define | M360_GMR_DPS_DSACK (3<<16) |
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#define | M360_GMR_WBT40 (1<<15) /* Wait between 040 transfers */ |
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#define | M360_GMR_WBTQ (1<<14) /* Wait between 360 transfers */ |
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#define | M360_GMR_SYNC (1<<13) /* Synchronous external access */ |
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#define | M360_GMR_EMWS (1<<12) /* External master wait state */ |
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#define | M360_GMR_OPAR (1<<11) /* Odd parity */ |
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#define | M360_GMR_PBEE (1<<10) /* Parity bus error enable */ |
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#define | M360_GMR_TSS40 (1<<9) /* TS* sample for 040 */ |
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#define | M360_GMR_NCS (1<<8) /* No CPU space */ |
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#define | M360_GMR_DWQ (1<<7) /* Delay write for 360 */ |
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#define | M360_GMR_DW40 (1<<6) /* Delay write for 040 */ |
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#define | M360_GMR_GAMX (1<<5) /* Global address mux enable */ |
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#define | M360_MEMC_BR_FC(x) ((x)<<7) /* Function code limit */ |
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#define | M360_MEMC_BR_TRLXQ (1<<6) /* Relax timing requirements */ |
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#define | M360_MEMC_BR_BACK40 (1<<5) /* Burst acknowledge to 040 */ |
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#define | M360_MEMC_BR_CSNT40 (1<<4) /* CS* negate timing for 040 */ |
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#define | M360_MEMC_BR_CSNTQ (1<<3) /* CS* negate timing for 360 */ |
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#define | M360_MEMC_BR_PAREN (1<<2) /* Enable parity checking */ |
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#define | M360_MEMC_BR_WP (1<<1) /* Write Protect */ |
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#define | M360_MEMC_BR_V (1<<0) /* Base/Option register are valid */ |
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#define | M360_MEMC_OR_TCYC(x) ((x)<<28) /* Cycle length (clocks) */ |
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#define | M360_MEMC_OR_WAITS(x) M360_MEMC_OR_TCYC((x)+1) |
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#define | M360_MEMC_OR_2KB 0x0FFFF800 /* Address range */ |
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#define | M360_MEMC_OR_4KB 0x0FFFF000 |
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#define | M360_MEMC_OR_8KB 0x0FFFE000 |
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#define | M360_MEMC_OR_16KB 0x0FFFC000 |
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#define | M360_MEMC_OR_32KB 0x0FFF8000 |
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#define | M360_MEMC_OR_64KB 0x0FFF0000 |
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#define | M360_MEMC_OR_128KB 0x0FFE0000 |
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#define | M360_MEMC_OR_256KB 0x0FFC0000 |
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#define | M360_MEMC_OR_512KB 0x0FF80000 |
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#define | M360_MEMC_OR_1MB 0x0FF00000 |
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#define | M360_MEMC_OR_2MB 0x0FE00000 |
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#define | M360_MEMC_OR_4MB 0x0FC00000 |
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#define | M360_MEMC_OR_8MB 0x0F800000 |
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#define | M360_MEMC_OR_16MB 0x0F000000 |
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#define | M360_MEMC_OR_32MB 0x0E000000 |
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#define | M360_MEMC_OR_64MB 0x0C000000 |
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#define | M360_MEMC_OR_128MB 0x08000000 |
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#define | M360_MEMC_OR_256MB 0x00000000 |
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#define | M360_MEMC_OR_FCMC(x) ((x)<<7) /* Function code mask */ |
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#define | M360_MEMC_OR_BCYC(x) ((x)<<5) /* Burst cycle length (clocks) */ |
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#define | M360_MEMC_OR_PGME (1<<3) /* Page mode enable */ |
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#define | M360_MEMC_OR_32BIT (0<<1) /* Port size */ |
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#define | M360_MEMC_OR_16BIT (1<<1) |
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#define | M360_MEMC_OR_8BIT (2<<1) |
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#define | M360_MEMC_OR_DSACK (3<<1) |
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#define | M360_MEMC_OR_DRAM (1<<0) /* Dynamic RAM select */ |
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#define | M360_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */ |
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#define | M360_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */ |
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#define | M360_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */ |
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#define | M360_SI_SMC2_BRG2 (1<<28) |
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#define | M360_SI_SMC2_BRG3 (2<<28) |
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#define | M360_SI_SMC2_BRG4 (3<<28) |
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#define | M360_SI_SMC2_CLK5 (0<<28) |
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#define | M360_SI_SMC2_CLK6 (1<<28) |
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#define | M360_SI_SMC2_CLK7 (2<<28) |
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#define | M360_SI_SMC2_CLK8 (3<<28) |
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#define | M360_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */ |
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#define | M360_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */ |
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#define | M360_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */ |
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#define | M360_SI_SMC1_BRG2 (1<<12) |
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#define | M360_SI_SMC1_BRG3 (2<<12) |
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#define | M360_SI_SMC1_BRG4 (3<<12) |
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#define | M360_SI_SMC1_CLK1 (0<<12) |
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#define | M360_SI_SMC1_CLK2 (1<<12) |
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#define | M360_SI_SMC1_CLK3 (2<<12) |
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#define | M360_SI_SMC1_CLK4 (3<<12) |
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#define | M360_SDMA_FREEZE (2<<13) /* Freeze on next bus cycle */ |
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#define | M360_SDMA_SISM_7 (7<<8) /* Normal interrupt service mask */ |
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#define | M360_SDMA_SAID_4 (4<<4) /* Normal arbitration ID */ |
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#define | M360_SDMA_INTE (1<<1) /* SBER interrupt enable */ |
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#define | M360_SDMA_INTB (1<<0) /* SBKP interrupt enable */ |
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#define | M360_BRG_RST (1<<17) /* Reset generator */ |
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#define | M360_BRG_EN (1<<16) /* Enable generator */ |
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#define | M360_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ |
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#define | M360_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */ |
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#define | M360_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */ |
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#define | M360_BRG_ATB (1<<13) /* Autobaud */ |
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#define | M360_BRG_115200 (13<<1) /* Assume 25 MHz clock */ |
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#define | M360_BRG_57600 (26<<1) |
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#define | M360_BRG_38400 (40<<1) |
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#define | M360_BRG_19200 (80<<1) |
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#define | M360_BRG_9600 (162<<1) |
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#define | M360_BRG_4800 (324<<1) |
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#define | M360_BRG_2400 (650<<1) |
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#define | M360_BRG_1200 (1301<<1) |
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#define | M360_BRG_600 (2603<<1) |
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#define | M360_BRG_300 ((324<<1) | 1) |
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#define | M360_BRG_150 ((650<<1) | 1) |
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#define | M360_BRG_75 ((1301<<1) | 1) |
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#define | M360_PB_SPI_MISO_MSK (1<< 3) |
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#define | M360_PB_SPI_MOSI_MSK (1<< 2) |
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#define | M360_PB_SPI_CLK_MSK (1<< 1) |
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1.8.15