7 #ifndef IRQ_SHARED_IRQ_C_GLUE_H 8 #define IRQ_SHARED_IRQ_C_GLUE_H 20 #ifndef BSP_SHARED_HANDLER_SUPPORT 21 #define BSP_SHARED_HANDLER_SUPPORT 1 41 extern void BSP_enable_irq_at_pic(
const rtems_irq_number irqLine);
46 extern int BSP_disable_irq_at_pic(
const rtems_irq_number irqLine);
73 bsp_irq_dispatch_list_base(
76 rtems_irq_hdl sentinel
80 for( vchain = &tbl[irq];
81 ((intptr_t)vchain != -1 && vchain->hdl != sentinel);
84 vchain->hdl(vchain->handle);
100 bsp_irq_dispatch_list(
103 rtems_irq_hdl sentinel
106 register uint32_t l_orig;
114 bsp_irq_dispatch_list_base( tbl, irq, sentinel );
Definition: deflate.c:115
#define _ISR_Get_level()
Return current interrupt level.
Definition: isrlevel.h:128
#define _ISR_Set_level(_new_level)
Set current interrupt level.
Definition: isrlevel.h:140
The set of registers that specifies the complete processor state.
Definition: cpu.h:629