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RTEMS
5.1
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29 #ifndef IMX_IOMUXREG_H 30 #define IMX_IOMUXREG_H 32 #define IMX_IOMUXREG_LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) 33 #define IMX_IOMUXREG_SHIFTIN(__x, __mask) ((__x) * IMX_IOMUXREG_LOWEST_SET_BIT(__mask)) 35 #define IMX_IOMUXREG_BIT(n) (1 << (n)) 36 #define IMX_IOMUXREG_BITS(__m, __n) \ 37 ((IMX_IOMUXREG_BIT(MAX((__m), (__n)) + 1) - 1) ^ (IMX_IOMUXREG_BIT(MIN((__m), (__n))) - 1)) 39 #define IOMUXC_GPR0 0x00 40 #define IOMUXC_GPR1 0x04 41 #define IOMUXC_GPR2 0x08 42 #define IOMUXC_GPR3 0x0C 43 #define IOMUXC_GPR3_HDMI_MASK (3 << 2) 44 #define IOMUXC_GPR3_HDMI_IPU1_DI0 (0 << 2) 45 #define IOMUXC_GPR3_HDMI_IPU1_DI1 (1 << 2) 46 #define IOMUXC_GPR3_HDMI_IPU2_DI0 (2 << 2) 47 #define IOMUXC_GPR3_HDMI_IPU2_DI1 (3 << 2) 49 #define IOMUX_GPR13 0x34 50 #define IOMUX_GPR13_SATA_PHY_8(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(26, 24)) 51 #define IOMUX_GPR13_SATA_PHY_7(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(23, 19)) 52 #define IOMUX_GPR13_SATA_PHY_6(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(18, 16)) 53 #define IOMUX_GPR13_SATA_SPEED(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 15)) 54 #define IOMUX_GPR13_SATA_PHY_5(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 14)) 55 #define IOMUX_GPR13_SATA_PHY_4(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(13, 11)) 56 #define IOMUX_GPR13_SATA_PHY_3(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(10, 7)) 57 #define IOMUX_GPR13_SATA_PHY_2(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(6, 2)) 58 #define IOMUX_GPR13_SATA_PHY_1(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 1)) 59 #define IOMUX_GPR13_SATA_PHY_0(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 0))