|
#define | BCM2835_CLOCK_FREQ 250000000 |
|
#define | BCM2835_TIMER_BASE (RPI_PERIPHERAL_BASE + 0xB400) |
|
#define | BCM2835_TIMER_LOD (BCM2835_TIMER_BASE + 0x00) |
|
#define | BCM2835_TIMER_VAL (BCM2835_TIMER_BASE + 0x04) |
|
#define | BCM2835_TIMER_CTL (BCM2835_TIMER_BASE + 0x08) |
|
#define | BCM2835_TIMER_CLI (BCM2835_TIMER_BASE + 0x0C) |
|
#define | BCM2835_TIMER_RIS (BCM2835_TIMER_BASE + 0x10) |
|
#define | BCM2835_TIMER_MIS (BCM2835_TIMER_BASE + 0x14) |
|
#define | BCM2835_TIMER_RLD (BCM2835_TIMER_BASE + 0x18) |
|
#define | BCM2835_TIMER_DIV (BCM2835_TIMER_BASE + 0x1C) |
|
#define | BCM2835_TIMER_CNT (BCM2835_TIMER_BASE + 0x20) |
|
#define | BCM2835_TIMER_PRESCALE 0xF9 |
|
|
#define | BCM2835_PM_PASSWD_MAGIC 0x5a000000 |
|
#define | BCM2835_PM_BASE (RPI_PERIPHERAL_BASE + 0x100000) |
|
#define | BCM2835_PM_GNRIC (BCM2835_PM_BASE + 0x00) |
|
#define | BCM2835_PM_GNRIC_POWUP 0x00000001 |
|
#define | BCM2835_PM_GNRIC_POWOK 0x00000002 |
|
#define | BCM2835_PM_GNRIC_ISPOW 0x00000004 |
|
#define | BCM2835_PM_GNRIC_MEMREP 0x00000008 |
|
#define | BCM2835_PM_GNRIC_MRDONE 0x00000010 |
|
#define | BCM2835_PM_GNRIC_ISFUNC 0x00000020 |
|
#define | BCM2835_PM_GNRIC_RSTN 0x00000fc0 |
|
#define | BCM2835_PM_GNRIC_ENAB 0x00001000 |
|
#define | BCM2835_PM_GNRIC_CFG 0x007f0000 |
|
#define | BCM2835_PM_AUDIO (BCM2835_PM_BASE + 0x04) |
|
#define | BCM2835_PM_AUDIO_APSM 0x000fffff |
|
#define | BCM2835_PM_AUDIO_CTRLEN 0x00100000 |
|
#define | BCM2835_PM_AUDIO_RSTN 0x00200000 |
|
#define | BCM2835_PM_STATUS (BCM2835_PM_BASE + 0x18) |
|
#define | BCM2835_PM_RSTC (BCM2835_PM_BASE + 0x1c) |
|
#define | BCM2835_PM_RSTC_DRCFG 0x00000003 |
|
#define | BCM2835_PM_RSTC_WRCFG 0x00000030 |
|
#define | BCM2835_PM_RSTC_WRCFG_FULL 0x00000020 |
|
#define | BCM2835_PM_RSTC_SRCFG 0x00000300 |
|
#define | BCM2835_PM_RSTC_QRCFG 0x00003000 |
|
#define | BCM2835_PM_RSTC_FRCFG 0x00030000 |
|
#define | BCM2835_PM_RSTC_HRCFG 0x00300000 |
|
#define | BCM2835_PM_RSTS (BCM2835_PM_BASE + 0x20) |
|
#define | BCM2835_PM_RSTS_HADDRQ 0x00000001 |
|
#define | BCM2835_PM_RSTS_HADDRF 0x00000002 |
|
#define | BCM2835_PM_RSTS_HADDRH 0x00000004 |
|
#define | BCM2835_PM_RSTS_HADWRQ 0x00000010 |
|
#define | BCM2835_PM_RSTS_HADWRF 0x00000020 |
|
#define | BCM2835_PM_RSTS_HADWRH 0x00000040 |
|
#define | BCM2835_PM_RSTS_HADSRQ 0x00000100 |
|
#define | BCM2835_PM_RSTS_HADSRF 0x00000200 |
|
#define | BCM2835_PM_RSTS_HADSRH 0x00000400 |
|
#define | BCM2835_PM_RSTS_HADPOR 0x00001000 |
|
#define | BCM2835_PM_WDOG (BCM2835_PM_BASE + 0x24) |
|
|
#define | BCM2835_GPIO_REGS_BASE (RPI_PERIPHERAL_BASE + 0x200000) |
|
#define | BCM2835_GPIO_GPFSEL1 (BCM2835_GPIO_REGS_BASE + 0x04) |
|
#define | BCM2835_GPIO_GPSET0 (BCM2835_GPIO_REGS_BASE + 0x1C) |
|
#define | BCM2835_GPIO_GPCLR0 (BCM2835_GPIO_REGS_BASE + 0x28) |
|
#define | BCM2835_GPIO_GPLEV0 (BCM2835_GPIO_REGS_BASE + 0x34) |
|
#define | BCM2835_GPIO_GPEDS0 (BCM2835_GPIO_REGS_BASE + 0x40) |
|
#define | BCM2835_GPIO_GPREN0 (BCM2835_GPIO_REGS_BASE + 0x4C) |
|
#define | BCM2835_GPIO_GPFEN0 (BCM2835_GPIO_REGS_BASE + 0x58) |
|
#define | BCM2835_GPIO_GPHEN0 (BCM2835_GPIO_REGS_BASE + 0x64) |
|
#define | BCM2835_GPIO_GPLEN0 (BCM2835_GPIO_REGS_BASE + 0x70) |
|
#define | BCM2835_GPIO_GPAREN0 (BCM2835_GPIO_REGS_BASE + 0x7C) |
|
#define | BCM2835_GPIO_GPAFEN0 (BCM2835_GPIO_REGS_BASE + 0x88) |
|
#define | BCM2835_GPIO_GPPUD (BCM2835_GPIO_REGS_BASE + 0x94) |
|
#define | BCM2835_GPIO_GPPUDCLK0 (BCM2835_GPIO_REGS_BASE + 0x98) |
|
|
#define | BCM2835_AUX_BASE (RPI_PERIPHERAL_BASE + 0x215000) |
|
#define | AUX_ENABLES (BCM2835_AUX_BASE + 0x04) |
|
#define | AUX_MU_IO_REG (BCM2835_AUX_BASE + 0x40) |
|
#define | AUX_MU_IER_REG (BCM2835_AUX_BASE + 0x44) |
|
#define | AUX_MU_IIR_REG (BCM2835_AUX_BASE + 0x48) |
|
#define | AUX_MU_LCR_REG (BCM2835_AUX_BASE + 0x4C) |
|
#define | AUX_MU_MCR_REG (BCM2835_AUX_BASE + 0x50) |
|
#define | AUX_MU_LSR_REG (BCM2835_AUX_BASE + 0x54) |
|
#define | AUX_MU_MSR_REG (BCM2835_AUX_BASE + 0x58) |
|
#define | AUX_MU_SCRATCH (BCM2835_AUX_BASE + 0x5C) |
|
#define | AUX_MU_CNTL_REG (BCM2835_AUX_BASE + 0x60) |
|
#define | AUX_MU_STAT_REG (BCM2835_AUX_BASE + 0x64) |
|
#define | AUX_MU_BAUD_REG (BCM2835_AUX_BASE + 0x68) |
|
Register Definitions.