RTEMS
5.1
cpukit
score
cpu
bfin
include
rtems
bfin
bf533.h
Go to the documentation of this file.
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/*
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* COPYRIGHT (c) 2006.
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* Atos Automacao Industrial LTDA.
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* modified by Alain Schaefer <alain.schaefer@easc.ch>
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* and Antonio Giovanini <antonio@atos.com.br>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*
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*/
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#ifndef _RTEMS_BFIN_533_H
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#define _RTEMS_BFIN_533_H
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#include <
rtems/bfin/bfin.h
>
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/* Clock and System Control Chapter 8 */
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#define PLL_CTL 0xFFC00000L
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#define PLL_DIV 0xFFC00004L
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#define VR_CTL 0xFFC00008L
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#define PLL_STAT 0xFFC0000CL
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#define PLL_LOCKCNT 0xFFC00010L
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#define SWRST 0xFFC00100L
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#define SYSCR 0xFFC00104L
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/* SPI Controller Chapter 10 */
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#define SPI_CTL 0xFFC00500L
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#define SPI_FLG 0xFFC00504L
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#define SPI_STAT 0xFFC00508L
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#define SPI_TDBR 0xFFC0050CL
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#define SPI_RDBR 0xFFC00510L
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#define SPI_BAUD 0xFFC00514L
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#define SPI_SHADOW 0xFFC00518L
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/* SPORT0 Controller */
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#define SPORT0_TCR1 0xFFC00800L
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#define SPORT0_TCR2 0xFFC00804L
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#define SPORT0_TCLKDIV 0xFFC00808L
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#define SPORT0_TFSDIV 0xFFC0080CL
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#define SPORT0_TX 0xFFC00810L
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#define SPORT0_RX 0xFFC00818L
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#define SPORT0_RCR1 0xFFC00820L
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#define SPORT0_RCR2 0xFFC00824L
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#define SPORT0_RCLKDIV 0xFFC00828L
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#define SPORT0_RFSDIV 0xFFC0082CL
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#define SPORT0_STAT 0xFFC00830L
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#define SPORT0_CHNL 0xFFC00834L
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#define SPORT0_MCMC1 0xFFC00838L
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#define SPORT0_MCMC2 0xFFC0083CL
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#define SPORT0_MTCS0 0xFFC00840L
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#define SPORT0_MTCS1 0xFFC00844L
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#define SPORT0_MTCS2 0xFFC00848L
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#define SPORT0_MTCS3 0xFFC0084CL
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#define SPORT0_MRCS0 0xFFC00850L
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#define SPORT0_MRCS1 0xFFC00854L
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#define SPORT0_MRCS2 0xFFC00858L
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#define SPORT0_MRCS3 0xFFC0085CL
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/* Parallel Peripheral Interface (PPI) Chapter 11 */
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#define PPI_CONTROL 0xFFC01000L
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#define PPI_STATUS 0xFFC01004L
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#define PPI_COUNT 0xFFC01008L
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#define PPI_DELAY 0xFFC0100CL
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#define PPI_FRAME 0xFFC01010L
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/********* PPI MASKS ***********/
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/* PPI_CONTROL Masks */
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#define PORT_EN 0x00000001
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#define PORT_DIR 0x00000002
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#define XFR_TYPE 0x0000000C
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#define PORT_CFG 0x00000030
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#define FLD_SEL 0x00000040
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#define PACK_EN 0x00000080
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#define DMA32 0x00000100
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#define SKIP_EN 0x00000200
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#define SKIP_EO 0x00000400
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#define DLENGTH 0x00003800
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#define DLEN_8 0x0
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#define DLEN(x) (((x-9) & 0x07) << 11)
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#define POL 0x0000C000
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/* PPI_STATUS Masks */
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#define FLD 0x00000400
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#define FT_ERR 0x00000800
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#define OVR 0x00001000
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#define UNDR 0x00002000
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#define ERR_DET 0x00004000
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#define ERR_NCOR 0x00008000
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/* SPORT1 Controller Chapter 12 */
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#define SPORT1_TCR1 0xFFC00900L
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#define SPORT1_TCR2 0xFFC00904L
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#define SPORT1_TCLKDIV 0xFFC00908L
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#define SPORT1_TFSDIV 0xFFC0090CL
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#define SPORT1_TX 0xFFC00910L
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#define SPORT1_RX 0xFFC00918L
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#define SPORT1_RCR1 0xFFC00920L
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#define SPORT1_RCR2 0xFFC00924L
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#define SPORT1_RCLKDIV 0xFFC00928L
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#define SPORT1_RFSDIV 0xFFC0092CL
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#define SPORT1_STAT 0xFFC00930L
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#define SPORT1_CHNL 0xFFC00934L
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#define SPORT1_MCMC1 0xFFC00938L
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#define SPORT1_MCMC2 0xFFC0093CL
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#define SPORT1_MTCS0 0xFFC00940L
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#define SPORT1_MTCS1 0xFFC00944L
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#define SPORT1_MTCS2 0xFFC00948L
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#define SPORT1_MTCS3 0xFFC0094CL
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#define SPORT1_MRCS0 0xFFC00950L
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#define SPORT1_MRCS1 0xFFC00954L
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#define SPORT1_MRCS2 0xFFC00958L
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#define SPORT1_MRCS3 0xFFC0095CL
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/* SPORTx_TCR1 Masks */
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#define TSPEN 0x0001
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#define ITCLK 0x0002
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#define TDTYPE 0x000C
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#define TLSBIT 0x0010
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#define ITFS 0x0200
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#define TFSR 0x0400
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#define DITFS 0x0800
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#define LTFS 0x1000
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#define LATFS 0x2000
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#define TCKFE 0x4000
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/* SPORTx_TCR2 Masks */
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#define SLEN 0x001F
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#define TXSE 0x0100
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#define TSFSE 0x0200
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#define TRFST 0x0400
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/* SPORTx_RCR1 Masks */
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#define RSPEN 0x0001
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#define IRCLK 0x0002
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#define RDTYPE 0x000C
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#define RULAW 0x0008
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#define RALAW 0x000C
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#define RLSBIT 0x0010
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#define IRFS 0x0200
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#define RFSR 0x0400
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#define LRFS 0x1000
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#define LARFS 0x2000
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#define RCKFE 0x4000
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/* SPORTx_RCR2 Masks */
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#define SLEN 0x001F
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#define RXSE 0x0100
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#define RSFSE 0x0200
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#define RRFST 0x0400
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/* SPORTx_STAT Masks */
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#define RXNE 0x0001
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#define RUVF 0x0002
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#define ROVF 0x0004
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#define TXF 0x0008
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#define TUVF 0x0010
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#define TOVF 0x0020
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#define TXHRE 0x0040
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/* SPORTx_MCMC1 Masks */
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#define WSIZE 0x0000F000
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#define WOFF 0x000003FF
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/* SPORTx_MCMC2 Masks */
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#define MCCRM 0x00000003
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#define MCDTXPE 0x00000004
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#define MCDRXPE 0x00000008
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#define MCMEN 0x00000010
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#define FSDR 0x00000080
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#define MFD 0x0000F000
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/* UART Controller Chapter 13 */
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#define UART_THR 0xFFC00400L
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#define UART_RBR 0xFFC00400L
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#define UART_DLL 0xFFC00400L
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#define UART_IER 0xFFC00404L
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#define UART_DLH 0xFFC00404L
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#define UART_IIR 0xFFC00408L
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#define UART_LCR 0xFFC0040CL
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#define UART_MCR 0xFFC00410L
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#define UART_LSR 0xFFC00414L
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#define UART_SCR 0xFFC0041CL
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#define UART_GCTL 0xFFC00424L
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/*
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* UART CONTROLLER MASKS
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*/
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/* UART_LCR */
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#define DLAB 0x80
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#define SB 0x40
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#define STP 0x20
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#define EPS 0x10
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#define PEN 0x08
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#define STB 0x04
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#define WLS(x) ((x-5) & 0x03)
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#define DLAB_P 0x07
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#define SB_P 0x06
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#define STP_P 0x05
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#define EPS_P 0x04
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#define PEN_P 0x03
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#define STB_P 0x02
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#define WLS_P1 0x01
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#define WLS_P0 0x00
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/* UART_MCR */
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#define LOOP_ENA 0x10
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#define LOOP_ENA_P 0x04
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/* UART_LSR */
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#define TEMT 0x40
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#define THRE 0x20
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#define BI 0x10
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#define FE 0x08
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#define PE 0x04
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#define OE 0x02
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#define DR 0x01
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#define TEMP_P 0x06
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#define THRE_P 0x05
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#define BI_P 0x04
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#define FE_P 0x03
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#define PE_P 0x02
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#define OE_P 0x01
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#define DR_P 0x00
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/* UART_IER */
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#define ELSI 0x04
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#define ETBEI 0x02
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#define ERBFI 0x01
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#define ELSI_P 0x02
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#define ETBEI_P 0x01
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#define ERBFI_P 0x00
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/* UART_IIR */
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#define STATUS(x) ((x << 1) & 0x06)
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#define NINT 0x01
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#define STATUS_P1 0x02
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#define STATUS_P0 0x01
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#define NINT_P 0x00
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/* UART_GCTL */
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#define FFE 0x20
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#define FPE 0x10
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#define RPOLC 0x08
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#define TPOLC 0x04
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#define IREN 0x02
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#define UCEN 0x01
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#define FFE_P 0x05
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#define FPE_P 0x04
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#define RPOLC_P 0x03
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#define TPOLC_P 0x02
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#define IREN_P 0x01
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#define UCEN_P 0x00
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/* General Purpose IO Chapter 14*/
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#define FIO_FLAG_D 0xFFC00700L
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#define FIO_FLAG_C 0xFFC00704L
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#define FIO_FLAG_S 0xFFC00708L
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#define FIO_FLAG_T 0xFFC0070CL
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#define FIO_MASKA_D 0xFFC00710L
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#define FIO_MASKA_C 0xFFC00714L
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#define FIO_MASKA_S 0xFFC00718L
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#define FIO_MASKA_T 0xFFC0071CL
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#define FIO_MASKB_D 0xFFC00720L
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#define FIO_MASKB_C 0xFFC00724L
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#define FIO_MASKB_S 0xFFC00728L
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#define FIO_MASKB_T 0xFFC0072CL
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#define FIO_DIR 0xFFC00730L
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#define FIO_POLAR 0xFFC00734L
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#define FIO_EDGE 0xFFC00738L
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#define FIO_BOTH 0xFFC0073CL
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#define FIO_INEN 0xFFC00740L
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/* General Purpose IO Masks */
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#define PF0 0x0001
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#define PF1 0x0002
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#define PF2 0x0004
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#define PF3 0x0008
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#define PF4 0x0010
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#define PF5 0x0020
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#define PF6 0x0040
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#define PF7 0x0080
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#define PF8 0x0100
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#define PF9 0x0200
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#define PF10 0x0400
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#define PF11 0x0800
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#define PF12 0x1000
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#define PF13 0x2000
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#define PF14 0x4000
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#define PF15 0x8000
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/* TIMER 0, 1, 2 Chapter 15 */
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#define TIMER0_CONFIG 0xFFC00600L
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#define TIMER0_COUNTER 0xFFC00604L
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#define TIMER0_PERIOD 0xFFC00608L
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#define TIMER0_WIDTH 0xFFC0060CL
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#define TIMER1_CONFIG 0xFFC00610L
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#define TIMER1_COUNTER 0xFFC00614L
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#define TIMER1_PERIOD 0xFFC00618L
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#define TIMER1_WIDTH 0xFFC0061CL
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#define TIMER2_CONFIG 0xFFC00620L
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#define TIMER2_COUNTER 0xFFC00624L
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#define TIMER2_PERIOD 0xFFC00628L
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#define TIMER2_WIDTH 0xFFC0062CL
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/*
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* These are defined in bsps/bfin/include/bf52x.h. Ensure those definitions
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* are consistent with our expectations.
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#define TIMER_ENABLE 0xFFC00640L
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#define TIMER_DISABLE 0xFFC00644L
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#define TIMER_STATUS 0xFFC00648L
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*/
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#if ((TIMER_ENABLE != 0xFFC00640L) || \
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(TIMER_DISABLE != 0xFFC00644L) || \
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(TIMER_STATUS != 0xFFC00648L))
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#error "Timer register addresses are inconsistent"
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#endif
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/* Real Time Clock Chapter 16 */
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#define RTC_STAT 0xFFC00300L
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#define RTC_ICTL 0xFFC00304L
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#define RTC_ISTAT 0xFFC00308L
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#define RTC_SWCNT 0xFFC0030CL
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#define RTC_ALARM 0xFFC00310L
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#define RTC_FAST 0xFFC00314L
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#define RTC_PREN 0xFFC00314L
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/* RTC_FAST Mask (RTC_PREN Mask) */
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#define ENABLE_PRESCALE 0x00000001
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#define PREN 0x00000001
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/* Asynchronous Memory Controller EBUI, Chapter 17*/
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#define EBIU_AMGCTL 0xFFC00A00L
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#define EBIU_AMBCTL0 0xFFC00A04L
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#define EBIU_AMBCTL1 0xFFC00A08L
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/* SDRAM Controller External Bus Interface Unit */
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#define EBIU_SDGCTL 0xFFC00A10L
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#define EBIU_SDBCTL 0xFFC00A14L
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#define EBIU_SDRRC 0xFFC00A18L
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#define EBIU_SDSTAT 0xFFC00A1CL
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/* DCPLB_DATA and ICPLB_DATA Registers */
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/*** Bit Positions */
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#define CPLB_VALID_P 0x00000000
/* 0=invalid entry, 1=valid entry */
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#define CPLB_LOCK_P 0x00000001
/* 0=entry may be replaced, 1=entry locked */
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#define CPLB_USER_RD_P 0x00000002
/* 0=no read access, 1=read access allowed (user mode) */
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/*** Masks */
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#define CPLB_VALID 0x00000001
/* 0=invalid entry, 1=valid entry */
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#define CPLB_LOCK 0x00000002
/* 0=entry may be replaced, 1=entry locked */
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#define CPLB_USER_RD 0x00000004
/* 0=no read access, 1=read access allowed (user mode) */
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#define PAGE_SIZE_1KB 0x00000000
/* 1 KB page size */
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#define PAGE_SIZE_4KB 0x00010000
/* 4 KB page size */
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#define PAGE_SIZE_1MB 0x00020000
/* 1 MB page size */
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#define PAGE_SIZE_4MB 0x00030000
/* 4 MB page size */
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#define CPLB_PORTPRIO 0x00000200
/* 0=low priority port, 1= high priority port */
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#define CPLB_L1_CHBL 0x00001000
/* 0=non-cacheable in L1, 1=cacheable in L1 */
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/*** ICPLB_DATA only */
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#define CPLB_LRUPRIO 0x00000100
/* 0=can be replaced by any line, 1=priority for non-replacement */
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/*** DCPLB_DATA only */
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#define CPLB_USER_WR 0x00000008
/* 0=no write access, 0=write access allowed (user mode) */
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#define CPLB_SUPV_WR 0x00000010
/* 0=no write access, 0=write access allowed (supervisor mode) */
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#define CPLB_DIRTY 0x00000080
/* 1=dirty, 0=clean */
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#define CPLB_L1_AOW 0x00008000
/* 0=do not allocate cache lines on write-through writes, */
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/* 1= allocate cache lines on write-through writes. */
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#define CPLB_WT 0x00004000
/* 0=write-back, 1=write-through */
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#ifdef __cplusplus
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}
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#endif
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#endif
/* _RTEMS_SCORE_BFIN_H */
bfin.h
Macros for MMR register common to all Blackfin Processors.
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