RTEMS
5.1
Main Page
Related Pages
Modules
+
Data Structures
Data Structures
Data Structure Index
Class Hierarchy
+
Data Fields
+
All
_
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
z
+
Variables
_
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
z
+
Files
File List
+
Globals
+
All
_
a
b
c
d
e
f
g
h
i
k
l
m
n
o
p
q
r
s
t
u
v
w
x
z
+
Functions
_
a
b
c
d
e
f
g
h
i
l
m
n
o
p
q
r
s
t
u
v
w
x
z
+
Variables
_
a
b
c
d
e
f
g
i
l
m
n
o
p
r
s
t
v
w
+
Typedefs
a
b
c
d
e
f
g
h
i
l
m
o
p
q
r
s
t
u
v
w
x
+
Enumerations
a
b
c
e
h
i
l
m
o
p
q
r
s
t
w
+
Enumerator
a
c
d
h
i
l
m
p
r
s
t
w
+
Macros
_
a
b
c
d
e
f
g
h
i
k
l
m
n
o
p
q
r
s
t
u
v
w
x
•
All
Data Structures
Files
Functions
Variables
Typedefs
Enumerations
Enumerator
Macros
Modules
Pages
bsps
arm
xilinx-zynq
include
bsp
cadence-i2c.h
1
/*
2
* SPDX-License-Identifier: BSD-2-Clause
3
*
4
* Copyright (C) 2014 embedded brains GmbH
5
*
6
* Redistribution and use in source and binary forms, with or without
7
* modification, are permitted provided that the following conditions
8
* are met:
9
* 1. Redistributions of source code must retain the above copyright
10
* notice, this list of conditions and the following disclaimer.
11
* 2. Redistributions in binary form must reproduce the above copyright
12
* notice, this list of conditions and the following disclaimer in the
13
* documentation and/or other materials provided with the distribution.
14
*
15
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25
* POSSIBILITY OF SUCH DAMAGE.
26
*/
27
28
#ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_H
29
#define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_H
30
31
#include <
rtems.h
>
32
33
#ifdef __cplusplus
34
extern
"C"
{
35
#endif
/* __cplusplus */
36
37
int
i2c_bus_register_cadence(
38
const
char
*bus_path,
39
uintptr_t register_base,
40
uint32_t input_clock,
41
rtems_vector_number
irq
42
);
43
44
#ifdef __cplusplus
45
}
46
#endif
/* __cplusplus */
47
48
#endif
/* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_H */
rtems_vector_number
ISR_Vector_number rtems_vector_number
Control block type used to manage the vectors.
Definition:
intr.h:47
rtems.h
Generated by
1.8.15