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RTEMS
5.1
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16 #define SIC_BASE_ADDRESS 0xffc00100 17 #define WDOG_BASE_ADDRESS 0xffc00200 18 #define RTC_BASE_ADDRESS 0xffc00300 19 #define UART0_BASE_ADDRESS 0xffc00400 20 #define SPI_BASE_ADDRESS 0xffc00500 21 #define TIMER_BASE_ADDRESS 0xffc00600 22 #define TIMER_CHANNELS 8 23 #define TIMER_PITCH 0x10 24 #define TIMER0_BASE_ADDRESS 0xffc00600 25 #define TIMER1_BASE_ADDRESS 0xffc00610 26 #define TIMER2_BASE_ADDRESS 0xffc00620 27 #define TIMER3_BASE_ADDRESS 0xffc00630 28 #define TIMER4_BASE_ADDRESS 0xffc00640 29 #define TIMER5_BASE_ADDRESS 0xffc00650 30 #define TIMER6_BASE_ADDRESS 0xffc00660 31 #define TIMER7_BASE_ADDRESS 0xffc00670 32 #define TIMER_ENABLE 0xffc00680 33 #define TIMER_DISABLE 0xffc00684 34 #define TIMER_STATUS 0xffc00688 35 #define PORTFIO_BASE_ADDRESS 0xffc00700 36 #define SPORT0_BASE_ADDRESS 0xffc00800 37 #define SPORT1_BASE_ADDRESS 0xffc00900 38 #define EBIU_BASE_ADDRESS 0xffc00a00 39 #define DMA_TC_PER 0xffc00b0c 40 #define DMA_TC_CNT 0xffc00b10 41 #define DMA_BASE_ADDRESS 0xffc00c00 42 #define DMA_CHANNELS 12 43 #define DMA_PITCH 0x40 44 #define DMA0_BASE_ADDRESS 0xffc00c00 45 #define DMA1_BASE_ADDRESS 0xffc00c40 46 #define DMA2_BASE_ADDRESS 0xffc00c80 47 #define DMA3_BASE_ADDRESS 0xffc00cc0 48 #define DMA4_BASE_ADDRESS 0xffc00d00 49 #define DMA5_BASE_ADDRESS 0xffc00d40 50 #define DMA6_BASE_ADDRESS 0xffc00d80 51 #define DMA7_BASE_ADDRESS 0xffc00dc0 52 #define DMA8_BASE_ADDRESS 0xffc00e00 53 #define DMA9_BASE_ADDRESS 0xffc00e40 54 #define DMA10_BASE_ADDRESS 0xffc00e80 55 #define DMA11_BASE_ADDRESS 0xffc00ec0 56 #define MDMA_BASE_ADDRESS 0xffc00f00 57 #define MDMA_CHANNELS 2 59 #define MDMA_PITCH 0x80 60 #define MDMA0D_BASE_ADDRESS 0xffc00f00 61 #define MDMA0S_BASE_ADDRESS 0xffc00f40 62 #define MDMA1D_BASE_ADDRESS 0xffc00f80 63 #define MDMA1S_BASE_ADDRESS 0xffc00fc0 64 #define PPI_BASE_ADDRESS 0xffc01000 65 #define TWI_BASE_ADDRESS 0xffc01400 66 #define PORTGIO_BASE_ADDRESS 0xffc01500 67 #define PORTHIO_BASE_ADDRESS 0xffc01700 68 #define UART1_BASE_ADDRESS 0xffc02000 69 #define CAN_BASE_ADDRESS 0xffc02a00 70 #define CAN_AM_BASE_ADDRESS 0xffc02b00 71 #define CAN_MB_BASE_ADDRESS 0xffc02c00 72 #define EMAC_BASE_ADDRESS 0xffc03000 73 #define PORTF_FER 0xffc03200 74 #define PORTG_FER 0xffc03204 75 #define PORTH_FER 0xffc03208 76 #define PORT_MUX 0xffc0320c 77 #define HMDMA0_BASE_ADDRESS 0xffc03300 78 #define HMDMA1_BASE_ADDRESS 0xffc03340 83 #define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK 0xf800 84 #define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT 11 85 #define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK 0x0700 86 #define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT 8 87 #define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK 0x00f0 88 #define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT 4 89 #define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK 0x000f 90 #define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT 0 92 #define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK 0xf800 93 #define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT 11 94 #define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK 0x0700 95 #define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT 8 96 #define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK 0x00f0 97 #define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT 4 98 #define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK 0x000f 99 #define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT 0 101 #define TIMER_ENABLE_TIMEN7 0x0080 102 #define TIMER_ENABLE_TIMEN6 0x0040 103 #define TIMER_ENABLE_TIMEN5 0x0020 104 #define TIMER_ENABLE_TIMEN4 0x0010 105 #define TIMER_ENABLE_TIMEN3 0x0008 106 #define TIMER_ENABLE_TIMEN2 0x0004 107 #define TIMER_ENABLE_TIMEN1 0x0002 108 #define TIMER_ENABLE_TIMEN0 0x0001 110 #define TIMER_DISABLE_TIMDIS7 0x0080 111 #define TIMER_DISABLE_TIMDIS6 0x0040 112 #define TIMER_DISABLE_TIMDIS5 0x0020 113 #define TIMER_DISABLE_TIMDIS4 0x0010 114 #define TIMER_DISABLE_TIMDIS3 0x0008 115 #define TIMER_DISABLE_TIMDIS2 0x0004 116 #define TIMER_DISABLE_TIMDIS1 0x0002 117 #define TIMER_DISABLE_TIMDIS0 0x0001 119 #define TIMER_STATUS_TRUN7 0x80000000 120 #define TIMER_STATUS_TRUN6 0x40000000 121 #define TIMER_STATUS_TRUN5 0x20000000 122 #define TIMER_STATUS_TRUN4 0x10000000 123 #define TIMER_STATUS_TOVF_ERR7 0x00800000 124 #define TIMER_STATUS_TOVF_ERR6 0x00400000 125 #define TIMER_STATUS_TOVF_ERR5 0x00200000 126 #define TIMER_STATUS_TOVF_ERR4 0x00100000 127 #define TIMER_STATUS_TIMIL7 0x00080000 128 #define TIMER_STATUS_TIMIL6 0x00040000 129 #define TIMER_STATUS_TIMIL5 0x00020000 130 #define TIMER_STATUS_TIMIL4 0x00010000 131 #define TIMER_STATUS_TRUN3 0x00008000 132 #define TIMER_STATUS_TRUN2 0x00004000 133 #define TIMER_STATUS_TRUN1 0x00002000 134 #define TIMER_STATUS_TRUN0 0x00001000 135 #define TIMER_STATUS_TOVF_ERR3 0x00000080 136 #define TIMER_STATUS_TOVF_ERR2 0x00000040 137 #define TIMER_STATUS_TOVF_ERR1 0x00000020 138 #define TIMER_STATUS_TOVF_ERR0 0x00000010 139 #define TIMER_STATUS_TIMIL3 0x00000008 140 #define TIMER_STATUS_TIMIL2 0x00000004 141 #define TIMER_STATUS_TIMIL1 0x00000002 142 #define TIMER_STATUS_TIMIL0 0x00000001 144 #define PORT_MUX_PGTE 0x0800 145 #define PORT_MUX_PGRE 0x0400 146 #define PORT_MUX_PGSE 0x0200 147 #define PORT_MUX_PFFE 0x0100 148 #define PORT_MUX_PFS4E 0x0080 149 #define PORT_MUX_PFS5E 0x0040 150 #define PORT_MUX_PFS6E 0x0020 151 #define PORT_MUX_PFTE 0x0010 152 #define PORT_MUX_PFDE 0x0008 153 #define PORT_MUX_PJCE_MASK 0x0006 154 #define PORT_MUX_PJCE_DR0SEC_DTOSEC 0x0000 155 #define PORT_MUX_PJCE_CANRX_CANTX 0x0002 156 #define PORT_MUX_PJCE_SPISSEL7 0x0004 157 #define PORT_MUX_PJSE 0x0001 162 #define CEC_EMULATION_VECTOR 0 163 #define CEC_RESET_VECTOR 1 164 #define CEC_NMI_VECTOR 2 165 #define CEC_EXCEPTIONS_VECTOR 3 166 #define CEC_HARDWARE_ERROR_VECTOR 5 167 #define CEC_CORE_TIMER_VECTOR 6 168 #define CEC_INTERRUPT_BASE_VECTOR 7 169 #define CEC_INTERRUPT_COUNT 9 174 #define SIC_IAR_COUNT 4 176 #define SIC_PLL_WAKEUP_VECTOR 0 177 #define SIC_DMA_ERROR_VECTOR 1 178 #define SIC_DMAR0_BLOCK_DONE_VECTOR 1 179 #define SIC_DMAR1_BLOCK_DONE_VECTOR 1 180 #define SIC_DMAR0_OVERFLOW_VECTOR 1 181 #define SIC_DMAR1_OVERFLOW_VECTOR 1 182 #define SIC_CAN_ERROR_VECTOR 2 183 #define SIC_MAC_ERROR_VECTOR 2 184 #define SIC_SPORT0_ERROR_VECTOR 2 185 #define SIC_SPORT1_ERROR_VECTOR 2 186 #define SIC_PPI_ERROR_VECTOR 2 187 #define SIC_SPI_ERROR_VECTOR 2 188 #define SIC_UART0_ERROR_VECTOR 2 189 #define SIC_UART1_ERROR_VECTOR 2 190 #define SIC_RTC_VECTOR 3 191 #define SIC_DMA0_PPI_VECTOR 4 192 #define SIC_DMA3_SPORT0_RX_VECTOR 5 193 #define SIC_DMA4_SPORT0_TX_VECTOR 6 194 #define SIC_DMA5_SPORT1_RX_VECTOR 7 195 #define SIC_DMA5_SPORT1_TX_VECTOR 8 196 #define SIC_TWI_VECTOR 9 197 #define SIC_DMA7_SPI_VECTOR 10 198 #define SIC_DMA8_UART0_RX_VECTOR 11 199 #define SIC_DMA9_UART0_TX_VECTOR 12 200 #define SIC_DMA10_UART1_RX_VECTOR 13 201 #define SIC_DMA11_UART1_TX_VECTOR 14 202 #define SIC_CAN_RX_VECTOR 15 203 #define SIC_CAN_TX_VECTOR 16 204 #define SIC_DMA1_MAC_RX_VECTOR 17 205 #define SIC_PORTH_IRQ_A_VECTOR 17 206 #define SIC_DMA2_MAC_TX_VECTOR 18 207 #define SIC_PORTH_IRQ_B_VECTOR 18 208 #define SIC_TIMER0_VECTOR 19 209 #define SIC_TIMER1_VECTOR 20 210 #define SIC_TIMER2_VECTOR 21 211 #define SIC_TIMER3_VECTOR 22 212 #define SIC_TIMER4_VECTOR 23 213 #define SIC_TIMER5_VECTOR 24 214 #define SIC_TIMER6_VECTOR 25 215 #define SIC_TIMER7_VECTOR 26 216 #define SIC_PORTF_IRQ_A_VECTOR 27 217 #define SIC_PORTG_IRQ_A_VECTOR 27 218 #define SIC_PORTG_IRQ_B_VECTOR 28 219 #define SIC_MDMA0_VECTOR 29 220 #define SIC_MDMA1_VECTOR 30 221 #define SIC_WATCHDOG_VECTOR 31 222 #define SIC_PORTF_IRQ_B_VECTOR 31
1.8.15