RTEMS  5.1
arm-gic-irq.h
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1 
9 /*
10  * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved.
11  *
12  * embedded brains GmbH
13  * Dornierstr. 4
14  * 82178 Puchheim
15  * Germany
16  * <info@embedded-brains.de>
17  *
18  * The license and distribution terms for this file may be
19  * found in the file LICENSE in this distribution or at
20  * http://www.rtems.org/license/LICENSE.
21  */
22 
23 #ifndef LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H
24 #define LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H
25 
26 #include <bsp.h>
27 #include <bsp/arm-gic.h>
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif /* __cplusplus */
33 
34 #define ARM_GIC_IRQ_SGI_0 0
35 #define ARM_GIC_IRQ_SGI_1 1
36 #define ARM_GIC_IRQ_SGI_2 2
37 #define ARM_GIC_IRQ_SGI_3 3
38 #define ARM_GIC_IRQ_SGI_5 5
39 #define ARM_GIC_IRQ_SGI_6 6
40 #define ARM_GIC_IRQ_SGI_7 7
41 #define ARM_GIC_IRQ_SGI_8 8
42 #define ARM_GIC_IRQ_SGI_9 9
43 #define ARM_GIC_IRQ_SGI_10 10
44 #define ARM_GIC_IRQ_SGI_11 11
45 #define ARM_GIC_IRQ_SGI_12 12
46 #define ARM_GIC_IRQ_SGI_13 13
47 #define ARM_GIC_IRQ_SGI_14 14
48 #define ARM_GIC_IRQ_SGI_15 15
49 
50 #define ARM_GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE)
51 
52 rtems_status_code arm_gic_irq_set_priority(
53  rtems_vector_number vector,
54  uint8_t priority
55 );
56 
57 rtems_status_code arm_gic_irq_get_priority(
58  rtems_vector_number vector,
59  uint8_t *priority
60 );
61 
62 rtems_status_code arm_gic_irq_set_group(
63  rtems_vector_number vector,
64  gic_group group
65 );
66 
67 rtems_status_code arm_gic_irq_get_group(
68  rtems_vector_number vector,
69  gic_group *group
70 );
71 
72 void bsp_interrupt_set_affinity(
73  rtems_vector_number vector,
74  const Processor_mask *affinity
75 );
76 
77 void bsp_interrupt_get_affinity(
78  rtems_vector_number vector,
79  Processor_mask *affinity
80 );
81 
82 typedef enum {
83  ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
84  ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_EXCEPT_SELF,
85  ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF
86 } arm_gic_irq_software_irq_target_filter;
87 
88 void arm_gic_trigger_sgi(
89  rtems_vector_number vector,
90  arm_gic_irq_software_irq_target_filter filter,
91  uint8_t targets
92 );
93 
94 static inline rtems_status_code arm_gic_irq_generate_software_irq(
95  rtems_vector_number vector,
96  arm_gic_irq_software_irq_target_filter filter,
97  uint8_t targets
98 )
99 {
101 
102  if (vector <= ARM_GIC_IRQ_SGI_15) {
103  arm_gic_trigger_sgi(vector, filter, targets);
104  } else {
105  sc = RTEMS_INVALID_ID;
106  }
107 
108  return sc;
109 }
110 
111 static inline uint32_t arm_gic_irq_processor_count(void)
112 {
113  volatile gic_dist *dist = ARM_GIC_DIST;
114 
115  return GIC_DIST_ICDICTR_CPU_NUMBER_GET(dist->icdictr) + 1;
116 }
117 
118 void arm_gic_irq_initialize_secondary_cpu(void);
119 
120 #ifdef __cplusplus
121 }
122 #endif /* __cplusplus */
123 
124 #endif /* LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H */
Definition: status.h:47
Definition: arm-gic-regs.h:88
ISR_Vector_number rtems_vector_number
Control block type used to manage the vectors.
Definition: intr.h:47
rtems_status_code
Classic API Status.
Definition: status.h:43
ARM GIC Support.
Definition: status.h:63
Processor Mask API.