RTEMS  5.1
Data Structures | Macros
arm-a9mpcore-regs.h File Reference

ARM_A9MPCORE_REGS Support. More...

#include <bsp/utility.h>

Go to the source code of this file.

Data Structures

struct  a9mpcore_scu
 
struct  a9mpcore_gic
 
struct  a9mpcore_gt
 
struct  a9mpcore_pt
 
struct  a9mpcore_pw
 
struct  a9mpcore_idist
 
struct  a9mpcore
 

Macros

#define A9MPCORE_SCU_CTRL_SCU_EN   BSP_BIT32(0)
 
#define A9MPCORE_SCU_CTRL_ADDR_FLT_EN   BSP_BIT32(1)
 
#define A9MPCORE_SCU_CTRL_RAM_PAR_EN   BSP_BIT32(2)
 
#define A9MPCORE_SCU_CTRL_SCU_SPEC_LINE_FILL_EN   BSP_BIT32(3)
 
#define A9MPCORE_SCU_CTRL_FORCE_PORT_0_EN   BSP_BIT32(4)
 
#define A9MPCORE_SCU_CTRL_SCU_STANDBY_EN   BSP_BIT32(5)
 
#define A9MPCORE_SCU_CTRL_IC_STANDBY_EN   BSP_BIT32(6)
 
#define A9MPCORE_SCU_CFG_CPU_COUNT(val)   BSP_FLD32(val, 0, 1)
 
#define A9MPCORE_SCU_CFG_CPU_COUNT_GET(reg)   BSP_FLD32GET(reg, 0, 1)
 
#define A9MPCORE_SCU_CFG_CPU_COUNT_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 1)
 
#define A9MPCORE_SCU_CFG_SMP_MODE(val)   BSP_FLD32(val, 4, 7)
 
#define A9MPCORE_SCU_CFG_SMP_MODE_GET(reg)   BSP_FLD32GET(reg, 4, 7)
 
#define A9MPCORE_SCU_CFG_SMP_MODE_SET(reg, val)   BSP_FLD32SET(reg, val, 4, 7)
 
#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE(val)   BSP_FLD32(val, 8, 15)
 
#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_GET(reg)   BSP_FLD32GET(reg, 8, 15)
 
#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_SET(reg, val)   BSP_FLD32SET(reg, val, 8, 15)
 
#define A9MPCORE_SCU_INVSS_CPU0(ways)   BSP_FLD32(val, 0, 3)
 
#define A9MPCORE_SCU_INVSS_CPU0_GET(reg)   /* Write only register */
 
#define A9MPCORE_SCU_INVSS_CPU0_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 3)
 
#define A9MPCORE_SCU_INVSS_CPU1(ways)   BSP_FLD32(val, 4, 7)
 
#define A9MPCORE_SCU_INVSS_CPU1_GET(reg)   /* Write only register */
 
#define A9MPCORE_SCU_INVSS_CPU1_SET(reg, val)   BSP_FLD32SET(reg, val, 4, 7)
 
#define A9MPCORE_SCU_INVSS_CPU2(ways)   BSP_FLD32(val, 8, 11)
 
#define A9MPCORE_SCU_INVSS_CPU2_GET(reg)   /* Write only register */
 
#define A9MPCORE_SCU_INVSS_CPU2_SET(reg, val)   BSP_FLD32SET(reg, val, 8, 11)
 
#define A9MPCORE_SCU_INVSS_CPU3(ways)   BSP_FLD32(val, 12, 15)
 
#define A9MPCORE_SCU_INVSS_CPU3_GET(reg)   /* Write only register */
 
#define A9MPCORE_SCU_INVSS_CPU3_SET(reg, val)   BSP_FLD32SET(reg, val, 12, 15)
 
#define A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE   BSP_BIT32(0)
 
#define A9MPCORE_GT_CTRL_PRESCALER(val)   BSP_FLD32(val, 8, 15)
 
#define A9MPCORE_GT_CTRL_PRESCALER_GET(reg)   BSP_FLD32GET(reg, 8, 15)
 
#define A9MPCORE_GT_CTRL_PRESCALER_SET(reg, val)   BSP_FLD32SET(reg, val, 8, 15)
 
#define A9MPCORE_GT_CTRL_AUTOINC_EN   BSP_BIT32(3)
 
#define A9MPCORE_GT_CTRL_IRQ_EN   BSP_BIT32(2)
 
#define A9MPCORE_GT_CTRL_COMP_EN   BSP_BIT32(1)
 
#define A9MPCORE_GT_CTRL_TMR_EN   BSP_BIT32(0)
 
#define A9MPCORE_GT_IRQST_EFLG   BSP_BIT32(0)
 
#define A9MPCORE_PT_CTRL_PRESCALER(val)   BSP_FLD32(val, 8, 15)
 
#define A9MPCORE_PT_CTRL_PRESCALER_GET(reg)   BSP_FLD32GET(reg, 8, 15)
 
#define A9MPCORE_PT_CTRL_PRESCALER_SET(reg, val)   BSP_FLD32SET(reg, val, 8, 15)
 
#define A9MPCORE_PT_CTRL_IRQ_EN   BSP_BIT32(2)
 
#define A9MPCORE_PT_CTRL_AUTO_RLD   BSP_BIT32(1)
 
#define A9MPCORE_PT_CTRL_TMR_EN   BSP_BIT32(0)
 
#define A9MPCORE_PT_IRQST_EFLG   BSP_BIT32(0)
 

Detailed Description

ARM_A9MPCORE_REGS Support.