alt_sdr.h File Reference

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Data Structures
struct	ALT_SDR_CTL_CTLCFG_s
struct	ALT_SDR_CTL_DRAMTIMING1_s
struct	ALT_SDR_CTL_DRAMTIMING2_s
struct	ALT_SDR_CTL_DRAMTIMING3_s
struct	ALT_SDR_CTL_DRAMTIMING4_s
struct	ALT_SDR_CTL_LOWPWRTIMING_s
struct	ALT_SDR_CTL_DRAMODT_s
struct	ALT_SDR_CTL_DRAMADDRW_s
struct	ALT_SDR_CTL_DRAMIFWIDTH_s
struct	ALT_SDR_CTL_DRAMDEVWIDTH_s
struct	ALT_SDR_CTL_DRAMSTS_s
struct	ALT_SDR_CTL_DRAMINTR_s
struct	ALT_SDR_CTL_SBECOUNT_s
struct	ALT_SDR_CTL_DBECOUNT_s
struct	ALT_SDR_CTL_ERRADDR_s
struct	ALT_SDR_CTL_DROPCOUNT_s
struct	ALT_SDR_CTL_DROPADDR_s
struct	ALT_SDR_CTL_LOWPWREQ_s
struct	ALT_SDR_CTL_LOWPWRACK_s
struct	ALT_SDR_CTL_STATICCFG_s
struct	ALT_SDR_CTL_CTLWIDTH_s
struct	ALT_SDR_CTL_PORTCFG_s
struct	ALT_SDR_CTL_FPGAPORTRST_s
struct	ALT_SDR_CTL_PROTPORTDEFAULT_s
struct	ALT_SDR_CTL_PROTRULEADDR_s
struct	ALT_SDR_CTL_PROTRULEID_s
struct	ALT_SDR_CTL_PROTRULEDATA_s
struct	ALT_SDR_CTL_PROTRULERDWR_s
struct	ALT_SDR_CTL_QOSLOWPRI_s
struct	ALT_SDR_CTL_QOSHIGHPRI_s
struct	ALT_SDR_CTL_QOSPRIORITYEN_s
struct	ALT_SDR_CTL_MPPRIORITY_s
struct	ALT_SDR_CTL_REMAPPRIORITY_s
struct	ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s
struct	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s
struct	ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s
struct	ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s
struct	ALT_SDR_CTL_MPWT_s
struct	ALT_SDR_CTL_MPWT_raw_s
struct	ALT_SDR_CTL_s
struct	ALT_SDR_CTL_raw_s
struct	ALT_SDR_s
struct	ALT_SDR_raw_s

Macros
#define	ALT_SDR_CTL_CTLCFG_MEMTYPE_LSB   0
#define	ALT_SDR_CTL_CTLCFG_MEMTYPE_MSB   2
#define	ALT_SDR_CTL_CTLCFG_MEMTYPE_WIDTH   3
#define	ALT_SDR_CTL_CTLCFG_MEMTYPE_SET_MSK   0x00000007
#define	ALT_SDR_CTL_CTLCFG_MEMTYPE_CLR_MSK   0xfffffff8
#define	ALT_SDR_CTL_CTLCFG_MEMTYPE_RESET   0x0
#define	ALT_SDR_CTL_CTLCFG_MEMTYPE_GET(value)   (((value) & 0x00000007) >> 0)
#define	ALT_SDR_CTL_CTLCFG_MEMTYPE_SET(value)   (((value) << 0) & 0x00000007)
#define	ALT_SDR_CTL_CTLCFG_MEMBL_LSB   3
#define	ALT_SDR_CTL_CTLCFG_MEMBL_MSB   7
#define	ALT_SDR_CTL_CTLCFG_MEMBL_WIDTH   5
#define	ALT_SDR_CTL_CTLCFG_MEMBL_SET_MSK   0x000000f8
#define	ALT_SDR_CTL_CTLCFG_MEMBL_CLR_MSK   0xffffff07
#define	ALT_SDR_CTL_CTLCFG_MEMBL_RESET   0x0
#define	ALT_SDR_CTL_CTLCFG_MEMBL_GET(value)   (((value) & 0x000000f8) >> 3)
#define	ALT_SDR_CTL_CTLCFG_MEMBL_SET(value)   (((value) << 3) & 0x000000f8)
#define	ALT_SDR_CTL_CTLCFG_ADDRORDER_LSB   8
#define	ALT_SDR_CTL_CTLCFG_ADDRORDER_MSB   9
#define	ALT_SDR_CTL_CTLCFG_ADDRORDER_WIDTH   2
#define	ALT_SDR_CTL_CTLCFG_ADDRORDER_SET_MSK   0x00000300
#define	ALT_SDR_CTL_CTLCFG_ADDRORDER_CLR_MSK   0xfffffcff
#define	ALT_SDR_CTL_CTLCFG_ADDRORDER_RESET   0x0
#define	ALT_SDR_CTL_CTLCFG_ADDRORDER_GET(value)   (((value) & 0x00000300) >> 8)
#define	ALT_SDR_CTL_CTLCFG_ADDRORDER_SET(value)   (((value) << 8) & 0x00000300)
#define	ALT_SDR_CTL_CTLCFG_ECCEN_LSB   10
#define	ALT_SDR_CTL_CTLCFG_ECCEN_MSB   10
#define	ALT_SDR_CTL_CTLCFG_ECCEN_WIDTH   1
#define	ALT_SDR_CTL_CTLCFG_ECCEN_SET_MSK   0x00000400
#define	ALT_SDR_CTL_CTLCFG_ECCEN_CLR_MSK   0xfffffbff
#define	ALT_SDR_CTL_CTLCFG_ECCEN_RESET   0x0
#define	ALT_SDR_CTL_CTLCFG_ECCEN_GET(value)   (((value) & 0x00000400) >> 10)
#define	ALT_SDR_CTL_CTLCFG_ECCEN_SET(value)   (((value) << 10) & 0x00000400)
#define	ALT_SDR_CTL_CTLCFG_ECCCORREN_LSB   11
#define	ALT_SDR_CTL_CTLCFG_ECCCORREN_MSB   11
#define	ALT_SDR_CTL_CTLCFG_ECCCORREN_WIDTH   1
#define	ALT_SDR_CTL_CTLCFG_ECCCORREN_SET_MSK   0x00000800
#define	ALT_SDR_CTL_CTLCFG_ECCCORREN_CLR_MSK   0xfffff7ff
#define	ALT_SDR_CTL_CTLCFG_ECCCORREN_RESET   0x0
#define	ALT_SDR_CTL_CTLCFG_ECCCORREN_GET(value)   (((value) & 0x00000800) >> 11)
#define	ALT_SDR_CTL_CTLCFG_ECCCORREN_SET(value)   (((value) << 11) & 0x00000800)
#define	ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_LSB   12
#define	ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_MSB   12
#define	ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_WIDTH   1
#define	ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET_MSK   0x00001000
#define	ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_CLR_MSK   0xffffefff
#define	ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_RESET   0x0
#define	ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_GET(value)   (((value) & 0x00001000) >> 12)
#define	ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET(value)   (((value) << 12) & 0x00001000)
#define	ALT_SDR_CTL_CTLCFG_GENSBE_LSB   13
#define	ALT_SDR_CTL_CTLCFG_GENSBE_MSB   13
#define	ALT_SDR_CTL_CTLCFG_GENSBE_WIDTH   1
#define	ALT_SDR_CTL_CTLCFG_GENSBE_SET_MSK   0x00002000
#define	ALT_SDR_CTL_CTLCFG_GENSBE_CLR_MSK   0xffffdfff
#define	ALT_SDR_CTL_CTLCFG_GENSBE_RESET   0x0
#define	ALT_SDR_CTL_CTLCFG_GENSBE_GET(value)   (((value) & 0x00002000) >> 13)
#define	ALT_SDR_CTL_CTLCFG_GENSBE_SET(value)   (((value) << 13) & 0x00002000)
#define	ALT_SDR_CTL_CTLCFG_GENDBE_LSB   14
#define	ALT_SDR_CTL_CTLCFG_GENDBE_MSB   14
#define	ALT_SDR_CTL_CTLCFG_GENDBE_WIDTH   1
#define	ALT_SDR_CTL_CTLCFG_GENDBE_SET_MSK   0x00004000
#define	ALT_SDR_CTL_CTLCFG_GENDBE_CLR_MSK   0xffffbfff
#define	ALT_SDR_CTL_CTLCFG_GENDBE_RESET   0x0
#define	ALT_SDR_CTL_CTLCFG_GENDBE_GET(value)   (((value) & 0x00004000) >> 14)
#define	ALT_SDR_CTL_CTLCFG_GENDBE_SET(value)   (((value) << 14) & 0x00004000)
#define	ALT_SDR_CTL_CTLCFG_REORDEREN_LSB   15
#define	ALT_SDR_CTL_CTLCFG_REORDEREN_MSB   15
#define	ALT_SDR_CTL_CTLCFG_REORDEREN_WIDTH   1
#define	ALT_SDR_CTL_CTLCFG_REORDEREN_SET_MSK   0x00008000
#define	ALT_SDR_CTL_CTLCFG_REORDEREN_CLR_MSK   0xffff7fff
#define	ALT_SDR_CTL_CTLCFG_REORDEREN_RESET   0x0
#define	ALT_SDR_CTL_CTLCFG_REORDEREN_GET(value)   (((value) & 0x00008000) >> 15)
#define	ALT_SDR_CTL_CTLCFG_REORDEREN_SET(value)   (((value) << 15) & 0x00008000)
#define	ALT_SDR_CTL_CTLCFG_STARVELIMIT_LSB   16
#define	ALT_SDR_CTL_CTLCFG_STARVELIMIT_MSB   21
#define	ALT_SDR_CTL_CTLCFG_STARVELIMIT_WIDTH   6
#define	ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET_MSK   0x003f0000
#define	ALT_SDR_CTL_CTLCFG_STARVELIMIT_CLR_MSK   0xffc0ffff
#define	ALT_SDR_CTL_CTLCFG_STARVELIMIT_RESET   0x0
#define	ALT_SDR_CTL_CTLCFG_STARVELIMIT_GET(value)   (((value) & 0x003f0000) >> 16)
#define	ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET(value)   (((value) << 16) & 0x003f0000)
#define	ALT_SDR_CTL_CTLCFG_DQSTRKEN_LSB   22
#define	ALT_SDR_CTL_CTLCFG_DQSTRKEN_MSB   22
#define	ALT_SDR_CTL_CTLCFG_DQSTRKEN_WIDTH   1
#define	ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET_MSK   0x00400000
#define	ALT_SDR_CTL_CTLCFG_DQSTRKEN_CLR_MSK   0xffbfffff
#define	ALT_SDR_CTL_CTLCFG_DQSTRKEN_RESET   0x0
#define	ALT_SDR_CTL_CTLCFG_DQSTRKEN_GET(value)   (((value) & 0x00400000) >> 22)
#define	ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET(value)   (((value) << 22) & 0x00400000)
#define	ALT_SDR_CTL_CTLCFG_NODMPINS_LSB   23
#define	ALT_SDR_CTL_CTLCFG_NODMPINS_MSB   23
#define	ALT_SDR_CTL_CTLCFG_NODMPINS_WIDTH   1
#define	ALT_SDR_CTL_CTLCFG_NODMPINS_SET_MSK   0x00800000
#define	ALT_SDR_CTL_CTLCFG_NODMPINS_CLR_MSK   0xff7fffff
#define	ALT_SDR_CTL_CTLCFG_NODMPINS_RESET   0x0
#define	ALT_SDR_CTL_CTLCFG_NODMPINS_GET(value)   (((value) & 0x00800000) >> 23)
#define	ALT_SDR_CTL_CTLCFG_NODMPINS_SET(value)   (((value) << 23) & 0x00800000)
#define	ALT_SDR_CTL_CTLCFG_BURSTINTREN_LSB   24
#define	ALT_SDR_CTL_CTLCFG_BURSTINTREN_MSB   24
#define	ALT_SDR_CTL_CTLCFG_BURSTINTREN_WIDTH   1
#define	ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET_MSK   0x01000000
#define	ALT_SDR_CTL_CTLCFG_BURSTINTREN_CLR_MSK   0xfeffffff
#define	ALT_SDR_CTL_CTLCFG_BURSTINTREN_RESET   0x0
#define	ALT_SDR_CTL_CTLCFG_BURSTINTREN_GET(value)   (((value) & 0x01000000) >> 24)
#define	ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET(value)   (((value) << 24) & 0x01000000)
#define	ALT_SDR_CTL_CTLCFG_BURSTTERMEN_LSB   25
#define	ALT_SDR_CTL_CTLCFG_BURSTTERMEN_MSB   25
#define	ALT_SDR_CTL_CTLCFG_BURSTTERMEN_WIDTH   1
#define	ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET_MSK   0x02000000
#define	ALT_SDR_CTL_CTLCFG_BURSTTERMEN_CLR_MSK   0xfdffffff
#define	ALT_SDR_CTL_CTLCFG_BURSTTERMEN_RESET   0x0
#define	ALT_SDR_CTL_CTLCFG_BURSTTERMEN_GET(value)   (((value) & 0x02000000) >> 25)
#define	ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET(value)   (((value) << 25) & 0x02000000)
#define	ALT_SDR_CTL_CTLCFG_OFST   0x0
#define	ALT_SDR_CTL_DRAMTIMING1_TCWL_LSB   0
#define	ALT_SDR_CTL_DRAMTIMING1_TCWL_MSB   3
#define	ALT_SDR_CTL_DRAMTIMING1_TCWL_WIDTH   4
#define	ALT_SDR_CTL_DRAMTIMING1_TCWL_SET_MSK   0x0000000f
#define	ALT_SDR_CTL_DRAMTIMING1_TCWL_CLR_MSK   0xfffffff0
#define	ALT_SDR_CTL_DRAMTIMING1_TCWL_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING1_TCWL_GET(value)   (((value) & 0x0000000f) >> 0)
#define	ALT_SDR_CTL_DRAMTIMING1_TCWL_SET(value)   (((value) << 0) & 0x0000000f)
#define	ALT_SDR_CTL_DRAMTIMING1_TAL_LSB   4
#define	ALT_SDR_CTL_DRAMTIMING1_TAL_MSB   8
#define	ALT_SDR_CTL_DRAMTIMING1_TAL_WIDTH   5
#define	ALT_SDR_CTL_DRAMTIMING1_TAL_SET_MSK   0x000001f0
#define	ALT_SDR_CTL_DRAMTIMING1_TAL_CLR_MSK   0xfffffe0f
#define	ALT_SDR_CTL_DRAMTIMING1_TAL_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING1_TAL_GET(value)   (((value) & 0x000001f0) >> 4)
#define	ALT_SDR_CTL_DRAMTIMING1_TAL_SET(value)   (((value) << 4) & 0x000001f0)
#define	ALT_SDR_CTL_DRAMTIMING1_TCL_LSB   9
#define	ALT_SDR_CTL_DRAMTIMING1_TCL_MSB   13
#define	ALT_SDR_CTL_DRAMTIMING1_TCL_WIDTH   5
#define	ALT_SDR_CTL_DRAMTIMING1_TCL_SET_MSK   0x00003e00
#define	ALT_SDR_CTL_DRAMTIMING1_TCL_CLR_MSK   0xffffc1ff
#define	ALT_SDR_CTL_DRAMTIMING1_TCL_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING1_TCL_GET(value)   (((value) & 0x00003e00) >> 9)
#define	ALT_SDR_CTL_DRAMTIMING1_TCL_SET(value)   (((value) << 9) & 0x00003e00)
#define	ALT_SDR_CTL_DRAMTIMING1_TRRD_LSB   14
#define	ALT_SDR_CTL_DRAMTIMING1_TRRD_MSB   17
#define	ALT_SDR_CTL_DRAMTIMING1_TRRD_WIDTH   4
#define	ALT_SDR_CTL_DRAMTIMING1_TRRD_SET_MSK   0x0003c000
#define	ALT_SDR_CTL_DRAMTIMING1_TRRD_CLR_MSK   0xfffc3fff
#define	ALT_SDR_CTL_DRAMTIMING1_TRRD_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING1_TRRD_GET(value)   (((value) & 0x0003c000) >> 14)
#define	ALT_SDR_CTL_DRAMTIMING1_TRRD_SET(value)   (((value) << 14) & 0x0003c000)
#define	ALT_SDR_CTL_DRAMTIMING1_TFAW_LSB   18
#define	ALT_SDR_CTL_DRAMTIMING1_TFAW_MSB   23
#define	ALT_SDR_CTL_DRAMTIMING1_TFAW_WIDTH   6
#define	ALT_SDR_CTL_DRAMTIMING1_TFAW_SET_MSK   0x00fc0000
#define	ALT_SDR_CTL_DRAMTIMING1_TFAW_CLR_MSK   0xff03ffff
#define	ALT_SDR_CTL_DRAMTIMING1_TFAW_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING1_TFAW_GET(value)   (((value) & 0x00fc0000) >> 18)
#define	ALT_SDR_CTL_DRAMTIMING1_TFAW_SET(value)   (((value) << 18) & 0x00fc0000)
#define	ALT_SDR_CTL_DRAMTIMING1_TRFC_LSB   24
#define	ALT_SDR_CTL_DRAMTIMING1_TRFC_MSB   31
#define	ALT_SDR_CTL_DRAMTIMING1_TRFC_WIDTH   8
#define	ALT_SDR_CTL_DRAMTIMING1_TRFC_SET_MSK   0xff000000
#define	ALT_SDR_CTL_DRAMTIMING1_TRFC_CLR_MSK   0x00ffffff
#define	ALT_SDR_CTL_DRAMTIMING1_TRFC_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING1_TRFC_GET(value)   (((value) & 0xff000000) >> 24)
#define	ALT_SDR_CTL_DRAMTIMING1_TRFC_SET(value)   (((value) << 24) & 0xff000000)
#define	ALT_SDR_CTL_DRAMTIMING1_OFST   0x4
#define	ALT_SDR_CTL_DRAMTIMING2_TREFI_LSB   0
#define	ALT_SDR_CTL_DRAMTIMING2_TREFI_MSB   12
#define	ALT_SDR_CTL_DRAMTIMING2_TREFI_WIDTH   13
#define	ALT_SDR_CTL_DRAMTIMING2_TREFI_SET_MSK   0x00001fff
#define	ALT_SDR_CTL_DRAMTIMING2_TREFI_CLR_MSK   0xffffe000
#define	ALT_SDR_CTL_DRAMTIMING2_TREFI_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING2_TREFI_GET(value)   (((value) & 0x00001fff) >> 0)
#define	ALT_SDR_CTL_DRAMTIMING2_TREFI_SET(value)   (((value) << 0) & 0x00001fff)
#define	ALT_SDR_CTL_DRAMTIMING2_TRCD_LSB   13
#define	ALT_SDR_CTL_DRAMTIMING2_TRCD_MSB   16
#define	ALT_SDR_CTL_DRAMTIMING2_TRCD_WIDTH   4
#define	ALT_SDR_CTL_DRAMTIMING2_TRCD_SET_MSK   0x0001e000
#define	ALT_SDR_CTL_DRAMTIMING2_TRCD_CLR_MSK   0xfffe1fff
#define	ALT_SDR_CTL_DRAMTIMING2_TRCD_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING2_TRCD_GET(value)   (((value) & 0x0001e000) >> 13)
#define	ALT_SDR_CTL_DRAMTIMING2_TRCD_SET(value)   (((value) << 13) & 0x0001e000)
#define	ALT_SDR_CTL_DRAMTIMING2_TRP_LSB   17
#define	ALT_SDR_CTL_DRAMTIMING2_TRP_MSB   20
#define	ALT_SDR_CTL_DRAMTIMING2_TRP_WIDTH   4
#define	ALT_SDR_CTL_DRAMTIMING2_TRP_SET_MSK   0x001e0000
#define	ALT_SDR_CTL_DRAMTIMING2_TRP_CLR_MSK   0xffe1ffff
#define	ALT_SDR_CTL_DRAMTIMING2_TRP_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING2_TRP_GET(value)   (((value) & 0x001e0000) >> 17)
#define	ALT_SDR_CTL_DRAMTIMING2_TRP_SET(value)   (((value) << 17) & 0x001e0000)
#define	ALT_SDR_CTL_DRAMTIMING2_TWR_LSB   21
#define	ALT_SDR_CTL_DRAMTIMING2_TWR_MSB   24
#define	ALT_SDR_CTL_DRAMTIMING2_TWR_WIDTH   4
#define	ALT_SDR_CTL_DRAMTIMING2_TWR_SET_MSK   0x01e00000
#define	ALT_SDR_CTL_DRAMTIMING2_TWR_CLR_MSK   0xfe1fffff
#define	ALT_SDR_CTL_DRAMTIMING2_TWR_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING2_TWR_GET(value)   (((value) & 0x01e00000) >> 21)
#define	ALT_SDR_CTL_DRAMTIMING2_TWR_SET(value)   (((value) << 21) & 0x01e00000)
#define	ALT_SDR_CTL_DRAMTIMING2_TWTR_LSB   25
#define	ALT_SDR_CTL_DRAMTIMING2_TWTR_MSB   28
#define	ALT_SDR_CTL_DRAMTIMING2_TWTR_WIDTH   4
#define	ALT_SDR_CTL_DRAMTIMING2_TWTR_SET_MSK   0x1e000000
#define	ALT_SDR_CTL_DRAMTIMING2_TWTR_CLR_MSK   0xe1ffffff
#define	ALT_SDR_CTL_DRAMTIMING2_TWTR_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING2_TWTR_GET(value)   (((value) & 0x1e000000) >> 25)
#define	ALT_SDR_CTL_DRAMTIMING2_TWTR_SET(value)   (((value) << 25) & 0x1e000000)
#define	ALT_SDR_CTL_DRAMTIMING2_OFST   0x8
#define	ALT_SDR_CTL_DRAMTIMING3_TRTP_LSB   0
#define	ALT_SDR_CTL_DRAMTIMING3_TRTP_MSB   3
#define	ALT_SDR_CTL_DRAMTIMING3_TRTP_WIDTH   4
#define	ALT_SDR_CTL_DRAMTIMING3_TRTP_SET_MSK   0x0000000f
#define	ALT_SDR_CTL_DRAMTIMING3_TRTP_CLR_MSK   0xfffffff0
#define	ALT_SDR_CTL_DRAMTIMING3_TRTP_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING3_TRTP_GET(value)   (((value) & 0x0000000f) >> 0)
#define	ALT_SDR_CTL_DRAMTIMING3_TRTP_SET(value)   (((value) << 0) & 0x0000000f)
#define	ALT_SDR_CTL_DRAMTIMING3_TRAS_LSB   4
#define	ALT_SDR_CTL_DRAMTIMING3_TRAS_MSB   8
#define	ALT_SDR_CTL_DRAMTIMING3_TRAS_WIDTH   5
#define	ALT_SDR_CTL_DRAMTIMING3_TRAS_SET_MSK   0x000001f0
#define	ALT_SDR_CTL_DRAMTIMING3_TRAS_CLR_MSK   0xfffffe0f
#define	ALT_SDR_CTL_DRAMTIMING3_TRAS_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING3_TRAS_GET(value)   (((value) & 0x000001f0) >> 4)
#define	ALT_SDR_CTL_DRAMTIMING3_TRAS_SET(value)   (((value) << 4) & 0x000001f0)
#define	ALT_SDR_CTL_DRAMTIMING3_TRC_LSB   9
#define	ALT_SDR_CTL_DRAMTIMING3_TRC_MSB   14
#define	ALT_SDR_CTL_DRAMTIMING3_TRC_WIDTH   6
#define	ALT_SDR_CTL_DRAMTIMING3_TRC_SET_MSK   0x00007e00
#define	ALT_SDR_CTL_DRAMTIMING3_TRC_CLR_MSK   0xffff81ff
#define	ALT_SDR_CTL_DRAMTIMING3_TRC_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING3_TRC_GET(value)   (((value) & 0x00007e00) >> 9)
#define	ALT_SDR_CTL_DRAMTIMING3_TRC_SET(value)   (((value) << 9) & 0x00007e00)
#define	ALT_SDR_CTL_DRAMTIMING3_TMRD_LSB   15
#define	ALT_SDR_CTL_DRAMTIMING3_TMRD_MSB   18
#define	ALT_SDR_CTL_DRAMTIMING3_TMRD_WIDTH   4
#define	ALT_SDR_CTL_DRAMTIMING3_TMRD_SET_MSK   0x00078000
#define	ALT_SDR_CTL_DRAMTIMING3_TMRD_CLR_MSK   0xfff87fff
#define	ALT_SDR_CTL_DRAMTIMING3_TMRD_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING3_TMRD_GET(value)   (((value) & 0x00078000) >> 15)
#define	ALT_SDR_CTL_DRAMTIMING3_TMRD_SET(value)   (((value) << 15) & 0x00078000)
#define	ALT_SDR_CTL_DRAMTIMING3_TCCD_LSB   19
#define	ALT_SDR_CTL_DRAMTIMING3_TCCD_MSB   22
#define	ALT_SDR_CTL_DRAMTIMING3_TCCD_WIDTH   4
#define	ALT_SDR_CTL_DRAMTIMING3_TCCD_SET_MSK   0x00780000
#define	ALT_SDR_CTL_DRAMTIMING3_TCCD_CLR_MSK   0xff87ffff
#define	ALT_SDR_CTL_DRAMTIMING3_TCCD_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING3_TCCD_GET(value)   (((value) & 0x00780000) >> 19)
#define	ALT_SDR_CTL_DRAMTIMING3_TCCD_SET(value)   (((value) << 19) & 0x00780000)
#define	ALT_SDR_CTL_DRAMTIMING3_OFST   0xc
#define	ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_LSB   0
#define	ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_MSB   9
#define	ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_WIDTH   10
#define	ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET_MSK   0x000003ff
#define	ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_CLR_MSK   0xfffffc00
#define	ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_GET(value)   (((value) & 0x000003ff) >> 0)
#define	ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET(value)   (((value) << 0) & 0x000003ff)
#define	ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_LSB   10
#define	ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_MSB   19
#define	ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_WIDTH   10
#define	ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET_MSK   0x000ffc00
#define	ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_CLR_MSK   0xfff003ff
#define	ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_GET(value)   (((value) & 0x000ffc00) >> 10)
#define	ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET(value)   (((value) << 10) & 0x000ffc00)
#define	ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_LSB   20
#define	ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_MSB   23
#define	ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_WIDTH   4
#define	ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET_MSK   0x00f00000
#define	ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_CLR_MSK   0xff0fffff
#define	ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_RESET   0x0
#define	ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_GET(value)   (((value) & 0x00f00000) >> 20)
#define	ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET(value)   (((value) << 20) & 0x00f00000)
#define	ALT_SDR_CTL_DRAMTIMING4_OFST   0x10
#define	ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_LSB   0
#define	ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_MSB   15
#define	ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_WIDTH   16
#define	ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET_MSK   0x0000ffff
#define	ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_CLR_MSK   0xffff0000
#define	ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_RESET   0x0
#define	ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_GET(value)   (((value) & 0x0000ffff) >> 0)
#define	ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET(value)   (((value) << 0) & 0x0000ffff)
#define	ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_LSB   16
#define	ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_MSB   19
#define	ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_WIDTH   4
#define	ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET_MSK   0x000f0000
#define	ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_CLR_MSK   0xfff0ffff
#define	ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_RESET   0x0
#define	ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_GET(value)   (((value) & 0x000f0000) >> 16)
#define	ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET(value)   (((value) << 16) & 0x000f0000)
#define	ALT_SDR_CTL_LOWPWRTIMING_OFST   0x14
#define	ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_LSB   0
#define	ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_MSB   3
#define	ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_WIDTH   4
#define	ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET_MSK   0x0000000f
#define	ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_CLR_MSK   0xfffffff0
#define	ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_RESET   0x0
#define	ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_GET(value)   (((value) & 0x0000000f) >> 0)
#define	ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET(value)   (((value) << 0) & 0x0000000f)
#define	ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_LSB   4
#define	ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_MSB   7
#define	ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_WIDTH   4
#define	ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET_MSK   0x000000f0
#define	ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_CLR_MSK   0xffffff0f
#define	ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_RESET   0x0
#define	ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_GET(value)   (((value) & 0x000000f0) >> 4)
#define	ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET(value)   (((value) << 4) & 0x000000f0)
#define	ALT_SDR_CTL_DRAMODT_OFST   0x18
#define	ALT_SDR_CTL_DRAMADDRW_COLBITS_LSB   0
#define	ALT_SDR_CTL_DRAMADDRW_COLBITS_MSB   4
#define	ALT_SDR_CTL_DRAMADDRW_COLBITS_WIDTH   5
#define	ALT_SDR_CTL_DRAMADDRW_COLBITS_SET_MSK   0x0000001f
#define	ALT_SDR_CTL_DRAMADDRW_COLBITS_CLR_MSK   0xffffffe0
#define	ALT_SDR_CTL_DRAMADDRW_COLBITS_RESET   0x0
#define	ALT_SDR_CTL_DRAMADDRW_COLBITS_GET(value)   (((value) & 0x0000001f) >> 0)
#define	ALT_SDR_CTL_DRAMADDRW_COLBITS_SET(value)   (((value) << 0) & 0x0000001f)
#define	ALT_SDR_CTL_DRAMADDRW_ROWBITS_LSB   5
#define	ALT_SDR_CTL_DRAMADDRW_ROWBITS_MSB   9
#define	ALT_SDR_CTL_DRAMADDRW_ROWBITS_WIDTH   5
#define	ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET_MSK   0x000003e0
#define	ALT_SDR_CTL_DRAMADDRW_ROWBITS_CLR_MSK   0xfffffc1f
#define	ALT_SDR_CTL_DRAMADDRW_ROWBITS_RESET   0x0
#define	ALT_SDR_CTL_DRAMADDRW_ROWBITS_GET(value)   (((value) & 0x000003e0) >> 5)
#define	ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET(value)   (((value) << 5) & 0x000003e0)
#define	ALT_SDR_CTL_DRAMADDRW_BANKBITS_LSB   10
#define	ALT_SDR_CTL_DRAMADDRW_BANKBITS_MSB   12
#define	ALT_SDR_CTL_DRAMADDRW_BANKBITS_WIDTH   3
#define	ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET_MSK   0x00001c00
#define	ALT_SDR_CTL_DRAMADDRW_BANKBITS_CLR_MSK   0xffffe3ff
#define	ALT_SDR_CTL_DRAMADDRW_BANKBITS_RESET   0x0
#define	ALT_SDR_CTL_DRAMADDRW_BANKBITS_GET(value)   (((value) & 0x00001c00) >> 10)
#define	ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET(value)   (((value) << 10) & 0x00001c00)
#define	ALT_SDR_CTL_DRAMADDRW_CSBITS_LSB   13
#define	ALT_SDR_CTL_DRAMADDRW_CSBITS_MSB   15
#define	ALT_SDR_CTL_DRAMADDRW_CSBITS_WIDTH   3
#define	ALT_SDR_CTL_DRAMADDRW_CSBITS_SET_MSK   0x0000e000
#define	ALT_SDR_CTL_DRAMADDRW_CSBITS_CLR_MSK   0xffff1fff
#define	ALT_SDR_CTL_DRAMADDRW_CSBITS_RESET   0x0
#define	ALT_SDR_CTL_DRAMADDRW_CSBITS_GET(value)   (((value) & 0x0000e000) >> 13)
#define	ALT_SDR_CTL_DRAMADDRW_CSBITS_SET(value)   (((value) << 13) & 0x0000e000)
#define	ALT_SDR_CTL_DRAMADDRW_OFST   0x2c
#define	ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_LSB   0
#define	ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_MSB   7
#define	ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_WIDTH   8
#define	ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET_MSK   0x000000ff
#define	ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_CLR_MSK   0xffffff00
#define	ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_RESET   0x0
#define	ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_GET(value)   (((value) & 0x000000ff) >> 0)
#define	ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET(value)   (((value) << 0) & 0x000000ff)
#define	ALT_SDR_CTL_DRAMIFWIDTH_OFST   0x30
#define	ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_LSB   0
#define	ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_MSB   3
#define	ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_WIDTH   4
#define	ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET_MSK   0x0000000f
#define	ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_CLR_MSK   0xfffffff0
#define	ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_RESET   0x0
#define	ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_GET(value)   (((value) & 0x0000000f) >> 0)
#define	ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET(value)   (((value) << 0) & 0x0000000f)
#define	ALT_SDR_CTL_DRAMDEVWIDTH_OFST   0x34
#define	ALT_SDR_CTL_DRAMSTS_CALSUCCESS_LSB   0
#define	ALT_SDR_CTL_DRAMSTS_CALSUCCESS_MSB   0
#define	ALT_SDR_CTL_DRAMSTS_CALSUCCESS_WIDTH   1
#define	ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET_MSK   0x00000001
#define	ALT_SDR_CTL_DRAMSTS_CALSUCCESS_CLR_MSK   0xfffffffe
#define	ALT_SDR_CTL_DRAMSTS_CALSUCCESS_RESET   0x0
#define	ALT_SDR_CTL_DRAMSTS_CALSUCCESS_GET(value)   (((value) & 0x00000001) >> 0)
#define	ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET(value)   (((value) << 0) & 0x00000001)
#define	ALT_SDR_CTL_DRAMSTS_CALFAIL_LSB   1
#define	ALT_SDR_CTL_DRAMSTS_CALFAIL_MSB   1
#define	ALT_SDR_CTL_DRAMSTS_CALFAIL_WIDTH   1
#define	ALT_SDR_CTL_DRAMSTS_CALFAIL_SET_MSK   0x00000002
#define	ALT_SDR_CTL_DRAMSTS_CALFAIL_CLR_MSK   0xfffffffd
#define	ALT_SDR_CTL_DRAMSTS_CALFAIL_RESET   0x0
#define	ALT_SDR_CTL_DRAMSTS_CALFAIL_GET(value)   (((value) & 0x00000002) >> 1)
#define	ALT_SDR_CTL_DRAMSTS_CALFAIL_SET(value)   (((value) << 1) & 0x00000002)
#define	ALT_SDR_CTL_DRAMSTS_SBEERR_LSB   2
#define	ALT_SDR_CTL_DRAMSTS_SBEERR_MSB   2
#define	ALT_SDR_CTL_DRAMSTS_SBEERR_WIDTH   1
#define	ALT_SDR_CTL_DRAMSTS_SBEERR_SET_MSK   0x00000004
#define	ALT_SDR_CTL_DRAMSTS_SBEERR_CLR_MSK   0xfffffffb
#define	ALT_SDR_CTL_DRAMSTS_SBEERR_RESET   0x0
#define	ALT_SDR_CTL_DRAMSTS_SBEERR_GET(value)   (((value) & 0x00000004) >> 2)
#define	ALT_SDR_CTL_DRAMSTS_SBEERR_SET(value)   (((value) << 2) & 0x00000004)
#define	ALT_SDR_CTL_DRAMSTS_DBEERR_LSB   3
#define	ALT_SDR_CTL_DRAMSTS_DBEERR_MSB   3
#define	ALT_SDR_CTL_DRAMSTS_DBEERR_WIDTH   1
#define	ALT_SDR_CTL_DRAMSTS_DBEERR_SET_MSK   0x00000008
#define	ALT_SDR_CTL_DRAMSTS_DBEERR_CLR_MSK   0xfffffff7
#define	ALT_SDR_CTL_DRAMSTS_DBEERR_RESET   0x0
#define	ALT_SDR_CTL_DRAMSTS_DBEERR_GET(value)   (((value) & 0x00000008) >> 3)
#define	ALT_SDR_CTL_DRAMSTS_DBEERR_SET(value)   (((value) << 3) & 0x00000008)
#define	ALT_SDR_CTL_DRAMSTS_CORRDROP_LSB   4
#define	ALT_SDR_CTL_DRAMSTS_CORRDROP_MSB   4
#define	ALT_SDR_CTL_DRAMSTS_CORRDROP_WIDTH   1
#define	ALT_SDR_CTL_DRAMSTS_CORRDROP_SET_MSK   0x00000010
#define	ALT_SDR_CTL_DRAMSTS_CORRDROP_CLR_MSK   0xffffffef
#define	ALT_SDR_CTL_DRAMSTS_CORRDROP_RESET   0x0
#define	ALT_SDR_CTL_DRAMSTS_CORRDROP_GET(value)   (((value) & 0x00000010) >> 4)
#define	ALT_SDR_CTL_DRAMSTS_CORRDROP_SET(value)   (((value) << 4) & 0x00000010)
#define	ALT_SDR_CTL_DRAMSTS_OFST   0x38
#define	ALT_SDR_CTL_DRAMINTR_INTREN_LSB   0
#define	ALT_SDR_CTL_DRAMINTR_INTREN_MSB   0
#define	ALT_SDR_CTL_DRAMINTR_INTREN_WIDTH   1
#define	ALT_SDR_CTL_DRAMINTR_INTREN_SET_MSK   0x00000001
#define	ALT_SDR_CTL_DRAMINTR_INTREN_CLR_MSK   0xfffffffe
#define	ALT_SDR_CTL_DRAMINTR_INTREN_RESET   0x0
#define	ALT_SDR_CTL_DRAMINTR_INTREN_GET(value)   (((value) & 0x00000001) >> 0)
#define	ALT_SDR_CTL_DRAMINTR_INTREN_SET(value)   (((value) << 0) & 0x00000001)
#define	ALT_SDR_CTL_DRAMINTR_SBEMSK_LSB   1
#define	ALT_SDR_CTL_DRAMINTR_SBEMSK_MSB   1
#define	ALT_SDR_CTL_DRAMINTR_SBEMSK_WIDTH   1
#define	ALT_SDR_CTL_DRAMINTR_SBEMSK_SET_MSK   0x00000002
#define	ALT_SDR_CTL_DRAMINTR_SBEMSK_CLR_MSK   0xfffffffd
#define	ALT_SDR_CTL_DRAMINTR_SBEMSK_RESET   0x0
#define	ALT_SDR_CTL_DRAMINTR_SBEMSK_GET(value)   (((value) & 0x00000002) >> 1)
#define	ALT_SDR_CTL_DRAMINTR_SBEMSK_SET(value)   (((value) << 1) & 0x00000002)
#define	ALT_SDR_CTL_DRAMINTR_DBEMSK_LSB   2
#define	ALT_SDR_CTL_DRAMINTR_DBEMSK_MSB   2
#define	ALT_SDR_CTL_DRAMINTR_DBEMSK_WIDTH   1
#define	ALT_SDR_CTL_DRAMINTR_DBEMSK_SET_MSK   0x00000004
#define	ALT_SDR_CTL_DRAMINTR_DBEMSK_CLR_MSK   0xfffffffb
#define	ALT_SDR_CTL_DRAMINTR_DBEMSK_RESET   0x0
#define	ALT_SDR_CTL_DRAMINTR_DBEMSK_GET(value)   (((value) & 0x00000004) >> 2)
#define	ALT_SDR_CTL_DRAMINTR_DBEMSK_SET(value)   (((value) << 2) & 0x00000004)
#define	ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_LSB   3
#define	ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_MSB   3
#define	ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_WIDTH   1
#define	ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET_MSK   0x00000008
#define	ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_CLR_MSK   0xfffffff7
#define	ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_RESET   0x0
#define	ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_GET(value)   (((value) & 0x00000008) >> 3)
#define	ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET(value)   (((value) << 3) & 0x00000008)
#define	ALT_SDR_CTL_DRAMINTR_INTRCLR_LSB   4
#define	ALT_SDR_CTL_DRAMINTR_INTRCLR_MSB   4
#define	ALT_SDR_CTL_DRAMINTR_INTRCLR_WIDTH   1
#define	ALT_SDR_CTL_DRAMINTR_INTRCLR_SET_MSK   0x00000010
#define	ALT_SDR_CTL_DRAMINTR_INTRCLR_CLR_MSK   0xffffffef
#define	ALT_SDR_CTL_DRAMINTR_INTRCLR_RESET   0x0
#define	ALT_SDR_CTL_DRAMINTR_INTRCLR_GET(value)   (((value) & 0x00000010) >> 4)
#define	ALT_SDR_CTL_DRAMINTR_INTRCLR_SET(value)   (((value) << 4) & 0x00000010)
#define	ALT_SDR_CTL_DRAMINTR_OFST   0x3c
#define	ALT_SDR_CTL_SBECOUNT_COUNT_LSB   0
#define	ALT_SDR_CTL_SBECOUNT_COUNT_MSB   7
#define	ALT_SDR_CTL_SBECOUNT_COUNT_WIDTH   8
#define	ALT_SDR_CTL_SBECOUNT_COUNT_SET_MSK   0x000000ff
#define	ALT_SDR_CTL_SBECOUNT_COUNT_CLR_MSK   0xffffff00
#define	ALT_SDR_CTL_SBECOUNT_COUNT_RESET   0x0
#define	ALT_SDR_CTL_SBECOUNT_COUNT_GET(value)   (((value) & 0x000000ff) >> 0)
#define	ALT_SDR_CTL_SBECOUNT_COUNT_SET(value)   (((value) << 0) & 0x000000ff)
#define	ALT_SDR_CTL_SBECOUNT_OFST   0x40
#define	ALT_SDR_CTL_DBECOUNT_COUNT_LSB   0
#define	ALT_SDR_CTL_DBECOUNT_COUNT_MSB   7
#define	ALT_SDR_CTL_DBECOUNT_COUNT_WIDTH   8
#define	ALT_SDR_CTL_DBECOUNT_COUNT_SET_MSK   0x000000ff
#define	ALT_SDR_CTL_DBECOUNT_COUNT_CLR_MSK   0xffffff00
#define	ALT_SDR_CTL_DBECOUNT_COUNT_RESET   0x0
#define	ALT_SDR_CTL_DBECOUNT_COUNT_GET(value)   (((value) & 0x000000ff) >> 0)
#define	ALT_SDR_CTL_DBECOUNT_COUNT_SET(value)   (((value) << 0) & 0x000000ff)
#define	ALT_SDR_CTL_DBECOUNT_OFST   0x44
#define	ALT_SDR_CTL_ERRADDR_ADDR_LSB   0
#define	ALT_SDR_CTL_ERRADDR_ADDR_MSB   31
#define	ALT_SDR_CTL_ERRADDR_ADDR_WIDTH   32
#define	ALT_SDR_CTL_ERRADDR_ADDR_SET_MSK   0xffffffff
#define	ALT_SDR_CTL_ERRADDR_ADDR_CLR_MSK   0x00000000
#define	ALT_SDR_CTL_ERRADDR_ADDR_RESET   0x0
#define	ALT_SDR_CTL_ERRADDR_ADDR_GET(value)   (((value) & 0xffffffff) >> 0)
#define	ALT_SDR_CTL_ERRADDR_ADDR_SET(value)   (((value) << 0) & 0xffffffff)
#define	ALT_SDR_CTL_ERRADDR_OFST   0x48
#define	ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_LSB   0
#define	ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_MSB   7
#define	ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_WIDTH   8
#define	ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET_MSK   0x000000ff
#define	ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_CLR_MSK   0xffffff00
#define	ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_RESET   0x0
#define	ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_GET(value)   (((value) & 0x000000ff) >> 0)
#define	ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET(value)   (((value) << 0) & 0x000000ff)
#define	ALT_SDR_CTL_DROPCOUNT_OFST   0x4c
#define	ALT_SDR_CTL_DROPADDR_CORRDROPADDR_LSB   0
#define	ALT_SDR_CTL_DROPADDR_CORRDROPADDR_MSB   31
#define	ALT_SDR_CTL_DROPADDR_CORRDROPADDR_WIDTH   32
#define	ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET_MSK   0xffffffff
#define	ALT_SDR_CTL_DROPADDR_CORRDROPADDR_CLR_MSK   0x00000000
#define	ALT_SDR_CTL_DROPADDR_CORRDROPADDR_RESET   0x0
#define	ALT_SDR_CTL_DROPADDR_CORRDROPADDR_GET(value)   (((value) & 0xffffffff) >> 0)
#define	ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET(value)   (((value) << 0) & 0xffffffff)
#define	ALT_SDR_CTL_DROPADDR_OFST   0x50
#define	ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_LSB   0
#define	ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_MSB   0
#define	ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_WIDTH   1
#define	ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET_MSK   0x00000001
#define	ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_CLR_MSK   0xfffffffe
#define	ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_RESET   0x0
#define	ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_GET(value)   (((value) & 0x00000001) >> 0)
#define	ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET(value)   (((value) << 0) & 0x00000001)
#define	ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_LSB   1
#define	ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_MSB   2
#define	ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_WIDTH   2
#define	ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET_MSK   0x00000006
#define	ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_CLR_MSK   0xfffffff9
#define	ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_RESET   0x0
#define	ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_GET(value)   (((value) & 0x00000006) >> 1)
#define	ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET(value)   (((value) << 1) & 0x00000006)
#define	ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_LSB   3
#define	ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_MSB   3
#define	ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_WIDTH   1
#define	ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET_MSK   0x00000008
#define	ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_CLR_MSK   0xfffffff7
#define	ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_RESET   0x0
#define	ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_GET(value)   (((value) & 0x00000008) >> 3)
#define	ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET(value)   (((value) << 3) & 0x00000008)
#define	ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_LSB   4
#define	ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_MSB   5
#define	ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_WIDTH   2
#define	ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET_MSK   0x00000030
#define	ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_CLR_MSK   0xffffffcf
#define	ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_RESET   0x0
#define	ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_GET(value)   (((value) & 0x00000030) >> 4)
#define	ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET(value)   (((value) << 4) & 0x00000030)
#define	ALT_SDR_CTL_LOWPWREQ_OFST   0x54
#define	ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_LSB   0
#define	ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_MSB   0
#define	ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_WIDTH   1
#define	ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET_MSK   0x00000001
#define	ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_CLR_MSK   0xfffffffe
#define	ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_RESET   0x0
#define	ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_GET(value)   (((value) & 0x00000001) >> 0)
#define	ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET(value)   (((value) << 0) & 0x00000001)
#define	ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_LSB   1
#define	ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_MSB   1
#define	ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_WIDTH   1
#define	ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET_MSK   0x00000002
#define	ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_CLR_MSK   0xfffffffd
#define	ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_RESET   0x0
#define	ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_GET(value)   (((value) & 0x00000002) >> 1)
#define	ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET(value)   (((value) << 1) & 0x00000002)
#define	ALT_SDR_CTL_LOWPWRACK_OFST   0x58
#define	ALT_SDR_CTL_STATICCFG_MEMBL_LSB   0
#define	ALT_SDR_CTL_STATICCFG_MEMBL_MSB   1
#define	ALT_SDR_CTL_STATICCFG_MEMBL_WIDTH   2
#define	ALT_SDR_CTL_STATICCFG_MEMBL_SET_MSK   0x00000003
#define	ALT_SDR_CTL_STATICCFG_MEMBL_CLR_MSK   0xfffffffc
#define	ALT_SDR_CTL_STATICCFG_MEMBL_RESET   0x0
#define	ALT_SDR_CTL_STATICCFG_MEMBL_GET(value)   (((value) & 0x00000003) >> 0)
#define	ALT_SDR_CTL_STATICCFG_MEMBL_SET(value)   (((value) << 0) & 0x00000003)
#define	ALT_SDR_CTL_STATICCFG_USEECCASDATA_LSB   2
#define	ALT_SDR_CTL_STATICCFG_USEECCASDATA_MSB   2
#define	ALT_SDR_CTL_STATICCFG_USEECCASDATA_WIDTH   1
#define	ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET_MSK   0x00000004
#define	ALT_SDR_CTL_STATICCFG_USEECCASDATA_CLR_MSK   0xfffffffb
#define	ALT_SDR_CTL_STATICCFG_USEECCASDATA_RESET   0x0
#define	ALT_SDR_CTL_STATICCFG_USEECCASDATA_GET(value)   (((value) & 0x00000004) >> 2)
#define	ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET(value)   (((value) << 2) & 0x00000004)
#define	ALT_SDR_CTL_STATICCFG_APPLYCFG_LSB   3
#define	ALT_SDR_CTL_STATICCFG_APPLYCFG_MSB   3
#define	ALT_SDR_CTL_STATICCFG_APPLYCFG_WIDTH   1
#define	ALT_SDR_CTL_STATICCFG_APPLYCFG_SET_MSK   0x00000008
#define	ALT_SDR_CTL_STATICCFG_APPLYCFG_CLR_MSK   0xfffffff7
#define	ALT_SDR_CTL_STATICCFG_APPLYCFG_RESET   0x0
#define	ALT_SDR_CTL_STATICCFG_APPLYCFG_GET(value)   (((value) & 0x00000008) >> 3)
#define	ALT_SDR_CTL_STATICCFG_APPLYCFG_SET(value)   (((value) << 3) & 0x00000008)
#define	ALT_SDR_CTL_STATICCFG_OFST   0x5c
#define	ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_LSB   0
#define	ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_MSB   1
#define	ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_WIDTH   2
#define	ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET_MSK   0x00000003
#define	ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_CLR_MSK   0xfffffffc
#define	ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_RESET   0x0
#define	ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_GET(value)   (((value) & 0x00000003) >> 0)
#define	ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET(value)   (((value) << 0) & 0x00000003)
#define	ALT_SDR_CTL_CTLWIDTH_OFST   0x60
#define	ALT_SDR_CTL_PORTCFG_AUTOPCHEN_LSB   10
#define	ALT_SDR_CTL_PORTCFG_AUTOPCHEN_MSB   19
#define	ALT_SDR_CTL_PORTCFG_AUTOPCHEN_WIDTH   10
#define	ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET_MSK   0x000ffc00
#define	ALT_SDR_CTL_PORTCFG_AUTOPCHEN_CLR_MSK   0xfff003ff
#define	ALT_SDR_CTL_PORTCFG_AUTOPCHEN_RESET   0x0
#define	ALT_SDR_CTL_PORTCFG_AUTOPCHEN_GET(value)   (((value) & 0x000ffc00) >> 10)
#define	ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET(value)   (((value) << 10) & 0x000ffc00)
#define	ALT_SDR_CTL_PORTCFG_OFST   0x7c
#define	ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_LSB   0
#define	ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSB   13
#define	ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_WIDTH   14
#define	ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET_MSK   0x00003fff
#define	ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_CLR_MSK   0xffffc000
#define	ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_RESET   0x0
#define	ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_GET(value)   (((value) & 0x00003fff) >> 0)
#define	ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET(value)   (((value) << 0) & 0x00003fff)
#define	ALT_SDR_CTL_FPGAPORTRST_OFST   0x80
#define	ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_LSB   0
#define	ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_MSB   9
#define	ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_WIDTH   10
#define	ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET_MSK   0x000003ff
#define	ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_CLR_MSK   0xfffffc00
#define	ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_RESET   0x0
#define	ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_GET(value)   (((value) & 0x000003ff) >> 0)
#define	ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET(value)   (((value) << 0) & 0x000003ff)
#define	ALT_SDR_CTL_PROTPORTDEFAULT_OFST   0x8c
#define	ALT_SDR_CTL_PROTRULEADDR_LOWADDR_LSB   0
#define	ALT_SDR_CTL_PROTRULEADDR_LOWADDR_MSB   11
#define	ALT_SDR_CTL_PROTRULEADDR_LOWADDR_WIDTH   12
#define	ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET_MSK   0x00000fff
#define	ALT_SDR_CTL_PROTRULEADDR_LOWADDR_CLR_MSK   0xfffff000
#define	ALT_SDR_CTL_PROTRULEADDR_LOWADDR_RESET   0x0
#define	ALT_SDR_CTL_PROTRULEADDR_LOWADDR_GET(value)   (((value) & 0x00000fff) >> 0)
#define	ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET(value)   (((value) << 0) & 0x00000fff)
#define	ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_LSB   12
#define	ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_MSB   23
#define	ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_WIDTH   12
#define	ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET_MSK   0x00fff000
#define	ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_CLR_MSK   0xff000fff
#define	ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_RESET   0x0
#define	ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_GET(value)   (((value) & 0x00fff000) >> 12)
#define	ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET(value)   (((value) << 12) & 0x00fff000)
#define	ALT_SDR_CTL_PROTRULEADDR_OFST   0x90
#define	ALT_SDR_CTL_PROTRULEID_LOWID_LSB   0
#define	ALT_SDR_CTL_PROTRULEID_LOWID_MSB   11
#define	ALT_SDR_CTL_PROTRULEID_LOWID_WIDTH   12
#define	ALT_SDR_CTL_PROTRULEID_LOWID_SET_MSK   0x00000fff
#define	ALT_SDR_CTL_PROTRULEID_LOWID_CLR_MSK   0xfffff000
#define	ALT_SDR_CTL_PROTRULEID_LOWID_RESET   0x0
#define	ALT_SDR_CTL_PROTRULEID_LOWID_GET(value)   (((value) & 0x00000fff) >> 0)
#define	ALT_SDR_CTL_PROTRULEID_LOWID_SET(value)   (((value) << 0) & 0x00000fff)
#define	ALT_SDR_CTL_PROTRULEID_HIGHID_LSB   12
#define	ALT_SDR_CTL_PROTRULEID_HIGHID_MSB   23
#define	ALT_SDR_CTL_PROTRULEID_HIGHID_WIDTH   12
#define	ALT_SDR_CTL_PROTRULEID_HIGHID_SET_MSK   0x00fff000
#define	ALT_SDR_CTL_PROTRULEID_HIGHID_CLR_MSK   0xff000fff
#define	ALT_SDR_CTL_PROTRULEID_HIGHID_RESET   0x0
#define	ALT_SDR_CTL_PROTRULEID_HIGHID_GET(value)   (((value) & 0x00fff000) >> 12)
#define	ALT_SDR_CTL_PROTRULEID_HIGHID_SET(value)   (((value) << 12) & 0x00fff000)
#define	ALT_SDR_CTL_PROTRULEID_OFST   0x94
#define	ALT_SDR_CTL_PROTRULEDATA_SECURITY_LSB   0
#define	ALT_SDR_CTL_PROTRULEDATA_SECURITY_MSB   1
#define	ALT_SDR_CTL_PROTRULEDATA_SECURITY_WIDTH   2
#define	ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET_MSK   0x00000003
#define	ALT_SDR_CTL_PROTRULEDATA_SECURITY_CLR_MSK   0xfffffffc
#define	ALT_SDR_CTL_PROTRULEDATA_SECURITY_RESET   0x0
#define	ALT_SDR_CTL_PROTRULEDATA_SECURITY_GET(value)   (((value) & 0x00000003) >> 0)
#define	ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET(value)   (((value) << 0) & 0x00000003)
#define	ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_LSB   2
#define	ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_MSB   2
#define	ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_WIDTH   1
#define	ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET_MSK   0x00000004
#define	ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_CLR_MSK   0xfffffffb
#define	ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_RESET   0x0
#define	ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_GET(value)   (((value) & 0x00000004) >> 2)
#define	ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET(value)   (((value) << 2) & 0x00000004)
#define	ALT_SDR_CTL_PROTRULEDATA_PORTMSK_LSB   3
#define	ALT_SDR_CTL_PROTRULEDATA_PORTMSK_MSB   12
#define	ALT_SDR_CTL_PROTRULEDATA_PORTMSK_WIDTH   10
#define	ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET_MSK   0x00001ff8
#define	ALT_SDR_CTL_PROTRULEDATA_PORTMSK_CLR_MSK   0xffffe007
#define	ALT_SDR_CTL_PROTRULEDATA_PORTMSK_RESET   0x0
#define	ALT_SDR_CTL_PROTRULEDATA_PORTMSK_GET(value)   (((value) & 0x00001ff8) >> 3)
#define	ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET(value)   (((value) << 3) & 0x00001ff8)
#define	ALT_SDR_CTL_PROTRULEDATA_RULERESULT_LSB   13
#define	ALT_SDR_CTL_PROTRULEDATA_RULERESULT_MSB   13
#define	ALT_SDR_CTL_PROTRULEDATA_RULERESULT_WIDTH   1
#define	ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET_MSK   0x00002000
#define	ALT_SDR_CTL_PROTRULEDATA_RULERESULT_CLR_MSK   0xffffdfff
#define	ALT_SDR_CTL_PROTRULEDATA_RULERESULT_RESET   0x0
#define	ALT_SDR_CTL_PROTRULEDATA_RULERESULT_GET(value)   (((value) & 0x00002000) >> 13)
#define	ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET(value)   (((value) << 13) & 0x00002000)
#define	ALT_SDR_CTL_PROTRULEDATA_OFST   0x98
#define	ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_LSB   0
#define	ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_MSB   4
#define	ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_WIDTH   5
#define	ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET_MSK   0x0000001f
#define	ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_CLR_MSK   0xffffffe0
#define	ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_RESET   0x0
#define	ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_GET(value)   (((value) & 0x0000001f) >> 0)
#define	ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET(value)   (((value) << 0) & 0x0000001f)
#define	ALT_SDR_CTL_PROTRULERDWR_WRRULE_LSB   5
#define	ALT_SDR_CTL_PROTRULERDWR_WRRULE_MSB   5
#define	ALT_SDR_CTL_PROTRULERDWR_WRRULE_WIDTH   1
#define	ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET_MSK   0x00000020
#define	ALT_SDR_CTL_PROTRULERDWR_WRRULE_CLR_MSK   0xffffffdf
#define	ALT_SDR_CTL_PROTRULERDWR_WRRULE_RESET   0x0
#define	ALT_SDR_CTL_PROTRULERDWR_WRRULE_GET(value)   (((value) & 0x00000020) >> 5)
#define	ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET(value)   (((value) << 5) & 0x00000020)
#define	ALT_SDR_CTL_PROTRULERDWR_RDRULE_LSB   6
#define	ALT_SDR_CTL_PROTRULERDWR_RDRULE_MSB   6
#define	ALT_SDR_CTL_PROTRULERDWR_RDRULE_WIDTH   1
#define	ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET_MSK   0x00000040
#define	ALT_SDR_CTL_PROTRULERDWR_RDRULE_CLR_MSK   0xffffffbf
#define	ALT_SDR_CTL_PROTRULERDWR_RDRULE_RESET   0x0
#define	ALT_SDR_CTL_PROTRULERDWR_RDRULE_GET(value)   (((value) & 0x00000040) >> 6)
#define	ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET(value)   (((value) << 6) & 0x00000040)
#define	ALT_SDR_CTL_PROTRULERDWR_OFST   0x9c
#define	ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_LSB   0
#define	ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_MSB   19
#define	ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_WIDTH   20
#define	ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET_MSK   0x000fffff
#define	ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_CLR_MSK   0xfff00000
#define	ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_RESET   0x0
#define	ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_GET(value)   (((value) & 0x000fffff) >> 0)
#define	ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET(value)   (((value) << 0) & 0x000fffff)
#define	ALT_SDR_CTL_QOSLOWPRI_OFST   0xa0
#define	ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_LSB   0
#define	ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_MSB   19
#define	ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_WIDTH   20
#define	ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET_MSK   0x000fffff
#define	ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_CLR_MSK   0xfff00000
#define	ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_RESET   0x0
#define	ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_GET(value)   (((value) & 0x000fffff) >> 0)
#define	ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET(value)   (((value) << 0) & 0x000fffff)
#define	ALT_SDR_CTL_QOSHIGHPRI_OFST   0xa4
#define	ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_LSB   0
#define	ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_MSB   9
#define	ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_WIDTH   10
#define	ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET_MSK   0x000003ff
#define	ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_CLR_MSK   0xfffffc00
#define	ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_RESET   0x0
#define	ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_GET(value)   (((value) & 0x000003ff) >> 0)
#define	ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET(value)   (((value) << 0) & 0x000003ff)
#define	ALT_SDR_CTL_QOSPRIORITYEN_OFST   0xa8
#define	ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_LSB   0
#define	ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_MSB   29
#define	ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_WIDTH   30
#define	ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET_MSK   0x3fffffff
#define	ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_CLR_MSK   0xc0000000
#define	ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_RESET   0x0
#define	ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_GET(value)   (((value) & 0x3fffffff) >> 0)
#define	ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET(value)   (((value) << 0) & 0x3fffffff)
#define	ALT_SDR_CTL_MPPRIORITY_OFST   0xac
#define	ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_LSB   0
#define	ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_MSB   7
#define	ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_WIDTH   8
#define	ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET_MSK   0x000000ff
#define	ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_CLR_MSK   0xffffff00
#define	ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_RESET   0x0
#define	ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_GET(value)   (((value) & 0x000000ff) >> 0)
#define	ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET(value)   (((value) << 0) & 0x000000ff)
#define	ALT_SDR_CTL_REMAPPRIORITY_OFST   0xe0
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_LSB   0
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_MSB   31
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_WIDTH   32
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET_MSK   0xffffffff
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_CLR_MSK   0x00000000
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_RESET   0x0
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_GET(value)   (((value) & 0xffffffff) >> 0)
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET(value)   (((value) << 0) & 0xffffffff)
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST   0x0
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST))
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_LSB   0
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_MSB   17
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_WIDTH   18
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET_MSK   0x0003ffff
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_CLR_MSK   0xfffc0000
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_RESET   0x0
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_GET(value)   (((value) & 0x0003ffff) >> 0)
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET(value)   (((value) << 0) & 0x0003ffff)
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_LSB   18
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_MSB   31
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_WIDTH   14
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET_MSK   0xfffc0000
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_CLR_MSK   0x0003ffff
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_RESET   0x0
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_GET(value)   (((value) & 0xfffc0000) >> 18)
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET(value)   (((value) << 18) & 0xfffc0000)
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST   0x4
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST))
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_LSB   0
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_MSB   31
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_WIDTH   32
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET_MSK   0xffffffff
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_CLR_MSK   0x00000000
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_RESET   0x0
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_GET(value)   (((value) & 0xffffffff) >> 0)
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET(value)   (((value) << 0) & 0xffffffff)
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST   0x8
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST))
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_LSB   0
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_MSB   17
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_WIDTH   18
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET_MSK   0x0003ffff
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_CLR_MSK   0xfffc0000
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_RESET   0x0
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_GET(value)   (((value) & 0x0003ffff) >> 0)
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET(value)   (((value) << 0) & 0x0003ffff)
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST   0xc
#define	ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST))

Typedefs
typedef volatile struct ALT_SDR_CTL_CTLCFG_s	ALT_SDR_CTL_CTLCFG_t
typedef volatile struct ALT_SDR_CTL_DRAMTIMING1_s	ALT_SDR_CTL_DRAMTIMING1_t
typedef volatile struct ALT_SDR_CTL_DRAMTIMING2_s	ALT_SDR_CTL_DRAMTIMING2_t
typedef volatile struct ALT_SDR_CTL_DRAMTIMING3_s	ALT_SDR_CTL_DRAMTIMING3_t
typedef volatile struct ALT_SDR_CTL_DRAMTIMING4_s	ALT_SDR_CTL_DRAMTIMING4_t
typedef volatile struct ALT_SDR_CTL_LOWPWRTIMING_s	ALT_SDR_CTL_LOWPWRTIMING_t
typedef volatile struct ALT_SDR_CTL_DRAMODT_s	ALT_SDR_CTL_DRAMODT_t
typedef volatile struct ALT_SDR_CTL_DRAMADDRW_s	ALT_SDR_CTL_DRAMADDRW_t
typedef volatile struct ALT_SDR_CTL_DRAMIFWIDTH_s	ALT_SDR_CTL_DRAMIFWIDTH_t
typedef volatile struct ALT_SDR_CTL_DRAMDEVWIDTH_s	ALT_SDR_CTL_DRAMDEVWIDTH_t
typedef volatile struct ALT_SDR_CTL_DRAMSTS_s	ALT_SDR_CTL_DRAMSTS_t
typedef volatile struct ALT_SDR_CTL_DRAMINTR_s	ALT_SDR_CTL_DRAMINTR_t
typedef volatile struct ALT_SDR_CTL_SBECOUNT_s	ALT_SDR_CTL_SBECOUNT_t
typedef volatile struct ALT_SDR_CTL_DBECOUNT_s	ALT_SDR_CTL_DBECOUNT_t
typedef volatile struct ALT_SDR_CTL_ERRADDR_s	ALT_SDR_CTL_ERRADDR_t
typedef volatile struct ALT_SDR_CTL_DROPCOUNT_s	ALT_SDR_CTL_DROPCOUNT_t
typedef volatile struct ALT_SDR_CTL_DROPADDR_s	ALT_SDR_CTL_DROPADDR_t
typedef volatile struct ALT_SDR_CTL_LOWPWREQ_s	ALT_SDR_CTL_LOWPWREQ_t
typedef volatile struct ALT_SDR_CTL_LOWPWRACK_s	ALT_SDR_CTL_LOWPWRACK_t
typedef volatile struct ALT_SDR_CTL_STATICCFG_s	ALT_SDR_CTL_STATICCFG_t
typedef volatile struct ALT_SDR_CTL_CTLWIDTH_s	ALT_SDR_CTL_CTLWIDTH_t
typedef volatile struct ALT_SDR_CTL_PORTCFG_s	ALT_SDR_CTL_PORTCFG_t
typedef volatile struct ALT_SDR_CTL_FPGAPORTRST_s	ALT_SDR_CTL_FPGAPORTRST_t
typedef volatile struct ALT_SDR_CTL_PROTPORTDEFAULT_s	ALT_SDR_CTL_PROTPORTDEFAULT_t
typedef volatile struct ALT_SDR_CTL_PROTRULEADDR_s	ALT_SDR_CTL_PROTRULEADDR_t
typedef volatile struct ALT_SDR_CTL_PROTRULEID_s	ALT_SDR_CTL_PROTRULEID_t
typedef volatile struct ALT_SDR_CTL_PROTRULEDATA_s	ALT_SDR_CTL_PROTRULEDATA_t
typedef volatile struct ALT_SDR_CTL_PROTRULERDWR_s	ALT_SDR_CTL_PROTRULERDWR_t
typedef volatile struct ALT_SDR_CTL_QOSLOWPRI_s	ALT_SDR_CTL_QOSLOWPRI_t
typedef volatile struct ALT_SDR_CTL_QOSHIGHPRI_s	ALT_SDR_CTL_QOSHIGHPRI_t
typedef volatile struct ALT_SDR_CTL_QOSPRIORITYEN_s	ALT_SDR_CTL_QOSPRIORITYEN_t
typedef volatile struct ALT_SDR_CTL_MPPRIORITY_s	ALT_SDR_CTL_MPPRIORITY_t
typedef volatile struct ALT_SDR_CTL_REMAPPRIORITY_s	ALT_SDR_CTL_REMAPPRIORITY_t
typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s	ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_t
typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s	ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_t
typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s	ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_t
typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s	ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_t
typedef volatile struct ALT_SDR_CTL_MPWT_s	ALT_SDR_CTL_MPWT_t
typedef volatile struct ALT_SDR_CTL_MPWT_raw_s	ALT_SDR_CTL_MPWT_raw_t
typedef volatile struct ALT_SDR_CTL_s	ALT_SDR_CTL_t
typedef volatile struct ALT_SDR_CTL_raw_s	ALT_SDR_CTL_raw_t
typedef volatile struct ALT_SDR_s	ALT_SDR_t
typedef volatile struct ALT_SDR_raw_s	ALT_SDR_raw_t