RTEMS Documentation Project RTEMS CPU Architecture Supplement
5.1
  • 1. Preface
  • 2. Port Specific Information
    • 2.1. CPU Model Dependent Features
      • 2.1.1. CPU Model Name
      • 2.1.2. Floating Point Unit
    • 2.2. Multilibs
    • 2.3. Calling Conventions
      • 2.3.1. Calling Mechanism
      • 2.3.2. Register Usage
      • 2.3.3. Parameter Passing
      • 2.3.4. User-Provided Routines
    • 2.4. Memory Model
      • 2.4.1. Flat Memory Model
    • 2.5. Interrupt Processing
      • 2.5.1. Vectoring of an Interrupt Handler
      • 2.5.2. Interrupt Levels
      • 2.5.3. Disabling of Interrupts by RTEMS
    • 2.6. Default Fatal Error Processing
    • 2.7. Symmetric Multiprocessing
    • 2.8. Thread-Local Storage
    • 2.9. CPU counter
    • 2.10. Interrupt Profiling
    • 2.11. Board Support Packages
      • 2.11.1. System Reset
  • 3. ARM Specific Information
    • 3.1. CPU Model Dependent Features
      • 3.1.1. CPU Model Name
      • 3.1.2. Count Leading Zeroes Instruction
      • 3.1.3. Floating Point Unit
    • 3.2. Multilibs
    • 3.3. Calling Conventions
    • 3.4. Memory Model
    • 3.5. Interrupt Processing
      • 3.5.1. Interrupt Levels
      • 3.5.2. Interrupt Stack
    • 3.6. Default Fatal Error Processing
    • 3.7. Symmetric Multiprocessing
    • 3.8. Thread-Local Storage
  • 4. Atmel AVR Specific Information
    • 4.1. CPU Model Dependent Features
      • 4.1.1. Count Leading Zeroes Instruction
    • 4.2. Calling Conventions
      • 4.2.1. Processor Background
      • 4.2.2. Register Usage
      • 4.2.3. Parameter Passing
    • 4.3. Memory Model
    • 4.4. Interrupt Processing
      • 4.4.1. Vectoring of an Interrupt Handler
      • 4.4.2. Disabling of Interrupts by RTEMS
      • 4.4.3. Interrupt Stack
    • 4.5. Default Fatal Error Processing
    • 4.6. Symmetric Multiprocessing
    • 4.7. Thread-Local Storage
    • 4.8. Board Support Packages
      • 4.8.1. System Reset
  • 5. Blackfin Specific Information
    • 5.1. CPU Model Dependent Features
      • 5.1.1. Count Leading Zeroes Instruction
    • 5.2. Calling Conventions
      • 5.2.1. Processor Background
      • 5.2.2. Register Usage
      • 5.2.3. Parameter Passing
    • 5.3. Memory Model
    • 5.4. Interrupt Processing
      • 5.4.1. Vectoring of an Interrupt Handler
      • 5.4.2. Disabling of Interrupts by RTEMS
      • 5.4.3. Interrupt Stack
    • 5.5. Default Fatal Error Processing
    • 5.6. Symmetric Multiprocessing
    • 5.7. Thread-Local Storage
    • 5.8. Board Support Packages
      • 5.8.1. System Reset
  • 6. Epiphany Specific Information
    • 6.1. Calling Conventions
      • 6.1.1. Floating Point Unit
    • 6.2. Memory Model
    • 6.3. Interrupt Processing
      • 6.3.1. Interrupt Levels
      • 6.3.2. Interrupt Stack
    • 6.4. Default Fatal Error Processing
    • 6.5. Symmetric Multiprocessing
  • 7. Intel/AMD x86 Specific Information
    • 7.1. CPU Model Dependent Features
      • 7.1.1. bswap Instruction
    • 7.2. Calling Conventions
      • 7.2.1. Processor Background
      • 7.2.2. Calling Mechanism
      • 7.2.3. Register Usage
      • 7.2.4. Parameter Passing
    • 7.3. Memory Model
      • 7.3.1. Flat Memory Model
    • 7.4. Interrupt Processing
      • 7.4.1. Vectoring of Interrupt Handler
      • 7.4.2. Interrupt Stack Frame
      • 7.4.3. Interrupt Levels
      • 7.4.4. Interrupt Stack
    • 7.5. Default Fatal Error Processing
    • 7.6. Symmetric Multiprocessing
    • 7.7. Thread-Local Storage
    • 7.8. Board Support Packages
      • 7.8.1. System Reset
      • 7.8.2. Processor Initialization
  • 8. Lattice Mico32 Specific Information
    • 8.1. CPU Model Dependent Features
    • 8.2. Register Architecture
    • 8.3. Calling Conventions
      • 8.3.1. Calling Mechanism
      • 8.3.2. Register Usage
      • 8.3.3. Parameter Passing
    • 8.4. Memory Model
    • 8.5. Interrupt Processing
    • 8.6. Default Fatal Error Processing
    • 8.7. Symmetric Multiprocessing
    • 8.8. Thread-Local Storage
    • 8.9. Board Support Packages
      • 8.9.1. System Reset
  • 9. Renesas M32C Specific Information
  • 10. M68xxx and Coldfire Specific Information
    • 10.1. CPU Model Dependent Features
      • 10.1.1. BFFFO Instruction
      • 10.1.2. Vector Base Register
      • 10.1.3. Separate Stacks
      • 10.1.4. Pre-Indexing Address Mode
      • 10.1.5. Extend Byte to Long Instruction
    • 10.2. Calling Conventions
      • 10.2.1. Calling Mechanism
      • 10.2.2. Register Usage
      • 10.2.3. Parameter Passing
    • 10.3. Memory Model
    • 10.4. Interrupt Processing
      • 10.4.1. Vectoring of an Interrupt Handler
        • 10.4.1.1. Models Without Separate Interrupt Stacks
        • 10.4.1.2. Models With Separate Interrupt Stacks
      • 10.4.2. CPU Models Without VBR and RAM at 0
      • 10.4.3. Interrupt Levels
    • 10.5. Default Fatal Error Processing
    • 10.6. Symmetric Multiprocessing
    • 10.7. Thread-Local Storage
    • 10.8. Board Support Packages
      • 10.8.1. System Reset
      • 10.8.2. Processor Initialization
  • 11. Xilinx MicroBlaze Specific Information
    • 11.1. Symmetric Multiprocessing
    • 11.2. Thread-Local Storage
  • 12. MIPS Specific Information
    • 12.1. CPU Model Dependent Features
      • 12.1.1. Another Optional Feature
    • 12.2. Calling Conventions
      • 12.2.1. Processor Background
      • 12.2.2. Calling Mechanism
      • 12.2.3. Register Usage
      • 12.2.4. Parameter Passing
    • 12.3. Memory Model
      • 12.3.1. Flat Memory Model
    • 12.4. Interrupt Processing
      • 12.4.1. Vectoring of an Interrupt Handler
      • 12.4.2. Interrupt Levels
    • 12.5. Default Fatal Error Processing
    • 12.6. Symmetric Multiprocessing
    • 12.7. Thread-Local Storage
    • 12.8. Board Support Packages
      • 12.8.1. System Reset
      • 12.8.2. Processor Initialization
  • 13. Altera Nios II Specific Information
    • 13.1. Symmetric Multiprocessing
    • 13.2. Thread-Local Storage
  • 14. OpenRISC 1000 Specific Information
    • 14.1. Calling Conventions
      • 14.1.1. Floating Point Unit
    • 14.2. Memory Model
    • 14.3. Interrupt Processing
      • 14.3.1. Interrupt Levels
      • 14.3.2. Interrupt Stack
    • 14.4. Default Fatal Error Processing
    • 14.5. Symmetric Multiprocessing
  • 15. PowerPC Specific Information
    • 15.1. Multilibs
    • 15.2. Application Binary Interface
    • 15.3. Special Registers
    • 15.4. Memory Model
    • 15.5. Interrupt Processing
      • 15.5.1. Interrupt Levels
      • 15.5.2. Interrupt Stack
    • 15.6. Default Fatal Error Processing
    • 15.7. Symmetric Multiprocessing
    • 15.8. Thread-Local Storage
    • 15.9. 64-bit Caveats
  • 16. RISC-V Specific Information
    • 16.1. Calling Conventions
    • 16.2. Multilibs
    • 16.3. Interrupt Processing
      • 16.3.1. Interrupt Levels
      • 16.3.2. Interrupt Stack
    • 16.4. Default Fatal Error Processing
    • 16.5. Symmetric Multiprocessing
    • 16.6. Thread-Local Storage
  • 17. SuperH Specific Information
    • 17.1. CPU Model Dependent Features
      • 17.1.1. Another Optional Feature
    • 17.2. Calling Conventions
      • 17.2.1. Calling Mechanism
      • 17.2.2. Register Usage
      • 17.2.3. Parameter Passing
    • 17.3. Memory Model
      • 17.3.1. Flat Memory Model
    • 17.4. Interrupt Processing
      • 17.4.1. Vectoring of an Interrupt Handler
      • 17.4.2. Interrupt Levels
    • 17.5. Default Fatal Error Processing
    • 17.6. Symmetric Multiprocessing
    • 17.7. Thread-Local Storage
    • 17.8. Board Support Packages
      • 17.8.1. System Reset
      • 17.8.2. Processor Initialization
  • 18. SPARC Specific Information
    • 18.1. CPU Model Dependent Features
      • 18.1.1. CPU Model Feature Flags
        • 18.1.1.1. CPU Model Name
        • 18.1.1.2. Floating Point Unit
        • 18.1.1.3. Bitscan Instruction
        • 18.1.1.4. Number of Register Windows
        • 18.1.1.5. Low Power Mode
      • 18.1.2. CPU Model Implementation Notes
    • 18.2. Calling Conventions
      • 18.2.1. Programming Model
        • 18.2.1.1. Non-Floating Point Registers
        • 18.2.1.2. Floating Point Registers
        • 18.2.1.3. Special Registers
      • 18.2.2. Register Windows
      • 18.2.3. Call and Return Mechanism
      • 18.2.4. Calling Mechanism
      • 18.2.5. Register Usage
      • 18.2.6. Parameter Passing
      • 18.2.7. User-Provided Routines
    • 18.3. Memory Model
      • 18.3.1. Flat Memory Model
    • 18.4. Interrupt Processing
      • 18.4.1. Synchronous Versus Asynchronous Traps
      • 18.4.2. Vectoring of Interrupt Handler
      • 18.4.3. Traps and Register Windows
      • 18.4.4. Interrupt Levels
      • 18.4.5. Disabling of Interrupts by RTEMS
      • 18.4.6. Interrupt Stack
    • 18.5. Default Fatal Error Processing
      • 18.5.1. Default Fatal Error Handler Operations
    • 18.6. Symmetric Multiprocessing
    • 18.7. Thread-Local Storage
    • 18.8. Board Support Packages
      • 18.8.1. System Reset
      • 18.8.2. Processor Initialization
    • 18.9. Stacks and Register Windows
      • 18.9.1. General Structure
      • 18.9.2. Register Semantics
      • 18.9.3. Register Windows and the Stack
      • 18.9.4. Procedure epilogue and prologue
      • 18.9.5. Procedures, stacks, and debuggers
      • 18.9.6. The window overflow and underflow traps
  • 19. SPARC-64 Specific Information
    • 19.1. CPU Model Dependent Features
      • 19.1.1. CPU Model Feature Flags
        • 19.1.1.1. CPU Model Name
        • 19.1.1.2. Floating Point Unit
        • 19.1.1.3. Number of Register Windows
      • 19.1.2. CPU Model Implementation Notes
        • 19.1.2.1. sun4u Notes
      • 19.1.3. sun4v Notes
    • 19.2. Calling Conventions
      • 19.2.1. Programming Model
        • 19.2.1.1. Non-Floating Point Registers
        • 19.2.1.2. Floating Point Registers
        • 19.2.1.3. Special Registers
      • 19.2.2. Register Windows
      • 19.2.3. Call and Return Mechanism
      • 19.2.4. Calling Mechanism
      • 19.2.5. Register Usage
      • 19.2.6. Parameter Passing
      • 19.2.7. User-Provided Routines
    • 19.3. Memory Model
      • 19.3.1. Flat Memory Model
    • 19.4. Interrupt Processing
      • 19.4.1. Synchronous Versus Asynchronous Traps
      • 19.4.2. Vectoring of Interrupt Handler
      • 19.4.3. Traps and Register Windows
      • 19.4.4. Interrupt Levels
      • 19.4.5. Disabling of Interrupts by RTEMS
      • 19.4.6. Interrupt Stack
    • 19.5. Default Fatal Error Processing
      • 19.5.1. Default Fatal Error Handler Operations
    • 19.6. Symmetric Multiprocessing
    • 19.7. Thread-Local Storage
    • 19.8. Board Support Packages
      • 19.8.1. HelenOS and Open Firmware
  • 20. References
Index
RTEMS CPU Architecture Supplement
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