Bug Summary

File:/home/joel/rtems-4.11-work/build/rtems/c/src/../../cpukit/score/cpu/sparc/cpu.c
Location:line 295, column 5
Description:Value stored to 'the_size' is never read

Annotated Source Code

1/*
2 * SPARC Dependent Source
3 *
4 * COPYRIGHT (c) 1989-2007.
5 * On-Line Applications Research Corporation (OAR).
6 *
7 * The license and distribution terms for this file may be
8 * found in the file LICENSE in this distribution or at
9 * http://www.rtems.com/license/LICENSE.
10 *
11 * $Id: cpu.c,v 1.30 2010/03/27 15:03:09 joel Exp $
12 */
13
14#ifdef HAVE_CONFIG_H1
15#include "config.h"
16#endif
17
18#include <rtems/system.h>
19#include <rtems/score/isr.h>
20#include <rtems/rtems/cache.h>
21
22/*
23 * This initializes the set of opcodes placed in each trap
24 * table entry. The routine which installs a handler is responsible
25 * for filling in the fields for the _handler address and the _vector
26 * trap type.
27 *
28 * The constants following this structure are masks for the fields which
29 * must be filled in when the handler is installed.
30 */
31
32const CPU_Trap_table_entry _CPU_Trap_slot_template = {
33 0xa1480000, /* mov %psr, %l0 */
34 0x29000000, /* sethi %hi(_handler), %l4 */
35 0x81c52000, /* jmp %l4 + %lo(_handler) */
36 0xa6102000 /* mov _vector, %l3 */
37};
38
39/*PAGE
40 *
41 * _CPU_Initialize
42 *
43 * This routine performs processor dependent initialization.
44 *
45 * INPUT PARAMETERS: NONE
46 *
47 * Output Parameters: NONE
48 *
49 * NOTE: There is no need to save the pointer to the thread dispatch routine.
50 * The SPARC's assembly code can reference it directly with no problems.
51 */
52
53void _CPU_Initialize(void)
54{
55#if (SPARC_HAS_FPU1 == 1)
56 Context_Control_fp *pointer;
57
58 /*
59 * This seems to be the most appropriate way to obtain an initial
60 * FP context on the SPARC. The NULL fp context is copied it to
61 * the task's FP context during Context_Initialize.
62 */
63
64 pointer = &_CPU_Null_fp_context;
65 _CPU_Context_save_fp( &pointer );
66#endif
67
68 /*
69 * Since no tasks have been created yet and no interrupts have occurred,
70 * there is no way that the currently executing thread can have an
71 * _ISR_Dispatch stack frame on its stack.
72 */
73 _CPU_ISR_Dispatch_disable = 0;
74}
75
76/*PAGE
77 *
78 * _CPU_ISR_Get_level
79 *
80 * Input Parameters: NONE
81 *
82 * Output Parameters:
83 * returns the current interrupt level (PIL field of the PSR)
84 */
85
86uint32_t _CPU_ISR_Get_level( void )
87{
88 uint32_t level;
89
90 sparc_get_interrupt_level( level )do { register uint32_t _psr_level = 0; do { (_psr_level) = 0;
asm volatile( "rd %%psr, %0" : "=r" (_psr_level) : "0" (_psr_level
) ); } while ( 0 ); (level) = (_psr_level & 0x00000F00) >>
8; } while ( 0 );
91
92 return level;
93}
94
95/*PAGE
96 *
97 * _CPU_ISR_install_raw_handler
98 *
99 * This routine installs the specified handler as a "raw" non-executive
100 * supported trap handler (a.k.a. interrupt service routine).
101 *
102 * Input Parameters:
103 * vector - trap table entry number plus synchronous
104 * vs. asynchronous information
105 * new_handler - address of the handler to be installed
106 * old_handler - pointer to an address of the handler previously installed
107 *
108 * Output Parameters: NONE
109 * *new_handler - address of the handler previously installed
110 *
111 * NOTE:
112 *
113 * On the SPARC, there are really only 256 vectors. However, the executive
114 * has no easy, fast, reliable way to determine which traps are synchronous
115 * and which are asynchronous. By default, synchronous traps return to the
116 * instruction which caused the interrupt. So if you install a software
117 * trap handler as an executive interrupt handler (which is desirable since
118 * RTEMS takes care of window and register issues), then the executive needs
119 * to know that the return address is to the trap rather than the instruction
120 * following the trap.
121 *
122 * So vectors 0 through 255 are treated as regular asynchronous traps which
123 * provide the "correct" return address. Vectors 256 through 512 are assumed
124 * by the executive to be synchronous and to require that the return address
125 * be fudged.
126 *
127 * If you use this mechanism to install a trap handler which must reexecute
128 * the instruction which caused the trap, then it should be installed as
129 * an asynchronous trap. This will avoid the executive changing the return
130 * address.
131 */
132
133void _CPU_ISR_install_raw_handler(
134 uint32_t vector,
135 proc_ptr new_handler,
136 proc_ptr *old_handler
137)
138{
139 uint32_t real_vector;
140 CPU_Trap_table_entry *tbr;
141 CPU_Trap_table_entry *slot;
142 uint32_t u32_tbr;
143 uint32_t u32_handler;
144
145 /*
146 * Get the "real" trap number for this vector ignoring the synchronous
147 * versus asynchronous indicator included with our vector numbers.
148 */
149
150 real_vector = SPARC_REAL_TRAP_NUMBER( vector )((vector) % 256);
151
152 /*
153 * Get the current base address of the trap table and calculate a pointer
154 * to the slot we are interested in.
155 */
156
157 sparc_get_tbr( u32_tbr )do { (u32_tbr) = 0; asm volatile( "rd %%tbr, %0" : "=r" (u32_tbr
) : "0" (u32_tbr) ); } while ( 0 );
158
159 u32_tbr &= 0xfffff000;
160
161 tbr = (CPU_Trap_table_entry *) u32_tbr;
162
163 slot = &tbr[ real_vector ];
164
165 /*
166 * Get the address of the old_handler from the trap table.
167 *
168 * NOTE: The old_handler returned will be bogus if it does not follow
169 * the RTEMS model.
170 */
171
172#define HIGH_BITS_MASK0xFFFFFC00 0xFFFFFC00
173#define HIGH_BITS_SHIFT10 10
174#define LOW_BITS_MASK0x000003FF 0x000003FF
175
176 if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) {
177 u32_handler =
178 (slot->sethi_of_handler_to_l4 << HIGH_BITS_SHIFT10) |
179 (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK0x000003FF);
180 *old_handler = (proc_ptr) u32_handler;
181 } else
182 *old_handler = 0;
183
184 /*
185 * Copy the template to the slot and then fix it.
186 */
187
188 *slot = _CPU_Trap_slot_template;
189
190 u32_handler = (uint32_t) new_handler;
191
192 slot->mov_vector_l3 |= vector;
193 slot->sethi_of_handler_to_l4 |=
194 (u32_handler & HIGH_BITS_MASK0xFFFFFC00) >> HIGH_BITS_SHIFT10;
195 slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK0x000003FF);
196
197 /* need to flush icache after this !!! */
198
199 rtems_cache_invalidate_entire_instruction();
200
201}
202
203/*PAGE
204 *
205 * _CPU_ISR_install_vector
206 *
207 * This kernel routine installs the RTEMS handler for the
208 * specified vector.
209 *
210 * Input parameters:
211 * vector - interrupt vector number
212 * new_handler - replacement ISR for this vector number
213 * old_handler - pointer to former ISR for this vector number
214 *
215 * Output parameters:
216 * *old_handler - former ISR for this vector number
217 *
218 */
219
220void _CPU_ISR_install_vector(
221 uint32_t vector,
222 proc_ptr new_handler,
223 proc_ptr *old_handler
224)
225{
226 uint32_t real_vector;
227 proc_ptr ignored;
228
229 /*
230 * Get the "real" trap number for this vector ignoring the synchronous
231 * versus asynchronous indicator included with our vector numbers.
232 */
233
234 real_vector = SPARC_REAL_TRAP_NUMBER( vector )((vector) % 256);
235
236 /*
237 * Return the previous ISR handler.
238 */
239
240 *old_handler = _ISR_Vector_table[ real_vector ];
241
242 /*
243 * Install the wrapper so this ISR can be invoked properly.
244 */
245
246 _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
247
248 /*
249 * We put the actual user ISR address in '_ISR_vector_table'. This will
250 * be used by the _ISR_Handler so the user gets control.
251 */
252
253 _ISR_Vector_table[ real_vector ] = new_handler;
254}
255
256/*PAGE
257 *
258 * _CPU_Context_Initialize
259 *
260 * This kernel routine initializes the basic non-FP context area associated
261 * with each thread.
262 *
263 * Input parameters:
264 * the_context - pointer to the context area
265 * stack_base - address of memory for the SPARC
266 * size - size in bytes of the stack area
267 * new_level - interrupt level for this context area
268 * entry_point - the starting execution point for this this context
269 * is_fp - TRUE if this context is associated with an FP thread
270 *
271 * Output parameters: NONE
272 */
273
274void _CPU_Context_Initialize(
275 Context_Control *the_context,
276 uint32_t *stack_base,
277 uint32_t size,
278 uint32_t new_level,
279 void *entry_point,
280 bool_Bool is_fp
281)
282{
283 uint32_t stack_high; /* highest "stack aligned" address */
284 uint32_t the_size;
285 uint32_t tmp_psr;
286
287 /*
288 * On CPUs with stacks which grow down (i.e. SPARC), we build the stack
289 * based on the stack_high address.
290 */
291
292 stack_high = ((uint32_t)(stack_base) + size);
293 stack_high &= ~(CPU_STACK_ALIGNMENT16 - 1);
294
295 the_size = size & ~(CPU_STACK_ALIGNMENT16 - 1);
Value stored to 'the_size' is never read
296
297 /*
298 * See the README in this directory for a diagram of the stack.
299 */
300
301 the_context->o7 = ((uint32_t) entry_point) - 8;
302 the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE0x60;
303 the_context->i6_fp = 0;
304
305 /*
306 * Build the PSR for the task. Most everything can be 0 and the
307 * CWP is corrected during the context switch.
308 *
309 * The EF bit determines if the floating point unit is available.
310 * The FPU is ONLY enabled if the context is associated with an FP task
311 * and this SPARC model has an FPU.
312 */
313
314 sparc_get_psr( tmp_psr )do { (tmp_psr) = 0; asm volatile( "rd %%psr, %0" : "=r" (tmp_psr
) : "0" (tmp_psr) ); } while ( 0 );
315 tmp_psr &= ~SPARC_PSR_PIL_MASK0x00000F00;
316 tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK0x00000F00;
317 tmp_psr &= ~SPARC_PSR_EF_MASK0x00001000; /* disabled by default */
318
319#if (SPARC_HAS_FPU1 == 1)
320 /*
321 * If this bit is not set, then a task gets a fault when it accesses
322 * a floating point register. This is a nice way to detect floating
323 * point tasks which are not currently declared as such.
324 */
325
326 if ( is_fp )
327 tmp_psr |= SPARC_PSR_EF_MASK0x00001000;
328#endif
329 the_context->psr = tmp_psr;
330
331 /*
332 * Since THIS thread is being created, there is no way that THIS
333 * thread can have an _ISR_Dispatch stack frame on its stack.
334 */
335 the_context->isr_dispatch_disable = 0;
336}