RTEMS 4.9.2 On-Line Library

Intel/AMD x86 Specific Information Vectoring of Interrupt Handler

RTEMS CPU Architecture Supplement

4.4.1: Vectoring of Interrupt Handler

Although the i386 supports multiple privilege levels, RTEMS and all user software executes at privilege level 0. This decision was made by the RTEMS designers to enhance compatibility with processors which do not provide sophisticated protection facilities like those of the i386. This decision greatly simplifies the discussion of i386 processing, as one need only consider interrupts without privilege transitions.

Upon receipt of an interrupt the i386 automatically performs the following actions:

pushes the EFLAGS register
pushes the far address of the interrupted instruction
vectors to the interrupt service routine (ISR).

A nested interrupt is processed similarly by the i386.

RTEMS CPU Architecture Supplement