RTEMS ARM Applications Supplement
All times reported except for the maximum period interrupts are disabled by RTEMS were measured using a Motorola MYBSP CPU board. The MYBSP is a 100 Mhz board with SDRAM and no numeric coprocessor. A countdown timer on this board was used to measure elapsed time with a 20 nanosecond resolution. All sources of hardware interrupts were disabled, although the interrupt level of the ARM microprocessor allows all interrupts.
The maximum period interrupts are disabled was measured by summing the number of CPU cycles required by each assembly language instruction executed while interrupts were disabled. The worst case times of the ARM9DTMI microprocessor were used for each instruction. Zero wait state memory was assumed. The total CPU cycles executed with interrupts disabled, including the instructions to disable and enable interrupts, was divided by TBD to simulate a TBD Mhz processor. It should be noted that the worst case instruction times assume that the internal cache is disabled and that no instructions overlap.
RTEMS ARM Applications Supplement
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