RTEMS ARM Applications Supplement
The maximum period with interrupts disabled within RTEMS is less than TBD microseconds including the instructions which disable and re-enable interrupts. The time required for the processor to vector an interrupt and for the RTEMS entry overhead before invoking the user's interrupt handler are a total of unavailable microseconds. These combine to yield a worst case interrupt latency of less than TBD + unavailable microseconds at 100 Mhz. [NOTE: The maximum period with interrupts disabled was last determined for Release ss-20020301.]
It should be noted again that the maximum period with interrupts disabled within RTEMS is hand-timed and based upon worst case (i.e. CPU cache disabled and no instruction overlap) times for a 100 Mhz processor. The interrupt vector and entry overhead time was generated on an MYBSP benchmark platform using the Multiprocessing Communications registers to generate as the interrupt source.
RTEMS ARM Applications Supplement
Copyright © 1988-2004 OAR Corporation