RTEMS PowerPC Applications Supplement
All times reported in this chapter were measured using a DMV177 board. All data and code caching was disabled. This results in very deterministic times which represent the worst possible performance. Many embedded applications disable caching to insure that execution times are repeatable. Moreover, the JTAG port on certain revisions of the PowerPC 603e does not operate properly if caching is enabled. Thus during development and debug, caching must be off.
The PowerPC decrementer register was was used to gather all timing information. In the PowerPC architecture, this register typically counts something like CPU cycles or is a function of the clock speed. On the PPC603e decrements once for every four (4) bus cycles. On the DMV177, the bus operates at a clock speed of 33 Mhz. This result in a very accurate number since it is a function of the microprocessor itself. Thus all measurements in this chapter are reported as the actual number of decrementer clicks reported.
To convert the numbers reported to microseconds, one should divide the number reported by 8.650752. This number was derived as shown below:
((33 * 1048576) / 1000000) / 4 = 8.650752
All sources of hardware interrupts were disabled, although traps were enabled and the interrupt level of the PowerPC allows all interrupts.
RTEMS PowerPC Applications Supplement
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