Upon receipt of an interrupt the PA-RISC
automatically performs the following actions:
The PSW (Program Status Word) is saved in the IPSW
(Interrupt Program Status Word).
The current privilege level is set to 0.
The following defined bits in the PSW are set:
E bit is set to the default endian bit
M bit is set to 1 if the interrupt is a high-priority
machine check and 0 otherwise
Q bit is set to zero thuse freezing the IIA
(Instruction Address) queues
C and D bits are set to zero thus disabling all
protection and translation.
I bit is set to zero this disabling all external,
powerfail, and low-priority machine check interrupts.
All others bits are set to zero.
General purpose registers r1, r8, r9, r16, r17, r24, and
r25 are copied to the shadow registers.
Execution begins at the address given by the formula:
Interruption Vector Address + (32 * interrupt vector number).
Once the processor has completed the actions it is is
required to perform for each interrupt, the RTEMS interrupt
management code (the beginning of which is stored in the
Interruption Vector Table) gains control and performs the
following actions upon each interrupt:
returns the processor to "virtual mode" thus reenabling
all code and data address translation.
saves all necessary interrupt state information
saves all floating point registers
saves all integer registers
switches the current stack to the interrupt stack
dispatches to the appropriate user provided interrupt
service routine (ISR). If the ISR was installed with the
interrupt_catch directive, then it will be executed at this.
Because, the RTEMS interrupt handler saves all registers which
are not preserved according to the calling conventions and
invokes the application's ISR, the ISR can easily be written in
a high-level language.
RTEMS refers to the combination of the interrupt
state information and registers saved when vectoring an
interrupt as the Interrupt Stack Frame (ISF). A nested
interrupt is processed similarly by the PA-RISC and RTEMS with
the exception that the nested interrupt occurred while executing
on the interrupt stack and, thus, the current stack need not be
switched.
RTEMS Hewlett Packard PA-RISC Applications Supplement