RTEMS Porting Guide
RTEMS is designed assuming that a CPU family has a level associated with interrupts. Interrupts below the current interrupt level are masked and do not interrupt the CPU until the interrupt level is lowered. This design provides for 256 distinct interrupt levels even though most CPU implementations support far fewer levels. Interrupt level 0 is assumed to map to the hardware settings for all interrupts enabled.
Over the years that RTEMS has been available, there has been much discussion on how to handle CPU families which support very few interrupt levels such as the i386, PowerPC, and HP-PA RISC. XXX
RTEMS Porting Guide
Copyright © 1988-2004 OAR Corporation